Added core program counter test. Also fixed the core not putting any of the core in the macro. This was caused by the unimplemented JTAG device not sending a signal to the core management, preventing it from ever allowing the core to run, resulting it being optimised away.
diff --git a/docs/Testing/Testing.md b/docs/Testing/Testing.md
index 32fe57b..1154da7 100644
--- a/docs/Testing/Testing.md
+++ b/docs/Testing/Testing.md
@@ -41,8 +41,13 @@
- Program Counter
- Write to program counter
- Check that the program counter is correct
+ - Write NOP for step (this does require instruction reads to work)
- Step core
- - Check that program counter is correct
+ - Check that the program counter is correct
+ - Jump the program counter
+ - Check that the program counter is correct
+ - Free run the program counter
+ - Check that the program counter increases
- Set GPIO high if pass
- Registers
- Write to r0, r1, r2
diff --git a/verilog/dv/corePC/Makefile b/verilog/dv/corePC/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/corePC/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/corePC/corePC.c b/verilog/dv/corePC/corePC.c
new file mode 100644
index 0000000..5f78d80
--- /dev/null
+++ b/verilog/dv/corePC/corePC.c
@@ -0,0 +1,237 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+/*
+ IO Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+#define GPIO0_OE_ADDR ((uint32_t*)0x33031000)
+#define GPIO0_OUTPUT_ADDR ((uint32_t*)0x33031004)
+#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031008)
+#define GPIO1_OE_ADDR ((uint32_t*)0x33032000)
+#define GPIO1_OUTPUT_ADDR ((uint32_t*)0x33032004)
+#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032008)
+
+#define GPIO0_OE (*GPIO0_OE_ADDR)
+#define GPIO0_OUTPUT (*GPIO0_OUTPUT_ADDR)
+#define GPIO0_INPUT (*GPIO0_INPUT_ADDR)
+#define GPIO1_OE (*GPIO1_OE_ADDR)
+#define GPIO1_OUTPUT (*GPIO1_OUTPUT_ADDR)
+#define GPIO1_INPUT (*GPIO1_INPUT_ADDR)
+
+#define CORE0_CONFIG_ADDR ((uint32_t*)0x30800000)
+#define CORE0_STATUS_ADDR ((uint32_t*)0x30800004)
+#define CORE0_REG_PC_ADDR ((uint32_t*)0x30810000)
+#define CORE0_REG_JUMP_ADDR ((uint32_t*)0x30810004)
+#define CORE0_REG_STEP_ADDR ((uint32_t*)0x30810008)
+#define CORE0_REG_INSTR_ADDR ((uint32_t*)0x30810010)
+#define CORE0_REG_IREG_ADDR ((uint32_t*)0x30811000)
+#define CORE0_SRAM_ADDR ((uint32_t*)0x30000000)
+
+#define CORE1_CONFIG_ADDR ((uint32_t*)0x31800000)
+#define CORE1_STATUS_ADDR ((uint32_t*)0x31800004)
+#define CORE1_REG_PC_ADDR ((uint32_t*)0x31810000)
+#define CORE1_REG_JUMP_ADDR ((uint32_t*)0x31810004)
+#define CORE1_REG_STEP_ADDR ((uint32_t*)0x31810008)
+#define CORE1_REG_INSTR_ADDR ((uint32_t*)0x31810010)
+#define CORE1_REG_IREG_ADDR ((uint32_t*)0x31811000)
+#define CORE1_SRAM_ADDR ((uint32_t*)0x31000000)
+
+#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
+#define MPRJ_WB_DATA_LOCATION 0x30008000
+
+#define CORE_RUN 0x1
+#define CORE_HALT 0x0
+#define CORE_RUNNING_NOERROR 0x10
+
+#define RV32I_NOP 0x00000013
+
+void wbWrite (uint32_t* location, uint32_t value)
+{
+ // Write the address
+ uint32_t locationData = (uint32_t)location;
+ MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+ // Write the data
+ uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+ *((volatile uint32_t*)writeAddress) = value;
+}
+
+uint32_t wbRead (uint32_t* location)
+{
+ // Write the address
+ uint32_t locationData = (uint32_t)location;
+ MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+ // Write the data
+ uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+ return *((volatile uint32_t*)writeAddress);
+}
+
+void nextTest (bool testPassing)
+{
+ uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
+ wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput | 0x02000);
+ wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput);
+}
+
+void main ()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt
+
+ // Enable the wishbone bus
+ reg_wb_enable = 1;
+
+ // Enable GPIO
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1) {}
+
+ // Setup test output
+ bool testPass = true;
+ wbWrite (GPIO0_OUTPUT_ADDR, 0x01000);
+ wbWrite (GPIO0_OE_ADDR, ~0x03000);
+
+ // Write nop to sram to allow step to be a valid instruction
+ // This does assume that instructions can be read
+ // Maybe test current instruction
+ wbWrite (CORE0_SRAM_ADDR, RV32I_NOP);
+ wbWrite (CORE1_SRAM_ADDR, RV32I_NOP);
+
+ // Test core 0
+ // Read that the config defaulted to 0
+ if (wbRead (CORE0_CONFIG_ADDR) != CORE_HALT) testPass = false;
+ nextTest (testPass);
+
+ // Read that the program counter defaulted to 0x0000_0000
+ if (wbRead (CORE0_REG_PC_ADDR) != 0x0) testPass = false;
+ nextTest (testPass);
+
+ // Step PC
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+
+ // Read that the PC stepped once
+ if (wbRead (CORE0_REG_PC_ADDR) != 0x4) testPass = false;
+ nextTest (testPass);
+
+ // Check that an NOP was read
+ if (wbRead (CORE0_REG_INSTR_ADDR) != RV32I_NOP) testPass = false;
+ nextTest (testPass);
+
+ // Jump PC
+ wbWrite (CORE0_REG_JUMP_ADDR, 0x100);
+
+ // Read that the PC jumped correctly
+ if (wbRead (CORE0_REG_PC_ADDR) != 0x104) testPass = false;
+ nextTest (testPass);
+
+ // Let the core run
+ wbWrite (CORE0_CONFIG_ADDR, CORE_RUN);
+
+ // Check that the core is running
+ if (wbRead (CORE0_STATUS_ADDR) != CORE_RUNNING_NOERROR) testPass = false;
+ nextTest (testPass);
+
+ // Check that the PC has increased
+ if (wbRead (CORE0_REG_PC_ADDR) >= 0x100) testPass = false;
+ nextTest (testPass);
+
+ // Halt the core
+ wbWrite (CORE0_CONFIG_ADDR, CORE_HALT);
+
+ // Make sure the core halted
+ if (wbRead (CORE0_CONFIG_ADDR) != CORE_HALT) testPass = false;
+
+ // Test core 1
+ // Read that the config defaulted to 0
+ if (wbRead (CORE1_CONFIG_ADDR) != CORE_HALT) testPass = false;
+ nextTest (testPass);
+
+ // Read that the program counter defaulted to 0x0000_0000
+ if (wbRead (CORE1_REG_PC_ADDR) != 0x0) testPass = false;
+ nextTest (testPass);
+
+ // Step PC
+ wbWrite (CORE1_REG_STEP_ADDR, 0x0);
+
+ // Read that the PC stepped once
+ if (wbRead (CORE1_REG_PC_ADDR) != 0x4) testPass = false;
+ nextTest (testPass);
+
+ // Check that an NOP was read
+ if (wbRead (CORE1_REG_INSTR_ADDR) != RV32I_NOP) testPass = false;
+ nextTest (testPass);
+
+ // Jump PC
+ wbWrite (CORE1_REG_JUMP_ADDR, 0x100);
+
+ // Read that the PC jumped correctly
+ if (wbRead (CORE1_REG_PC_ADDR) != 0x104) testPass = false;
+ nextTest (testPass);
+
+ // Let the core run
+ wbWrite (CORE1_CONFIG_ADDR, CORE_RUN);
+
+ // Check that the core is running
+ if (wbRead (CORE1_STATUS_ADDR) != CORE_RUNNING_NOERROR) testPass = false;
+ nextTest (testPass);
+
+ // Check that the PC has increased
+ if (wbRead (CORE1_REG_PC_ADDR) >= 0x100) testPass = false;
+ nextTest (testPass);
+
+ // Halt the core
+ wbWrite (CORE1_CONFIG_ADDR, CORE_HALT);
+
+ // Make sure the core halted
+ if (wbRead (CORE1_CONFIG_ADDR) != CORE_HALT) testPass = false;
+
+ // Finish test
+ nextTest (testPass);
+}
diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v
new file mode 100644
index 0000000..a1d6de9
--- /dev/null
+++ b/verilog/dv/corePC/corePC_tb.v
@@ -0,0 +1,184 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module corePC_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ wire succesOutput = mprj_io[12];
+ wire nextTestOutput = mprj_io[13];
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("corePC.vcd");
+ $dumpvars(0, corePC_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (500) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;35m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Core PC Test (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Core PC Test (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ // Wait for tests
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+
+ // Wait for management core to output a output test result
+ @(posedge nextTestOutput);
+
+ if (succesOutput) begin
+ $display("%c[1;92m",27);
+ `ifdef GL
+ $display("Monitor: Core PC Test (GL) Passed");
+ `else
+ $display("Monitor: Core PC Test (RTL) Passed");
+ `endif
+ $display("%c[0m",27);
+ end else begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Core PC Test (GL) Failed");
+ `else
+ $display ("Monitor: Core PC Test (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #300000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("corePC.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/ExperiarCore/JTAG.v b/verilog/rtl/ExperiarCore/JTAG.v
index 144efa7..c959d00 100644
--- a/verilog/rtl/ExperiarCore/JTAG.v
+++ b/verilog/rtl/ExperiarCore/JTAG.v
@@ -25,7 +25,7 @@
);
assign management_writeEnable = 1'b0;
- assign management_writeEnable = 1'b0;
+ assign management_readEnable = 1'b0;
assign management_byteSelect = 4'b1111;
assign management_address = 20'h0_0000;
assign management_writeData = 32'b0;
diff --git a/verilog/rtl/ExperiarCore/RV32ICore.v b/verilog/rtl/ExperiarCore/RV32ICore.v
index 2f005be..fc9fd7d 100644
--- a/verilog/rtl/ExperiarCore/RV32ICore.v
+++ b/verilog/rtl/ExperiarCore/RV32ICore.v
@@ -36,15 +36,14 @@
output wire probe_isCompressed
);
- localparam STATE_HALT = 2'b00;
- localparam STATE_DEBUG = 2'b10;
- localparam STATE_FETCH = 2'b01;
- localparam STATE_EXECUTE = 2'b11;
+ localparam STATE_FETCH = 1'b0;
+ localparam STATE_EXECUTE = 1'b1;
// System registers
- reg[1:0] state;
- reg[31:0] programCounter;
- reg[31:0] currentInstruction;
+ reg state = STATE_FETCH;
+ reg[3:0] currentError = 4'b0;
+ reg[31:0] programCounter = 32'b0;
+ reg[31:0] currentInstruction = 32'b0;
reg[31:0] registers [0:31];
// Management control
@@ -80,8 +79,6 @@
management_byteSelect[0] ? management_dataOut[7:0] : 8'h00
};
- wire[3:0] currentError = { 1'b0, 1'b0, addressMissaligned, invalidInstruction };
-
// Immediate Decode
wire[31:0] imm_I = {currentInstruction[31] ? 21'h1F_FFFF : 21'h00_0000, currentInstruction[30:25], currentInstruction[24:21], currentInstruction[20]};
wire[31:0] imm_S = {currentInstruction[31] ? 21'h1F_FFFF : 21'h00_0000, currentInstruction[30:25], currentInstruction[11:8] , currentInstruction[7]};
@@ -96,7 +93,7 @@
wire[4:0] rs2Index = currentInstruction[24:20];
wire[2:0] funct3 = currentInstruction[14:12];
wire[6:0] funct7 = currentInstruction[31:25];
- wire isCompressed = !(opcode[0] && opcode[1]);
+ wire isCompressed = opcode[1:0] != 2'b11;
// Instruction decode
wire isLUI = (opcode == 7'b0110111);
@@ -264,6 +261,9 @@
if (rst) begin
state <= STATE_FETCH;
programCounter <= 32'b0;
+ currentError <= 4'b0;
+ programCounter <= 32'b0;
+ currentInstruction <= 32'b0;
end else begin
if (!(|currentError)) begin
case (state)
@@ -281,11 +281,15 @@
end
STATE_EXECUTE: begin
- if (progressExecute) begin
- if (integerRegisterWriteEn && |rdIndex) registers[rdIndex] <= integerRegisterWriteData;
+ if (addressMissaligned || invalidInstruction) begin
+ currentError <= { 1'b0, 1'b0, addressMissaligned, invalidInstruction };
+ end else begin
+ if (progressExecute) begin
+ if (integerRegisterWriteEn && |rdIndex) registers[rdIndex] <= integerRegisterWriteData;
- programCounter <= { nextProgramCounter[31:1] , 1'b0};
- state <= STATE_FETCH;
+ programCounter <= { nextProgramCounter[31:1] , 1'b0};
+ state <= STATE_FETCH;
+ end
end
end
@@ -297,7 +301,7 @@
// Debug
- assign probe_state = state;
+ assign probe_state = { 1'b0, state };
assign probe_programCounter = programCounter;
assign probe_opcode = opcode;
assign probe_errorCode = currentError;
