ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program.

Features

• Dual RV32I cores
• Per core SRAM
• JTAG interface
• External flash controller
• Shared video SRAM
• Configurable VGA output
• 3x UART ports + 1 internal to caravel
• 1x SPI ports
• 4x PWM counters with 4x seperate outputs (2 are internal read only)

Memory Map

Macro Layout

ToDo

• Get it to build
• Flash controller
• JTAG core managment controller
• CSRs
• Test
• Fix all of the errors

Reference work and inspiration

• Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
• Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
• Caravel Documentation: Reference for caravel and configuration.
• Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.