Added video device simulation test, and new VGA state register which contains synchronisation signals. Also fixed some issues with register addresses, and the VGA signal generation. The video test doesn't currently validate that the correct pixels are displayed, but it does test the synchronisation times.
diff --git a/README.md b/README.md index 28fabc9..139646a 100644 --- a/README.md +++ b/README.md
@@ -42,23 +42,23 @@ # Tests ## RTL ### verify-peripheralsGPIO-rtl: Success -### verify-peripheralsUART-rtl: Failed +### verify-peripheralsUART-rtl: Success ### verify-peripheralsSPI-rtl: Not implemented ### verify-peripheralsPWM-rtl: Not implemented ### verify-memory-rtl: Not implemented -### verify-video-rtl: Not implemented +### verify-video-rtl: Not run ### verify-corePC-rtl: Success ### verify-coreMem-rtl: Not implemented ### verify-coreArch-rtl: Not implemented ## GL -### verify-peripheralsGPIO-gl: Not run -### verify-peripheralsUART-gl: Not run +### verify-peripheralsGPIO-gl: Failed +### verify-peripheralsUART-gl: Failed ### verify-peripheralsSPI-gl: Not implemented ### verify-peripheralsPWM-gl: Not implemented ### verify-memory-gl: Not implemented ### verify-video-gl: Not implemented -### verify-corePC-gl: Not run +### verify-corePC-gl: Failed ### verify-coreMem-gl: Not implemented ### verify-coreArch-gl: Not implemented @@ -68,7 +68,6 @@ - Fix precheck errors # Could do -- Add gpio registers for set, clear, and toggle which use the write data as a mask - Add uart pin swapping - Flash controller - JTAG core management controller
diff --git a/docs/Design/MemoryMap.txt b/docs/Design/MemoryMap.txt index 04d8216..81fff28 100644 --- a/docs/Design/MemoryMap.txt +++ b/docs/Design/MemoryMap.txt
@@ -38,7 +38,8 @@ 0x1280_0020: Vertical visible area compare 0x1280_0024: Vertical front porch compare 0x1280_0028: Vertical sync pulse compare - 0x1280_002C: Vertical whole line compare + 0x1280_002C: Vertical whole line compare + 0x1280_0030: VGA screen state 0x13xx_xxxx: Slave 3 (Peripherals) 0x1300_xxxx: Peripheral 0 (UART) 0x1300_0xxx: Peripheral configuration
diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v index 2c08de1..86ed378 100644 --- a/verilog/dv/corePC/corePC_tb.v +++ b/verilog/dv/corePC/corePC_tb.v
@@ -127,7 +127,7 @@ power4 <= 1'b1; end - always @(mprj_io) begin + always @(succesOutput, nextTestOutput) begin #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput); end
diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v index 67679c6..317341d 100644 --- a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v +++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
@@ -146,7 +146,7 @@ power4 <= 1'b1; end - always @(mprj_io) begin + always @(succesOutput, nextTestOutput, outputTestData, inputTestData) begin #1 $display("Success:0b%b Next test:0b%b Output:0b%b Input:0b%b", succesOutput, nextTestOutput, outputTestData, inputTestData); end
diff --git a/verilog/dv/peripheralsUART/peripheralsUART_tb.v b/verilog/dv/peripheralsUART/peripheralsUART_tb.v index e02fa63..489f174 100644 --- a/verilog/dv/peripheralsUART/peripheralsUART_tb.v +++ b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
@@ -121,7 +121,7 @@ power4 <= 1'b1; end - always @(mprj_io) begin + always @(succesOutput, nextTestOutput) begin #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput); end
diff --git a/verilog/dv/video/Makefile b/verilog/dv/video/Makefile new file mode 100644 index 0000000..3fd0b56 --- /dev/null +++ b/verilog/dv/video/Makefile
@@ -0,0 +1,32 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + + +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile + +
diff --git a/verilog/dv/video/video.c b/verilog/dv/video/video.c new file mode 100644 index 0000000..3e09c5e --- /dev/null +++ b/verilog/dv/video/video.c
@@ -0,0 +1,252 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include <defs.h> +#include <stub.c> + +/* + IO Test: + - Configures MPRJ lower 8-IO pins as outputs + - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) +*/ + +#define GPIO0_OE_WRITE_ADDR ((uint32_t*)0x33031000) +#define GPIO0_OE_SET_ADDR ((uint32_t*)0x33031004) +#define GPIO0_OE_CLEAR_ADDR ((uint32_t*)0x33031008) +#define GPIO0_OE_TOGGLE_ADDR ((uint32_t*)0x3303100C) +#define GPIO0_OUTPUT_WRITE_ADDR ((uint32_t*)0x33031010) +#define GPIO0_OUTPUT_SET_ADDR ((uint32_t*)0x33031014) +#define GPIO0_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33031018) +#define GPIO0_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303101C) +#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031020) +#define GPIO1_OE_WRITE_ADDR ((uint32_t*)0x33032000) +#define GPIO1_OE_SET_ADDR ((uint32_t*)0x33032004) +#define GPIO1_OE_CLEAR_ADDR ((uint32_t*)0x33032008) +#define GPIO1_OE_TOGGLE_ADDR ((uint32_t*)0x3303200C) +#define GPIO1_OUTPUT_WRITE_ADDR ((uint32_t*)0x33032010) +#define GPIO1_OUTPUT_SET_ADDR ((uint32_t*)0x33032014) +#define GPIO1_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33032018) +#define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C) +#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020) + +#define VGA_SRAM ((uint32_t*)0x32000000) +#define VGA_CONFIGURATION_REGISTER ((uint32_t*)0x32800000) +#define VGA_HORIZONTAL_VISIBLE_AREA_COMPARE ((uint32_t*)0x32800010) +#define VGA_HORIZONTAL_FRONT_PORCH_COMPARE ((uint32_t*)0x32800014) +#define VGA_HORIZONTAL_SYNC_PULSE_COMPARE ((uint32_t*)0x32800018) +#define VGA_HORIZONTAL_WHOLE_LINE_COMPARE ((uint32_t*)0x3280001C) +#define VGA_VERTICAL_VISIBLE_AREA_COMPARE ((uint32_t*)0x32800020) +#define VGA_VERTICAL_FRONT_PORCH_COMPARE ((uint32_t*)0x32800024) +#define VGA_VERTICAL_SYNC_PULSE_COMPARE ((uint32_t*)0x32800028) +#define VGA_VERTICAL_WHOLE_LINE_COMPARE ((uint32_t*)0x3280002C) +#define VGA_STATE ((uint32_t*)0x32800030) + +#define VGA_COLOR_RED 0b110000 +#define VGA_COLOR_GREEN 0b001100 +#define VGA_COLOR_BLUE 0b000011 +#define VGA_COLOR_CYAN (VGA_COLOR_GREEN | VGA_COLOR_BLUE) +#define VGA_COLOR_MAGENTA (VGA_COLOR_RED | VGA_COLOR_BLUE) +#define VGA_COLOR_YELLOW (VGA_COLOR_RED | VGA_COLOR_GREEN) +#define VGA_COLOR_BLACK 0b000000 +#define VGA_COLOR_WHITE (VGA_COLOR_RED | VGA_COLOR_GREEN | VGA_COLOR_BLUE) + +#define VGA_5PIXELS(p0, p1, p2, p3, p4) ((p4 << 24) | (p3 << 18) | (p2 << 12) | (p1 << 6) | p0) + +#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000) +#define MPRJ_WB_DATA_LOCATION 0x30008000 + +void wbWrite (uint32_t* location, uint32_t value) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + *((volatile uint32_t*)writeAddress) = value; +} + +uint32_t wbRead (uint32_t* location) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + return *((volatile uint32_t*)writeAddress); +} + +void nextTest (bool testPassing) +{ + uint32_t testPassingOutput = testPassing ? 0x01000 : 0; + wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000); + wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000); +} + +void main () +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt + + // Enable the wishbone bus + reg_wb_enable = 1; + + // Enable GPIO + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + + // Enable vga output + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1) {} + + // Setup test output + bool testPass = true; + wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000); + wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000); + + // http://tinyvga.com/vga-timing/800x600@60Hz + // This should generate a valid VGA signal for a 5MHz pixel clock + // As the clock is actually 40MHz, it should just run faster so the simulation doesn't take ages + + // Write some test pixel data to video sram + uint32_t testPixel0 = VGA_5PIXELS (VGA_COLOR_RED, VGA_COLOR_GREEN, VGA_COLOR_BLUE, VGA_COLOR_BLACK, VGA_COLOR_WHITE); + uint32_t testPixel1 = VGA_5PIXELS (VGA_COLOR_CYAN, VGA_COLOR_MAGENTA, VGA_COLOR_YELLOW, VGA_COLOR_BLACK, VGA_COLOR_WHITE); + uint32_t testPixel2 = VGA_5PIXELS (0b110111, 0b011000, 0b100001, 0b011110, 0b111111); + uint32_t testPixel3 = VGA_5PIXELS (0b000000, 0b010000, 0b000100, 0b000001, 0b010101); + wbWrite (VGA_SRAM, testPixel0); + wbWrite (VGA_SRAM + 1, testPixel1); + wbWrite (VGA_SRAM + 2, testPixel2); + wbWrite (VGA_SRAM + 3, testPixel3); + + wbWrite (VGA_SRAM + 8, testPixel0); + wbWrite (VGA_SRAM + 9, testPixel1); + wbWrite (VGA_SRAM + 10, testPixel2); + wbWrite (VGA_SRAM + 11, testPixel3); + wbWrite (VGA_SRAM + 12, testPixel0); + + // Make sure some of the data has been written properly + // Don't bother testing everything as that would take even longer + if (wbRead (VGA_SRAM) != testPixel0) testPass = false; + if (wbRead (VGA_SRAM + 1) != testPixel1) testPass = false; + if (wbRead (VGA_SRAM + 2) != testPixel2) testPass = false; + if (wbRead (VGA_SRAM + 3) != testPixel3) testPass = false; + nextTest (testPass); + + uint32_t horizontalVisibleAreaCompare = 99; + wbWrite (VGA_HORIZONTAL_VISIBLE_AREA_COMPARE, horizontalVisibleAreaCompare); + if (wbRead (VGA_HORIZONTAL_VISIBLE_AREA_COMPARE) != horizontalVisibleAreaCompare) testPass = false; + nextTest (testPass); + + uint32_t horizontalFrontPorchCompare = 104; + wbWrite (VGA_HORIZONTAL_FRONT_PORCH_COMPARE, horizontalFrontPorchCompare); + if (wbRead (VGA_HORIZONTAL_FRONT_PORCH_COMPARE) != horizontalFrontPorchCompare) testPass = false; + nextTest (testPass); + + uint32_t horizontalSyncPulseCompare = 120; + wbWrite (VGA_HORIZONTAL_SYNC_PULSE_COMPARE, horizontalSyncPulseCompare); + if (wbRead (VGA_HORIZONTAL_SYNC_PULSE_COMPARE) != horizontalSyncPulseCompare) testPass = false; + nextTest (testPass); + + uint32_t horizontalWholeLineCompare = 131; + wbWrite (VGA_HORIZONTAL_WHOLE_LINE_COMPARE, horizontalWholeLineCompare); + if (wbRead (VGA_HORIZONTAL_WHOLE_LINE_COMPARE) != horizontalWholeLineCompare) testPass = false; + nextTest (testPass); + + uint32_t verticalVisibleAreaCompare = 599; + wbWrite (VGA_VERTICAL_VISIBLE_AREA_COMPARE, verticalVisibleAreaCompare); + if (wbRead (VGA_VERTICAL_VISIBLE_AREA_COMPARE) != verticalVisibleAreaCompare) testPass = false; + nextTest (testPass); + + uint32_t verticalFrontPorchCompare = 600; + wbWrite (VGA_VERTICAL_FRONT_PORCH_COMPARE, verticalFrontPorchCompare); + if (wbRead (VGA_VERTICAL_FRONT_PORCH_COMPARE) != verticalFrontPorchCompare) testPass = false; + nextTest (testPass); + + uint32_t verticalSyncPulseCompare = 604; + wbWrite (VGA_VERTICAL_SYNC_PULSE_COMPARE, verticalSyncPulseCompare); + if (wbRead (VGA_VERTICAL_SYNC_PULSE_COMPARE) != verticalSyncPulseCompare) testPass = false; + nextTest (testPass); + + uint32_t verticalWholeLineCompare = 627; + wbWrite (VGA_VERTICAL_WHOLE_LINE_COMPARE, verticalWholeLineCompare); + if (wbRead (VGA_VERTICAL_WHOLE_LINE_COMPARE) != verticalWholeLineCompare) testPass = false; + nextTest (testPass); + + // Enable default VGA output + uint32_t enableVGARaw = 0x4AA; + wbWrite (VGA_CONFIGURATION_REGISTER, enableVGARaw); + if (wbRead (VGA_CONFIGURATION_REGISTER) != enableVGARaw) testPass = false; + nextTest (testPass); + + // Wait for two vsync pulses + // Ideally wait for the vsync signal + // As we don't have interrupts, and the time between checks is so long this won't work + // uint32_t vsyncMask = 0x4; + // while ((wbRead (VGA_STATE) & vsyncMask) != vsyncMask) {} + // while ((wbRead (VGA_STATE) & vsyncMask) != vsyncMask) {} + // Instead just do a number of reads that should give enough time for the timing test to take place + for (uint32_t i = 0; i < 24; i++) wbRead (VGA_STATE); + + // Enable VGA output in tight memory mode + uint32_t enableVGATight = 0x5AA; + wbWrite (VGA_CONFIGURATION_REGISTER, enableVGATight); + if (wbRead (VGA_CONFIGURATION_REGISTER) != enableVGATight) testPass = false; + nextTest (testPass); + + // Wait for two vsync pulses + // while ((wbRead (VGA_STATE) & vsyncMask) != vsyncMask) {} + // while ((wbRead (VGA_STATE) & vsyncMask) != vsyncMask) {} + for (uint32_t i = 0; i < 24; i++) wbRead (VGA_STATE); + + // Finish test + // There will be some testing after this to check that + nextTest (testPass); +}
diff --git a/verilog/dv/video/video_tb.v b/verilog/dv/video/video_tb.v new file mode 100644 index 0000000..427642d --- /dev/null +++ b/verilog/dv/video/video_tb.v
@@ -0,0 +1,265 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module video_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + wire succesOutput = mprj_io[12]; + wire nextTestOutput = mprj_io[13]; + + wire[5:0] vgaPixel = mprj_io[35:30]; + wire vgaVSync = mprj_io[36]; + wire vgaHSync = mprj_io[37]; + + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + reg timingValid = 1'b1; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + timingValid = 1'b1; + end + + initial begin + $dumpfile("video.vcd"); + $dumpvars(0, video_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (1000) begin + repeat (1000) @(posedge clock); + //$display("+1000 cycles"); + end + $display("%c[1;35m",27); + `ifdef GL + $display ("Monitor: Timeout, Peripherals Video Test (GL) Failed"); + `else + $display ("Monitor: Timeout, Peripherals Video Test (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + realtime timerStart; + realtime timerLength; + + initial begin + $timeformat(-6, 3, "us", 8); + + // Wait for tests + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + + // Test default vga mode + @(negedge vgaHSync); + timerStart = $realtime; + + // Measure hsync pulse length + @(posedge vgaHSync); + timerLength = $realtime - timerStart; + $display("H Sync pulse period: %t", timerLength); + if (timerLength < 390 || timerLength > 410) timingValid = 1'b0; + + // Measure hsync period + @(negedge vgaHSync); + timerLength = $realtime - timerStart; + $display("H Sync period: %t", timerLength); + if (timerLength < 3290 || timerLength > 3310) timingValid = 1'b0; + + @(negedge vgaVSync); + timerStart = $realtime; + + // Measure hsync pulse length + @(posedge vgaVSync); + timerLength = $realtime - timerStart; + $display("V Sync pulse period: %t", timerLength); + if (timerLength < 13190 || timerLength > 13210) timingValid = 1'b0; + + // Measure vsync period + @(negedge vgaVSync); + timerLength = $realtime - timerStart; + $display("V Sync period: %t", timerLength); + if (timerLength < 2072390 || timerLength > 2072410) timingValid = 1'b0; + + // Test tight memory mode + @(posedge nextTestOutput); + + @(negedge vgaHSync); + timerStart = $realtime; + + // Measure hsync pulse length + @(posedge vgaHSync); + timerLength = $realtime - timerStart; + $display("H Sync pulse period: %t", timerLength); + if (timerLength < 390 || timerLength > 410) timingValid = 1'b0; + + // Measure hsync period + @(negedge vgaHSync); + timerLength = $realtime - timerStart; + $display("H Sync period: %t", timerLength); + if (timerLength < 3290 || timerLength > 3310) timingValid = 1'b0; + + @(negedge vgaVSync); + timerStart = $realtime; + + // Measure hsync pulse length + @(posedge vgaVSync); + timerLength = $realtime - timerStart; + $display("V Sync pulse period: %t", timerLength); + if (timerLength < 13190 || timerLength > 13210) timingValid = 1'b0; + + // Measure vsync period + @(negedge vgaVSync); + timerLength = $realtime - timerStart; + $display("V Sync period: %t", timerLength); + if (timerLength < 2072390 || timerLength > 2072410) timingValid = 1'b0; + + // Wait for test to finish + @(posedge nextTestOutput); + + if (timingValid) begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals Video Test VGA Timing (GL) Failed"); + `else + $display ("Monitor: Peripherals Video Test VGA Timing (RTL) Failed"); + `endif + $display("%c[0m",27); + end else if (succesOutput) begin + $display("%c[1;92m",27); + `ifdef GL + $display("Monitor: Peripherals Video Test (GL) Passed"); + `else + $display("Monitor: Peripherals Video Test (RTL) Passed"); + `endif + $display("%c[0m",27); + end else begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals Video Test (GL) Failed"); + `else + $display ("Monitor: Peripherals Video Test (RTL) Failed"); + `endif + $display("%c[0m",27); + end + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #300000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(succesOutput, nextTestOutput) begin + #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("video.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/Video/VGA_top.v b/verilog/rtl/Video/VGA_top.v index 18e43c4..d41ce5a 100644 --- a/verilog/rtl/Video/VGA_top.v +++ b/verilog/rtl/Video/VGA_top.v
@@ -20,6 +20,7 @@ // Memory interface input wire vga_clk, + output wire vga_fetchData, output reg[ADDRESS_BITS-1:0] vga_address, input wire[31:0] vga_data, @@ -43,7 +44,7 @@ localparam DRAW_MODE_COLOUR_PALETTE = 2'b10; localparam DRAW_MODE_SPRITES = 2'b11; - localparam CONFIG_ADDRESS = 12'h010; + localparam CONFIG_ADDRESS = 12'h800; wire configEnable = peripheralBus_address[23:12] == CONFIG_ADDRESS; wire[11:0] configRegisterAddress = peripheralBus_address[11:0]; @@ -53,10 +54,11 @@ // b00-b03: horizontalPixelSize Default 0xA // b04-b07: verticalPixelSize Default 0xA // b08-b09: drawMode Default 0b00 - wire[9:0] configuration; + // b10: enableOutput Default 0 + wire[10:0] configuration; wire[31:0] configurationRegisterOutputData; wire configurationRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h020), .DEFAULT(10'h0AA)) configurationRegister( + ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h000), .DEFAULT(11'h0AA)) configurationRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -72,6 +74,7 @@ wire[3:0] horizontalPixelSize = configuration[3:0]; wire[3:0] verticalPixelSize = configuration[7:4]; wire[1:0] drawMode = configuration[9:8]; + wire enableOutput = configuration[10]; // Defaults are timing for 800 x 600 at 60Hz // http://tinyvga.com/vga-timing/800x600@60Hz @@ -79,7 +82,7 @@ wire[10:0] horizontalVisibleAreaCompare; wire[31:0] horizontalVisibleAreaCompareRegisterOutputData; wire horizontalVisibleAreaCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h000), .DEFAULT(11'h31F)) horizontalVisibleAreaCompareRegister( + ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h010), .DEFAULT(11'h31F)) horizontalVisibleAreaCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -96,7 +99,7 @@ wire[10:0] horizontalFrontPorchCompare; wire[31:0] horizontalFrontPorchCompareRegisterOutputData; wire horizontalFrontPorchCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h004), .DEFAULT(11'h347)) horizontalFrontPorchCompareRegister( + ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h014), .DEFAULT(11'h347)) horizontalFrontPorchCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -113,7 +116,7 @@ wire[10:0] horizontalSyncPulseCompare; wire[31:0] horizontalSyncPulseCompareRegisterOutputData; wire horizontalSyncPulseCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h008), .DEFAULT(11'h3C7)) horizontalSyncPulseCompareRegister( + ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h018), .DEFAULT(11'h3C7)) horizontalSyncPulseCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -130,7 +133,7 @@ wire[10:0] horizontalWholeLineCompare; wire[31:0] horizontalWholeLineCompareRegisterOutputData; wire horizontalWholeLineCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h00C), .DEFAULT(11'h41F)) horizontalWholeLineCompareRegister( + ConfigurationRegister #(.WIDTH(11), .ADDRESS(12'h01C), .DEFAULT(11'h41F)) horizontalWholeLineCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -147,7 +150,7 @@ wire[9:0] verticalVisibleAreaCompare; wire[31:0] verticalVisibleAreaCompareRegisterOutputData; wire verticalVisibleAreaCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h010), .DEFAULT(11'h257)) verticalVisibleAreaCompareRegister( + ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h020), .DEFAULT(11'h257)) verticalVisibleAreaCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -164,7 +167,7 @@ wire[9:0] verticalFrontPorchCompare; wire[31:0] verticalFrontPorchCompareRegisterOutputData; wire verticalFrontPorchCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h014), .DEFAULT(11'h258)) verticalFrontPorchCompareRegister( + ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h024), .DEFAULT(11'h258)) verticalFrontPorchCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -181,7 +184,7 @@ wire[9:0] verticalSyncPulseCompare; wire[31:0] verticalSyncPulseCompareRegisterOutputData; wire verticalSyncPulseCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h018), .DEFAULT(11'h25C)) verticalSyncPulseCompareRegister( + ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h028), .DEFAULT(11'h25C)) verticalSyncPulseCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -198,7 +201,7 @@ wire[9:0] verticalWholeLineCompare; wire[31:0] verticalWholeLineCompareRegisterOutputData; wire verticalWholeLineCompareRegisterOutputRequest; - ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h01C), .DEFAULT(11'h273)) verticalWholeLineCompareRegister( + ConfigurationRegister #(.WIDTH(10), .ADDRESS(12'h02C), .DEFAULT(11'h273)) verticalWholeLineCompareRegister( .clk(clk), .rst(rst), .enable(configEnable), @@ -211,6 +214,34 @@ .requestOutput(verticalWholeLineCompareRegisterOutputRequest), .currentValue(verticalWholeLineCompare)); + // VGA state register + reg inVerticalVisibleArea = 1'b1; + reg inHorizontalVisibleArea = 1'b1; + wire[31:0] stateRegisterOutputData; + wire stateRegisterOutputRequest; + wire stateReadDataEnable_nc; + wire stateRegisterBusyBusy_nc; + wire[4:0] stateRegisterWriteData_nc; + wire stateRegisterWriteDataEnable_nc; + DataRegister #(.WIDTH(5), .ADDRESS(12'h030)) stateRegister( + .clk(clk), + .rst(rst), + .enable(configEnable), + .peripheralBus_we(peripheralBus_we), + .peripheralBus_oe(peripheralBus_oe), + .peripheralBus_busy(stateRegisterBusyBusy_nc), + .peripheralBus_address(configRegisterAddress), + .peripheralBus_byteSelect(peripheralBus_byteSelect), + .peripheralBus_dataWrite(peripheralBus_dataWrite), + .peripheralBus_dataRead(stateRegisterOutputData), + .requestOutput(stateRegisterOutputRequest), + .writeData(stateRegisterWriteData_nc), + .writeData_en(stateRegisterWriteDataEnable_nc), + .writeData_busy(1'b0), + .readData({ inVerticalVisibleArea, inHorizontalVisibleArea, !vga_vsync, !vga_hsync, enableOutput }), + .readData_en(stateReadDataEnable_nc), + .readData_busy(1'b0)); + assign peripheralBus_busy = 1'b0; assign requestOutput = configurationRegisterOutputRequest || horizontalVisibleAreaCompareRegisterOutputRequest @@ -220,7 +251,8 @@ || verticalVisibleAreaCompareRegisterOutputRequest || verticalFrontPorchCompareRegisterOutputRequest || verticalSyncPulseCompareRegisterOutputRequest - || verticalWholeLineCompareRegisterOutputRequest; + || verticalWholeLineCompareRegisterOutputRequest + || stateRegisterOutputRequest; always @(*) begin case (1'b1) @@ -242,6 +274,8 @@ peripheralBus_dataRead <= verticalSyncPulseCompareRegisterOutputData; verticalWholeLineCompareRegisterOutputRequest: peripheralBus_dataRead <= verticalWholeLineCompareRegisterOutputData; + stateRegisterOutputRequest: + peripheralBus_dataRead <= stateRegisterOutputData; default: peripheralBus_dataRead <= ~32'b0; endcase end @@ -252,18 +286,23 @@ wire isEndHorizontalFrontPorch = horizontalCounter == horizontalFrontPorchCompare; wire isEndHorizontalSyncPulse = horizontalCounter == horizontalSyncPulseCompare; wire isEndHorizontalWholeLine = horizontalCounter == horizontalWholeLineCompare; - reg inHorizontalVisibleArea = 1'b1; reg hsync; always @(posedge vga_clk) begin - if (isEndHorizontalWholeLine) horizontalCounter <= 10'b0; - else horizontalCounter <= horizontalCounter + 1; + if (rst || !enableOutput) begin + horizontalCounter <= 10'b0; + inHorizontalVisibleArea <= 1'b1; + hsync <= 1'b1; + end else begin + if (isEndHorizontalWholeLine) horizontalCounter <= 10'b0; + else horizontalCounter <= horizontalCounter + 1; - if (isEndHorizontalVisibleArea) inHorizontalVisibleArea <= 1'b0; - else if (isEndHorizontalWholeLine) inHorizontalVisibleArea <= 1'b1; + if (isEndHorizontalVisibleArea) inHorizontalVisibleArea <= 1'b0; + else if (isEndHorizontalWholeLine) inHorizontalVisibleArea <= 1'b1; - if (isEndHorizontalFrontPorch) hsync <= 1'b0; - else if (isEndHorizontalSyncPulse) hsync <= 1'b1; + if (isEndHorizontalFrontPorch) hsync <= 1'b0; + else if (isEndHorizontalSyncPulse) hsync <= 1'b1; + end end reg[9:0] verticalCounter; @@ -271,18 +310,25 @@ wire isEndVerticalFrontPorch = verticalCounter == verticalFrontPorchCompare; wire isEndVerticalSyncPulse = verticalCounter == verticalSyncPulseCompare; wire isEndVerticalWholeLine = verticalCounter == verticalWholeLineCompare; - reg inVerticalVisibleArea = 1'b1; reg vsync; always @(posedge vga_clk) begin - if (isEndVerticalWholeLine) verticalCounter <= 10'b0; - else verticalCounter <= verticalCounter + 1; + if (rst || !enableOutput) begin + verticalCounter <= 10'b0; + inVerticalVisibleArea <= 1'b1; + vsync <= 1'b1; + end else begin + if (isEndHorizontalWholeLine) begin + if (isEndVerticalWholeLine) verticalCounter <= 10'b0; + else verticalCounter <= verticalCounter + 1; - if (isEndVerticalVisibleArea) inVerticalVisibleArea <= 1'b0; - else if (isEndVerticalWholeLine) inVerticalVisibleArea <= 1'b1; + if (isEndVerticalVisibleArea) inVerticalVisibleArea <= 1'b0; + else if (isEndVerticalWholeLine) inVerticalVisibleArea <= 1'b1; - if (isEndVerticalFrontPorch) vsync <= 1'b0; - else if (isEndVerticalSyncPulse) vsync <= 1'b1; + if (isEndVerticalFrontPorch) vsync <= 1'b0; + else if (isEndVerticalSyncPulse) vsync <= 1'b1; + end + end end // Latch data in from sram and delay sync signals @@ -292,17 +338,25 @@ reg loadPixel; - reg[2:0] hsyncDelay; - reg[2:0] vsyncDelay; + reg[1:0] hsyncDelay; + reg[1:0] vsyncDelay; reg[31:0] currentPixelData; always @(posedge vga_clk) begin - if (loadPixel) currentPixelData <= vga_data; - hsyncDelay <= { hsyncDelay[0], hsync }; - vsyncDelay <= { vsyncDelay[0], vsync }; + if (rst || !enableOutput) begin + currentPixelData <= 1'b0; + hsyncDelay <= 2'b11; + vsyncDelay <= 2'b11; + end else begin + if (loadPixel) currentPixelData <= vga_data; + hsyncDelay <= { hsyncDelay[0], hsync }; + vsyncDelay <= { vsyncDelay[0], vsync }; + end end - assign vga_hsync = hsyncDelay[1]; - assign vga_vsync = vsyncDelay[1]; + assign vga_fetchData = loadPixel; + + assign vga_hsync = enableOutput ? hsyncDelay[1] : 1'b1; + assign vga_vsync = enableOutput ? vsyncDelay[1] : 1'b1; // VGA pixel address select reg[17:0] raw_directPixelCounter; @@ -324,51 +378,68 @@ reg[3:0] raw_verticalPixelStretchCounter_d; wire[3:0] raw_nextVerticalPixelStretchCounter = raw_verticalPixelStretchCounter + 1; + wire raw_horizontalPixelStretchNextPixel = raw_horizontalPixelStretchCounter == horizontalPixelSize; + wire raw_verticalPixelStretchNextPixel = raw_verticalPixelStretchCounter == verticalPixelSize; + // Raw draw mode always @(*) begin - if (inHorizontalVisibleArea) begin - if (raw_horizontalPixelStretchCounter == horizontalPixelSize) begin - if (raw_subPixelCounter == MAX_SUB_PIXEL_VALUE) begin - raw_subPixelCounter_d <= 3'b0; - raw_horizontalPixelCounter_d <= raw_horizontalPixelCounter + 1; - raw_directPixelCounter_d <= raw_nextDirectPixelCounter; - end else begin - raw_subPixelCounter_d <= raw_subPixelCounter + 1; - end + if (inVerticalVisibleArea) begin + if (inHorizontalVisibleArea) begin + if (raw_horizontalPixelStretchNextPixel) begin + if (raw_subPixelCounter == MAX_SUB_PIXEL_VALUE) begin + raw_subPixelCounter_d <= 3'b0; + raw_horizontalPixelCounter_d <= raw_horizontalPixelCounter + 1; + raw_directPixelCounter_d <= raw_nextDirectPixelCounter; + end else begin + raw_subPixelCounter_d <= raw_subPixelCounter + 1; + end - raw_horizontalPixelStretchCounter_d <= 4'b0; + raw_horizontalPixelStretchCounter_d <= 4'b0; + end else begin + raw_horizontalPixelStretchCounter_d <= raw_nextHorizontalPixelStretchCounter; + end end else begin - raw_horizontalPixelStretchCounter_d <= raw_nextHorizontalPixelStretchCounter; + raw_subPixelCounter_d <= 3'b0; + raw_horizontalPixelCounter_d <= 9'b0; + raw_horizontalPixelStretchCounter_d <= 4'b0; + end + + if (isEndHorizontalWholeLine) begin + raw_directPixelCounter_d <= raw_nextDirectPixelCounter; + + if (raw_verticalPixelStretchNextPixel) begin + raw_verticalPixelCounter_d <= raw_verticalPixelCounter + 1; + raw_verticalPixelStretchCounter_d <= 4'b0; + end else begin + raw_verticalPixelStretchCounter_d <= raw_nextVerticalPixelStretchCounter; + end end end else begin + raw_directPixelCounter_d <= 18'b0; raw_subPixelCounter_d <= 3'b0; raw_horizontalPixelCounter_d <= 9'b0; raw_horizontalPixelStretchCounter_d <= 4'b0; - - if (inVerticalVisibleArea) raw_directPixelCounter_d <= raw_nextDirectPixelCounter; - else raw_directPixelCounter_d <= 18'b0; - end - - if (inVerticalVisibleArea) begin - if (raw_verticalPixelStretchCounter == verticalPixelSize) begin - raw_verticalPixelCounter_d <= raw_verticalPixelCounter + 1; - raw_verticalPixelStretchCounter_d <= 4'b0; - end else begin - raw_verticalPixelStretchCounter_d <= raw_nextVerticalPixelStretchCounter; - end - end else begin raw_verticalPixelCounter_d <= 9'b0; - raw_verticalPixelStretchCounter_d <= 4'b0; + raw_verticalPixelStretchCounter_d <= 4'b0; end end always @(posedge vga_clk) begin - raw_directPixelCounter <= raw_directPixelCounter_d; - raw_horizontalPixelCounter <= raw_horizontalPixelCounter_d; - raw_verticalPixelCounter <= raw_verticalPixelCounter_d; - raw_subPixelCounter <= raw_subPixelCounter_d; - raw_horizontalPixelStretchCounter <= raw_horizontalPixelStretchCounter_d; - raw_verticalPixelStretchCounter <= raw_verticalPixelStretchCounter_d; + if (rst || !enableOutput) begin + raw_directPixelCounter <= 18'b0; + raw_horizontalPixelCounter <= 9'b0; + raw_verticalPixelCounter <= 10'b0; + raw_subPixelCounter <= 3'b0; + raw_horizontalPixelStretchCounter <= 4'b0; + raw_verticalPixelStretchCounter <= 4'b0; + end else begin + raw_directPixelCounter <= raw_directPixelCounter_d; + raw_horizontalPixelCounter <= raw_horizontalPixelCounter_d; + raw_verticalPixelCounter <= raw_verticalPixelCounter_d; + raw_subPixelCounter <= raw_subPixelCounter_d; + raw_horizontalPixelStretchCounter <= raw_horizontalPixelStretchCounter_d; + raw_verticalPixelStretchCounter <= raw_verticalPixelStretchCounter_d; + end end wire raw_directPixelCounterChanged = raw_directPixelCounter != raw_directPixelCounter_d; @@ -434,8 +505,10 @@ endcase end - assign vga_r = raw_currentPixel[1:0]; - assign vga_g = raw_currentPixel[3:2]; - assign vga_b = raw_currentPixel[5:4]; + wire onScreen = inHorizontalVisibleArea && inVerticalVisibleArea; + + assign vga_r = enableOutput && onScreen ? raw_currentPixel[1:0] : 2'b0; + assign vga_g = enableOutput && onScreen ? raw_currentPixel[3:2] : 2'b0; + assign vga_b = enableOutput && onScreen ? raw_currentPixel[5:4] : 2'b0; endmodule
diff --git a/verilog/rtl/Video/VideoMemory_top.v b/verilog/rtl/Video/VideoMemory_top.v index c0deb3e..beb76af 100644 --- a/verilog/rtl/Video/VideoMemory_top.v +++ b/verilog/rtl/Video/VideoMemory_top.v
@@ -17,6 +17,7 @@ output wire requestOutput, // Video interface + input wire video_fetchData, input wire[SRAM_ADDRESS_SIZE+3:0] video_address, output reg[31:0] video_data, @@ -142,12 +143,16 @@ // Set enable bit for video port (active low) always @(*) begin - case (videoSRAMBank) - 2'b00: sram_csb1 <= 4'b1110; - 2'b01: sram_csb1 <= 4'b1101; - 2'b10: sram_csb1 <= 4'b1011; - 2'b11: sram_csb1 <= 4'b0111; - endcase + if (video_fetchData) begin + case (videoSRAMBank) + 2'b00: sram_csb1 <= 4'b1110; + 2'b01: sram_csb1 <= 4'b1101; + 2'b10: sram_csb1 <= 4'b1011; + 2'b11: sram_csb1 <= 4'b0111; + endcase + end else begin + sram_csb1 <= 4'b1111; + end end assign sram_addr1 = video_address[SRAM_ADDRESS_SIZE+1:2];
diff --git a/verilog/rtl/Video/Video_top.v b/verilog/rtl/Video/Video_top.v index bed22e2..b2cdb4b 100644 --- a/verilog/rtl/Video/Video_top.v +++ b/verilog/rtl/Video/Video_top.v
@@ -94,6 +94,7 @@ .peripheralBus_dataRead(peripheralBus_dataRead), .peripheralBus_dataWrite(peripheralBus_dataWrite)); + wire video_fetchData; wire[SRAM_ADDRESS_SIZE+3:0] vga_address; wire[31:0] vga_data; @@ -115,6 +116,7 @@ .peripheralBus_dataRead(videoMemoryDataRead), .peripheralBus_dataWrite(peripheralBus_dataWrite), .requestOutput(videoMemoryRequestOutput), + .video_fetchData(vga_fetchData), .video_address(vga_address), .video_data(vga_data), .sram0_csb0(sram0_csb0), @@ -160,6 +162,7 @@ .peripheralBus_dataWrite(peripheralBus_dataWrite), .requestOutput(vgaRequestOutput), .vga_clk(vga_clk), + .vga_fetchData(vga_fetchData), .vga_address(vga_address), .vga_data(vga_data), .vga_r(vga_r),