Added some utility modules for use with peripherals.
diff --git a/verilog/rtl/Peripherals/Registers/ConfigurationRegister.v b/verilog/rtl/Peripherals/Registers/ConfigurationRegister.v
new file mode 100644
index 0000000..4fc64e0
--- /dev/null
+++ b/verilog/rtl/Peripherals/Registers/ConfigurationRegister.v
@@ -0,0 +1,44 @@
+module ConfigurationRegister #(
+ parameter WIDTH = 32,
+ parameter ADDRESS = 12'b0,
+ parameter DEFAULT = 32'b0
+ )(
+ input wire clk,
+ input wire rst,
+
+ // Peripheral Bus
+ input wire enable,
+ input wire peripheralBus_we,
+ input wire peripheralBus_oe,
+ input wire[11:0] peripheralBus_address,
+ inout wire[31:0] peripheralBus_data,
+
+ output wire[WIDTH-1:0] currentValue
+ );
+
+reg[WIDTH-1:0] registerValue;
+
+wire registerSelect = enable && (peripheralBus_address == ADDRESS);
+wire we = registerSelect && peripheralBus_we && !peripheralBus_oe;
+wire oe = registerSelect && peripheralBus_oe && !peripheralBus_we;
+
+always @(posedge clk) begin
+ if (rst) begin
+ registerValue <= DEFAULT;
+ end else begin
+ if (we) registerValue <= peripheralBus_data[WIDTH-1:0];
+ end
+end
+
+generate
+ if (WIDTH == 32) begin
+ assign peripheralBus_data = oe ? registerValue : 32'bz;
+ end else begin
+ wire[32-WIDTH-1:0] zeroPadding = 'b0;
+ assign peripheralBus_data = oe ? { zeroPadding, registerValue } : 32'bz;
+ end
+endgenerate
+
+assign currentValue = registerValue;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Peripherals/Registers/DataRegister.v b/verilog/rtl/Peripherals/Registers/DataRegister.v
new file mode 100644
index 0000000..491b56e
--- /dev/null
+++ b/verilog/rtl/Peripherals/Registers/DataRegister.v
@@ -0,0 +1,44 @@
+module DataRegister #(
+ parameter WIDTH = 32,
+ parameter ADDRESS = 12'b0
+ )(
+ input wire clk,
+ input wire rst,
+
+ // Peripheral Bus
+ input wire enable,
+ input wire peripheralBus_we,
+ input wire peripheralBus_oe,
+ output wire peripheralBus_busy,
+ input wire[11:0] peripheralBus_address,
+ inout wire[31:0] peripheralBus_data,
+
+ input wire[WIDTH-1:0] writeData,
+ output wire writeData_en,
+ input wire writeData_busy,
+ output wire[WIDTH-1:0] readData,
+ output wire readData_en,
+ input wire readData_busy
+ );
+
+wire registerSelect = enable && (peripheralBus_address == ADDRESS);
+wire we = registerSelect && peripheralBus_we && !peripheralBus_oe;
+wire oe = registerSelect && peripheralBus_oe && !peripheralBus_we;
+
+assign writeData = we ? peripheralBus_data[WIDTH-1:0] : 'b0;
+assign writeData_en = we;
+
+generate
+ if (WIDTH == 32) begin
+ assign peripheralBus_data = oe ? readData : 32'bz;
+ end else begin
+ wire[32-WIDTH-1:0] zeroPadding = 'b0;
+ assign peripheralBus_data = oe ? { zeroPadding, readData } : 32'bz;
+ end
+endgenerate
+
+assign readData_en = oe;
+
+assign peripheralBus_busy = registerSelect && ((we && writeData_busy) | (oe && readData_busy));
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Peripherals/Registers/DeviceSelect.v b/verilog/rtl/Peripherals/Registers/DeviceSelect.v
new file mode 100644
index 0000000..83dbea7
--- /dev/null
+++ b/verilog/rtl/Peripherals/Registers/DeviceSelect.v
@@ -0,0 +1,13 @@
+module DeviceSelect #(
+ parameter ID = 4'h0
+ )(
+ input wire peripheralEnable,
+ input wire[15:0] peripheralBus_address,
+ output wire[11:0] localAddress,
+ output wire deviceEnable
+ );
+
+assign deviceEnable = peripheralEnable && (peripheralBus_address[15:12] == ID);
+assign localAddress = peripheralBus_address[11:0];
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Peripherals/Registers/PeripheralSelect.v b/verilog/rtl/Peripherals/Registers/PeripheralSelect.v
new file mode 100644
index 0000000..97de0f3
--- /dev/null
+++ b/verilog/rtl/Peripherals/Registers/PeripheralSelect.v
@@ -0,0 +1,12 @@
+module PeripheralSelect #(
+ parameter ID = 8'h00
+ )(
+ input wire[23:0] peripheralBus_address,
+ output wire[15:0] localAddress,
+ output wire peripheralEnable
+ );
+
+assign peripheralEnable = peripheralBus_address[23:16] == ID;
+assign localAddress = peripheralBus_address[15:0];
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Utility/ConfigurationRegister.v b/verilog/rtl/Utility/ConfigurationRegister.v
deleted file mode 100644
index 1dc4ef5..0000000
--- a/verilog/rtl/Utility/ConfigurationRegister.v
+++ /dev/null
@@ -1,32 +0,0 @@
-module ConfigurationRegister #(
- parameter WIDTH = 32,
- parameter ADDRESS = 32'b0
- )(
- input wire clk,
- input wire rst,
-
- // RW interface
- input wire we,
- input wire oe,
- input wire[31:0] interfaceAddress,
- inout wire[31:0] interfaceData,
-
- output wire[WIDTH-1:0] currentValue
- );
-
-reg[WIDTH-1:0] registerValue;
-
-wire registerSelect = interfaceAddress == ADDRESS;
-
-always @(posedge clk) begin
- if (rst) begin
- registerValue <= 'b0;
- end else begin
- if (registerSelect && we && !oe) registerValue <= WIDTH'(interfaceData);
- end
-end
-
-assign interfaceData = registerSelect && oe && !we ? 32'(registerValue) : 32'bz;
-assign currentValue = registerValue;
-
-endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Utility/counter.v b/verilog/rtl/Utility/counter.v
index 5989927..a2c078b 100644
--- a/verilog/rtl/Utility/counter.v
+++ b/verilog/rtl/Utility/counter.v
@@ -1,4 +1,4 @@
-module counter #(
+module Counter #(
parameter WIDTH = 8, // Width of the output
parameter DIV = 0, // number of bits to use as divisor
parameter TOP = 0, // max value, 0 = none
