Fixed spelling error in source file name.
diff --git a/openlane/ExperiarCore/config.tcl b/openlane/ExperiarCore/config.tcl
index f907839..6a4b7c9 100644
--- a/openlane/ExperiarCore/config.tcl
+++ b/openlane/ExperiarCore/config.tcl
@@ -15,7 +15,7 @@
$script_dir/../../verilog/rtl/ExperiarCore/JTAG.v \
$script_dir/../../verilog/rtl/ExperiarCore/JTAGRegister.v \
$script_dir/../../verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v \
- $script_dir/../../verilog/rtl/ExperiarCore/Memory/MemoryContorller.v \
+ $script_dir/../../verilog/rtl/ExperiarCore/Memory/MemoryController.v \
$script_dir/../../verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v \
$script_dir/../../verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v \
$script_dir/../../verilog/rtl/Peripherals/Registers/ConfigurationRegister.v \
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index cf9d940..f4747b1 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -9,7 +9,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/JTAG.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/JTAGRegister.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
--v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Memory/MemoryContorller.v
+-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Memory/MemoryController.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/Flash/Flash_top.v
diff --git a/verilog/rtl/ExperiarCore/Memory/MemoryContorller.v b/verilog/rtl/ExperiarCore/Memory/MemoryController.v
similarity index 100%
rename from verilog/rtl/ExperiarCore/Memory/MemoryContorller.v
rename to verilog/rtl/ExperiarCore/Memory/MemoryController.v
