Fixed performing load instructions not triggering a read from the local memory controller.
diff --git a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
index 95602d0..d66f53e 100644
--- a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
+++ b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
@@ -68,6 +68,7 @@
reg coreReadReady = 1'b0;
always @(posedge clk) begin
if (rst) coreReadReady <= 1'b0;
+ else if (!coreBusy) coreReadReady <= 1'b0;
else if (coreSRAMReadEnable) coreReadReady <= 1'b1;
else coreReadReady <= 1'b0;
end
