commit	7eff5974a4cff4d7a20ab5c6f158a0c6871d12e3	[log] [tgz]
author	Charlie <charlie.david.smith@hotmail.co.uk>	Mon May 16 23:00:43 2022 +0100
committer	Charlie <charlie.david.smith@hotmail.co.uk>	Mon May 16 23:00:43 2022 +0100
tree	fe35002dec07d79c09b91608d619e5678b1250eb
parent	f76defcbe5fcda02a6961deb864dfddfb3c99694 [diff]

Updated Makefile to work correctly when running verify scripts with the project in a symbolically linked directory.

Makefile[diff]

1 file changed

tree: fe35002dec07d79c09b91608d619e5678b1250eb

README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program.

Features

Block diagram of Experiar SoC

Dual RV32I cores
Per core SRAM
External flash controller
Larger shared block SRAM
VGA output using frame buffer in block SRAM
4x UART ports + 1 internal to caravel
2x SPI ports
4x PWM counters with 4x seperate outputs
DMA for UART peripheral

Memory Map

Memory map for Experiar SoC

ToDo

Flash controller
DMA
Block SRAM
VGA
Multi core controller
Fix all of the timeing errors
Test

Reference work and inspiration

Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
Caravel Documentation: Reference for caravel and configuration.