Updated testing setup to remove example tests, and provide a proper GPIO test which passes when using verify rtl.
diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO.c b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
new file mode 100644
index 0000000..1325ed6
--- /dev/null
+++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
@@ -0,0 +1,154 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+/*
+ IO Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+#define GPIO0_OE_ADDR ((uint32_t*)0x33031000)
+#define GPIO0_OUTPUT_ADDR ((uint32_t*)0x33031004)
+#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031008)
+#define GPIO1_OE_ADDR ((uint32_t*)0x33032000)
+#define GPIO1_OUTPUT_ADDR ((uint32_t*)0x33032004)
+#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032008)
+
+#define GPIO0_OE (*GPIO0_OE_ADDR)
+#define GPIO0_OUTPUT (*GPIO0_OUTPUT_ADDR)
+#define GPIO0_INPUT (*GPIO0_INPUT_ADDR)
+#define GPIO1_OE (*GPIO1_OE_ADDR)
+#define GPIO1_OUTPUT (*GPIO1_OUTPUT_ADDR)
+#define GPIO1_INPUT (*GPIO1_INPUT_ADDR)
+
+#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
+#define MPRJ_WB_DATA_LOCATION 0x30008000
+
+void wbWrite (uint32_t* location, uint32_t value)
+{
+ // Write the address
+ uint32_t locationData = (uint32_t)location;
+ MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+ // Write the data
+ uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+ *((volatile uint32_t*)writeAddress) = value;
+}
+
+uint32_t wbRead (uint32_t* location)
+{
+ // Write the address
+ uint32_t locationData = (uint32_t)location;
+ MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+ // Write the data
+ uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+ return *((volatile uint32_t*)writeAddress);
+}
+
+void nextTest (bool testPassing)
+{
+ uint32_t testPassingOutput = testPassing ? 0x1 << 12 : 0;
+ wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput | (0x1 << 13));
+ wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput);
+}
+
+void main ()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt
+
+ // Enable the wishbone bus
+ reg_wb_enable = 1;
+
+ // Enable GPIO
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1) {}
+
+ wbWrite (GPIO0_OE_ADDR, ~0x3F000);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0x1 << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0x3 << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0x7 << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0xF << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0xE << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0xC << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0x8 << 14);
+ wbWrite (GPIO0_OUTPUT_ADDR, 0);
+
+ bool inputTestPass = true;
+
+ wbWrite (GPIO1_OE_ADDR, ~0x00000);
+
+ nextTest (inputTestPass);
+ uint32_t ioData = wbRead (GPIO1_INPUT_ADDR);
+ wbWrite (GPIO0_OUTPUT_ADDR, (inputTestPass ? 0x1 << 12 : 0) | (ioData << 15));
+ if (ioData != 0x2) inputTestPass = false; // input = 2'b10
+
+ nextTest (inputTestPass);
+ ioData = wbRead (GPIO1_INPUT_ADDR);
+ wbWrite (GPIO0_OUTPUT_ADDR, (inputTestPass ? 0x1 << 12 : 0) | (ioData << 15));
+ if (ioData != 0x1) inputTestPass = false; // input = 2'b01
+
+ nextTest (inputTestPass);
+ ioData = wbRead (GPIO1_INPUT_ADDR);
+ wbWrite (GPIO0_OUTPUT_ADDR, (inputTestPass ? 0x1 << 12 : 0) | (ioData << 15));
+ if (ioData != 0x3) inputTestPass = false; // input = 2'b11
+
+ nextTest (inputTestPass);
+ ioData = wbRead (GPIO1_INPUT_ADDR);
+ wbWrite (GPIO0_OUTPUT_ADDR, (inputTestPass ? 0x1 << 12 : 0) | (ioData << 15));
+ if (ioData != 0) inputTestPass = false; // input = 2'b00
+
+ // Finish test
+ nextTest (inputTestPass);
+}
