commit	abf0b17672e555056b8a54651d20147bc31d3a79	[log] [tgz]
author	Charlie <charlie.david.smith@hotmail.co.uk>	Fri Apr 29 11:15:34 2022 +0100
committer	Charlie <charlie.david.smith@hotmail.co.uk>	Fri Apr 29 11:15:34 2022 +0100
tree	d4cdadd9b857d20514f70de3adcb6ff39d4db658
parent	f7da1ed9f9261c8cc03d76b26d9ce5a9062fdd9d [diff]

Added top files and config files for remaining peripherals.

openlane/Peripheral_GPIO/config.tcl[Added - diff]
openlane/Peripheral_GPIO/pin_order.cfg[Added - diff]
openlane/Peripheral_UART/config.tcl[Added - diff]
openlane/Peripheral_UART/pin_order.cfg[Added - diff]
openlane/Peripheral_WBPeripheralBusInterface/config.tcl[Added - diff]
openlane/Peripheral_WBPeripheralBusInterface/pin_order.cfg[Added - diff]
openlane/Peripherals/config.tcl[Added - diff]
openlane/Peripherals/macro.cfg[Added - diff]
openlane/Peripherals/pin_order.cfg[Added - diff]
openlane/Peripherals_Flat/config.tcl[Added - diff]
openlane/Peripherals_Flat/pin_order.cfg[Added - diff]
verilog/rtl/GPIO/GPIO_top.v[Deleted - diff]
verilog/rtl/Peripherals/GPIO/GPIO_top.v[Added - diff]
verilog/rtl/Peripherals/Peripherals_top.v[Added - diff]
verilog/rtl/Peripherals/SPI/SPIDevice.v[Added - diff]
verilog/rtl/Peripherals/UART/UART_Buffer.v[Renamed from verilog/rtl/UART/UART_Buffer.v - diff]
verilog/rtl/Peripherals/UART/UART_rx.v[Renamed from verilog/rtl/UART/UART_rx.v - diff]
verilog/rtl/Peripherals/UART/UART_top.v[Added - diff]
verilog/rtl/Peripherals/UART/UART_tx.v[Renamed from verilog/rtl/UART/UART_tx.v - diff]
verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v[Added - diff]
verilog/rtl/UART/UART_top.v[Deleted - diff]

21 files changed

tree: d4cdadd9b857d20514f70de3adcb6ff39d4db658

README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program