Fixed GL simulations not working properly due to missing pullup on mprj_io[3]. This is needed to make sure the management core doesn't end up in an invalid reset state. Also fixed nextTest method which wasn't correctly setting the test passed pin low if a test failed. This uncovered a some mistake made in the GPIO, memory, and UART tests, which are now also fixed. These included input pins not being connected to anything within the peripherals macro.
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index 3f90e15..98680d6 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -164,8 +164,3 @@
- name: Run DV GL tests
run: |
make verify-peripheralsGPIO-gl
- make verify-peripheralsUART-gl
- make verify-memory-gl
- make verify-video-gl
- make verify-corePC-gl
-
\ No newline at end of file
diff --git a/verilog/dv/corePC/corePC.c b/verilog/dv/corePC/corePC.c
index afedc4b..c40e0a6 100644
--- a/verilog/dv/corePC/corePC.c
+++ b/verilog/dv/corePC/corePC.c
@@ -96,8 +96,16 @@
void nextTest (bool testPassing)
{
- uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
- wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000);
+ if (testPassing)
+ {
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+ }
+ else
+ {
+ wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+ }
+
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
}
diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v
index 86ed378..143f8c5 100644
--- a/verilog/dv/corePC/corePC_tb.v
+++ b/verilog/dv/corePC/corePC_tb.v
@@ -30,6 +30,7 @@
wire succesOutput = mprj_io[12];
wire nextTestOutput = mprj_io[13];
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// External clock is used by default. Make this artificially fast for the
@@ -43,7 +44,12 @@
initial begin
$dumpfile("corePC.vcd");
+
+`ifdef SIM
$dumpvars(0, corePC_tb);
+`else
+ $dumpvars(1, corePC_tb);
+`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (700) begin
diff --git a/verilog/dv/memory/memory.c b/verilog/dv/memory/memory.c
index f0e8dc2..bb1ec7d 100644
--- a/verilog/dv/memory/memory.c
+++ b/verilog/dv/memory/memory.c
@@ -48,7 +48,7 @@
#define CORE0_SRAM ((uint32_t*)0x30000000)
#define CORE1_SRAM ((uint32_t*)0x31000000)
#define VGA_SRAM ((uint32_t*)0x32000000)
-#define SRAM_BANK_SIZE 0x1000u
+#define SRAM_BANK_SIZE 0x200
#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
#define MPRJ_WB_DATA_LOCATION 0x30008000
@@ -121,8 +121,16 @@
void nextTest (bool testPassing)
{
- uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
- wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000);
+ if (testPassing)
+ {
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+ }
+ else
+ {
+ wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+ }
+
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
}
diff --git a/verilog/dv/memory/memory_tb.v b/verilog/dv/memory/memory_tb.v
index d91e66c..b20e63c 100644
--- a/verilog/dv/memory/memory_tb.v
+++ b/verilog/dv/memory/memory_tb.v
@@ -30,6 +30,7 @@
wire succesOutput = mprj_io[12];
wire nextTestOutput = mprj_io[13];
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// External clock is used by default. Make this artificially fast for the
@@ -43,7 +44,12 @@
initial begin
$dumpfile("memory.vcd");
+
+`ifdef SIM
$dumpvars(0, memory_tb);
+`else
+ $dumpvars(1, memory_tb);
+`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (1500) begin
diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO.c b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
index d95f507..8e67636 100644
--- a/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
+++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
@@ -71,8 +71,16 @@
void nextTest (bool testPassing)
{
- uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
- wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000);
+ if (testPassing)
+ {
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+ }
+ else
+ {
+ wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+ }
+
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
}
@@ -107,6 +115,7 @@
reg_wb_enable = 1;
// Enable GPIO
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
@@ -130,32 +139,38 @@
wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x10000);
wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x20000);
wbWrite (GPIO0_OUTPUT_TOGGLE_ADDR, 0x3C000);
- wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x3C000);
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x3C000 | 0x01000); // Need to write to testPass pin as well, otherwise to goes low temporarily
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x04000);
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x08000);
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x10000);
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x20000);
nextTest (testPass);
+ wbWrite (GPIO0_OE_SET_ADDR, 0x00080);
+ uint32_t ioData = wbRead (GPIO0_INPUT_ADDR);
+ if (ioData != 0x80) testPass = false; // input = 1'b1
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | (((ioData >> 5) & 0xF) << 14));
+ nextTest (testPass);
+
wbWrite (GPIO1_OE_WRITE_ADDR, ~0x00000);
- uint32_t ioData = wbRead (GPIO1_INPUT_ADDR);
- wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | (ioData << 15));
+ ioData = wbRead (GPIO1_INPUT_ADDR);
if (ioData != 0x2) testPass = false; // input = 2'b10
-
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | ((ioData & 0xF) << 14));
nextTest (testPass);
+
ioData = wbRead (GPIO1_INPUT_ADDR);
- wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | (ioData << 15));
if (ioData != 0x1) testPass = false; // input = 2'b01
-
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | ((ioData & 0xF) << 14));
nextTest (testPass);
+
ioData = wbRead (GPIO1_INPUT_ADDR);
- wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | (ioData << 15));
if (ioData != 0x3) testPass = false; // input = 2'b11
-
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | ((ioData & 0xF) << 14));
nextTest (testPass);
+
ioData = wbRead (GPIO1_INPUT_ADDR);
- wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | (ioData << 15));
- if (ioData != 0) testPass = false; // input = 2'b00
+ if (ioData != 0x0) testPass = false; // input = 2'b00
+ wbWrite (GPIO0_OUTPUT_WRITE_ADDR, (testPass ? 0x01000 : 0) | ((ioData & 0xF) << 14));
// Finish test
nextTest (testPass);
diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
index 317341d..f3e5224 100644
--- a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
+++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
@@ -32,8 +32,19 @@
wire nextTestOutput = mprj_io[13];
wire[3:0] outputTestData = mprj_io[17:14];
+ // Need to add pullup to io3 otherwise GL simulation wont work
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
assign mprj_io[20:19] = inputTestData;
+ assign mprj_io[7] = 1'b1;
+
+ // Need to add pulls (can be up or down) to all unsed io so that input data is known
+ assign mprj_io[2:0] = 3'b0;
+ assign mprj_io[6:4] = 3'b0;
+ assign mprj_io[11:8] = 4'b0;
+ assign mprj_io[18] = 1'b0;
+ assign mprj_io[37:21] = 17'b0;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -47,6 +58,10 @@
// Generate input signal
initial begin
+ // Test input from first gpio bank
+ @(posedge nextTestOutput);
+
+ // Test input from second gpio bank
@(posedge nextTestOutput);
inputTestData = 2'b10;
@@ -62,10 +77,15 @@
initial begin
$dumpfile("peripheralsGPIO.vcd");
+
+`ifdef SIM
$dumpvars(0, peripheralsGPIO_tb);
+`else
+ $dumpvars(1, peripheralsGPIO_tb);
+`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (300) begin
+ repeat (400) begin
repeat (1000) @(posedge clock);
//$display("+1000 cycles");
end
@@ -98,6 +118,7 @@
@(posedge nextTestOutput);
@(posedge nextTestOutput);
@(posedge nextTestOutput);
+ @(posedge nextTestOutput);
// Wait for management core to output a output test result
@(posedge nextTestOutput);
diff --git a/verilog/dv/peripheralsUART/peripheralsUART.c b/verilog/dv/peripheralsUART/peripheralsUART.c
index 5b5a4c2..eed2e11 100644
--- a/verilog/dv/peripheralsUART/peripheralsUART.c
+++ b/verilog/dv/peripheralsUART/peripheralsUART.c
@@ -83,8 +83,16 @@
void nextTest (bool testPassing)
{
- uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
- wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000);
+ if (testPassing)
+ {
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+ }
+ else
+ {
+ wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+ }
+
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
}
@@ -178,9 +186,9 @@
// Read back data from peripheral
if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[0])) testPass = false;
- if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[0])) testPass = false;
- if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[0])) testPass = false;
- if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[0])) testPass = false;
+ if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[1])) testPass = false;
+ if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[2])) testPass = false;
+ if (wbRead (SOC_UART0_RX_ADDR) != (0x100 | testData[3])) testPass = false;
nextTest (testPass);
// Try reading an extra time and make sure there is no data
diff --git a/verilog/dv/peripheralsUART/peripheralsUART_tb.v b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
index 489f174..29b4bc8 100644
--- a/verilog/dv/peripheralsUART/peripheralsUART_tb.v
+++ b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
@@ -30,6 +30,7 @@
wire succesOutput = mprj_io[12];
wire nextTestOutput = mprj_io[13];
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// External clock is used by default. Make this artificially fast for the
@@ -43,7 +44,12 @@
initial begin
$dumpfile("peripheralsUART.vcd");
+
+`ifdef SIM
$dumpvars(0, peripheralsUART_tb);
+`else
+ $dumpvars(1, peripheralsUART_tb);
+`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (750) begin
diff --git a/verilog/dv/video/video.c b/verilog/dv/video/video.c
index 8c2379f..3139cd7 100644
--- a/verilog/dv/video/video.c
+++ b/verilog/dv/video/video.c
@@ -94,8 +94,16 @@
void nextTest (bool testPassing)
{
- uint32_t testPassingOutput = testPassing ? 0x01000 : 0;
- wbWrite (GPIO0_OUTPUT_SET_ADDR, testPassingOutput | 0x02000);
+ if (testPassing)
+ {
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+ }
+ else
+ {
+ wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+ wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+ }
+
wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
}
diff --git a/verilog/dv/video/video_tb.v b/verilog/dv/video/video_tb.v
index d201d52..9266622 100644
--- a/verilog/dv/video/video_tb.v
+++ b/verilog/dv/video/video_tb.v
@@ -34,6 +34,7 @@
wire vgaVSync = mprj_io[36];
wire vgaHSync = mprj_io[37];
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
reg timingValid = 1'b1;
@@ -50,7 +51,12 @@
initial begin
$dumpfile("video.vcd");
+
+`ifdef SIM
$dumpvars(0, video_tb);
+`else
+ $dumpvars(1, video_tb);
+`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (1000) begin
diff --git a/verilog/rtl/CaravelHost/WBAddressExtension.v b/verilog/rtl/CaravelHost/WBAddressExtension.v
index cae9c4d..5a11088 100644
--- a/verilog/rtl/CaravelHost/WBAddressExtension.v
+++ b/verilog/rtl/CaravelHost/WBAddressExtension.v
@@ -9,8 +9,8 @@
input wire[3:0] wbs_sel_i,
input wire[31:0] wbs_adr_i,
input wire[31:0] wbs_data_i,
- output wire wbs_ack_o,
- output wire[31:0] wbs_data_o,
+ output reg wbs_ack_o,
+ output reg[31:0] wbs_data_o,
// Wishbone connection to user space
output wire userSpace_wb_cyc_i,
@@ -26,12 +26,13 @@
reg[31:0] currentAddress = 32'b0;
// Connect user space wishbone bus
- wire userSpaceSelect = wbs_adr_i[15];
+ wire busAccess = wbs_cyc_i && wbs_adr_i[31:16] == 16'h3000;
+ wire userSpaceSelect = busAccess && wbs_adr_i[15];
wire[14:0] addressOffset = wbs_adr_i[14:0];
- assign userSpace_wb_cyc_i = wbs_cyc_i && userSpaceSelect;
- assign userSpace_wb_stb_i = wbs_stb_i && userSpaceSelect;
- assign userSpace_wb_we_i = wbs_we_i && userSpaceSelect;
+ assign userSpace_wb_cyc_i = userSpaceSelect ? wbs_cyc_i : 1'b0;
+ assign userSpace_wb_stb_i = userSpaceSelect ? wbs_stb_i : 1'b0;
+ assign userSpace_wb_we_i = userSpaceSelect ? wbs_we_i : 1'b0;
assign userSpace_wb_sel_i = userSpaceSelect ? wbs_sel_i : 4'b0000;
assign userSpace_wb_adr_i = userSpaceSelect ? { currentAddress[31:15], addressOffset } : 32'b0;
assign userSpace_wb_data_i = userSpaceSelect ? wbs_data_i : 32'b0;
@@ -60,7 +61,7 @@
acknowledge <= 1'b0;
dataRead_buffered <= ~32'b0;
- if (wbs_cyc_i && !userSpaceSelect) begin
+ if (wbs_cyc_i && busAccess && !userSpaceSelect) begin
if (wbs_stb_i) begin
if (wbs_we_i) begin
state <= STATE_WRITE_SINGLE;
@@ -101,7 +102,19 @@
end
// Connect wishbone return signals
- assign wbs_ack_o = userSpaceSelect ? userSpace_wb_ack_o : acknowledge;
- assign wbs_data_o = userSpaceSelect ? userSpace_wb_data_o : dataRead_buffered;
+ always @(*) begin
+ if (busAccess) begin
+ if (userSpaceSelect) begin
+ wbs_ack_o <= userSpace_wb_ack_o;
+ wbs_data_o <= userSpace_wb_data_o;
+ end else begin
+ wbs_ack_o <= acknowledge;
+ wbs_data_o <= dataRead_buffered;
+ end
+ end else begin
+ wbs_ack_o <= 1'b0;
+ wbs_data_o <= 32'b0;
+ end
+ end
endmodule
\ No newline at end of file
diff --git a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
index ca74d52..95602d0 100644
--- a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
+++ b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
@@ -90,10 +90,10 @@
wire rwBankSelect = rwAddress[SRAM_ADDRESS_SIZE];
assign wbDataRead = {
- wbByteSelect[3] && wbReadReady ? rwPortReadData[31:24] : 8'h00,
- wbByteSelect[2] && wbReadReady ? rwPortReadData[23:16] : 8'h00,
- wbByteSelect[1] && wbReadReady ? rwPortReadData[15:8] : 8'h00,
- wbByteSelect[0] && wbReadReady ? rwPortReadData[7:0] : 8'h00
+ wbByteSelect[3] && wbReadReady ? rwPortReadData[31:24] : ~8'h00,
+ wbByteSelect[2] && wbReadReady ? rwPortReadData[23:16] : ~8'h00,
+ wbByteSelect[1] && wbReadReady ? rwPortReadData[15:8] : ~8'h00,
+ wbByteSelect[0] && wbReadReady ? rwPortReadData[7:0] : ~8'h00
};
// Read port
@@ -102,10 +102,10 @@
wire rBankSelect = rAddress[SRAM_ADDRESS_SIZE];
assign coreDataRead = {
- coreByteSelect[3] && coreReadReady ? rPortReadData[31:24] : 8'h00,
- coreByteSelect[2] && coreReadReady ? rPortReadData[23:16] : 8'h00,
- coreByteSelect[1] && coreReadReady ? rPortReadData[15:8] : 8'h00,
- coreByteSelect[0] && coreReadReady ? rPortReadData[7:0] : 8'h00
+ coreByteSelect[3] && coreReadReady ? rPortReadData[31:24] : ~8'h00,
+ coreByteSelect[2] && coreReadReady ? rPortReadData[23:16] : ~8'h00,
+ coreByteSelect[1] && coreReadReady ? rPortReadData[15:8] : ~8'h00,
+ coreByteSelect[0] && coreReadReady ? rPortReadData[7:0] : ~8'h00
};
// SRAM connections
diff --git a/verilog/rtl/Peripherals/GPIO/GPIO_top.v b/verilog/rtl/Peripherals/GPIO/GPIO_top.v
index c911402..f0d8eef 100644
--- a/verilog/rtl/Peripherals/GPIO/GPIO_top.v
+++ b/verilog/rtl/Peripherals/GPIO/GPIO_top.v
@@ -77,7 +77,7 @@
.gpio_output(gpio1_output),
.gpio_oe(gpio1_oe));
- assign requestOutput = device1OutputRequest || device1OutputRequest;
+ assign requestOutput = device0OutputRequest || device1OutputRequest;
assign peripheralBus_dataRead = device0OutputRequest ? device0OutputData :
device1OutputRequest ? device1OutputData :
~32'b0;
diff --git a/verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py b/verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py
index 299ba63..1abb9a1 100644
--- a/verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py
+++ b/verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py
@@ -194,31 +194,31 @@
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = {IO_INPUT};\n")
- outputLines.append(f" assign {pinName.lower()} = inputBuffer[PIN_{pinName}];\n")
+ outputLines.append(f" assign {pinName.lower()} = io_in[PIN_{pinName}];\n")
def writeIRQPin(outputLines:list[str], pinName:str, allowGPIO:bool):
if allowGPIO:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = irq_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = irq_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = irq_en ? 1'b0 : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = irq_en ? {IO_INPUT} : gpio_oe[PIN_{pinName}];\n")
- outputLines.append(f" assign irq_in = irq_en ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign irq_in = irq_en ? io_in[PIN_{pinName}] : 1'b0;\n")
else:
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = {IO_INPUT};\n")
- outputLines.append(f" assign irq_in = inputBuffer[PIN_{pinName}];\n")
+ outputLines.append(f" assign irq_in = io_in[PIN_{pinName}];\n")
def writeFlashPin(outputLines:list[str], pinName:str, isOutput:bool, pinType:str, allowGPIO:bool):
if allowGPIO:
if isOutput:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = flash_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = flash_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = flash_en ? flash_{pinType.lower()} : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = flash_en ? {IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = flash_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = flash_en ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = flash_en ? flash_{pinType.lower()}_write : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = flash_en ? !flash_{pinType.lower()}_we : gpio_oe[PIN_{pinName}];\n")
- outputLines.append(f" assign flash_{pinType.lower()}_read = flash_en && !flash_{pinType.lower()}_we ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign flash_{pinType.lower()}_read = flash_en && !flash_{pinType.lower()}_we ? io_in[PIN_{pinName}] : 1'b0;\n")
else:
if isOutput:
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
@@ -228,19 +228,19 @@
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = flash_{pinType.lower()}_write;\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = !flash_{pinType.lower()}_we;\n")
- outputLines.append(f" assign flash_{pinType.lower()}_read = !flash_{pinType.lower()}_we ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign flash_{pinType.lower()}_read = !flash_{pinType.lower()}_we ? io_in[PIN_{pinName}] : 1'b0;\n")
def writeUARTPin(outputLines:list[str], pinName:str, uartIndex:int, isOutput:bool, allowGPIO:bool):
if allowGPIO:
if isOutput:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = uart_en[{uartIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = uart_en[{uartIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = uart_en[{uartIndex}] ? uart_tx[{uartIndex}] : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = uart_en[{uartIndex}] ? {IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = uart_en[{uartIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = uart_en[{uartIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = uart_en[{uartIndex}] ? 1'b0 : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = uart_en[{uartIndex}] ? {IO_INPUT} : gpio_oe[PIN_{pinName}];\n")
- outputLines.append(f" assign uart_rx[{uartIndex}] = uart_en[{uartIndex}] ? inputBuffer[PIN_{pinName}] : 1'b1;\n") # UART Rx defaults to high when not in use
+ outputLines.append(f" assign uart_rx[{uartIndex}] = uart_en[{uartIndex}] ? io_in[PIN_{pinName}] : 1'b1;\n") # UART Rx defaults to high when not in use
else:
if isOutput:
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
@@ -250,11 +250,11 @@
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = {IO_INPUT};\n")
- outputLines.append(f" assign uart_rx[{uartIndex}] = inputBuffer[PIN_{pinName}];\n")
+ outputLines.append(f" assign uart_rx[{uartIndex}] = io_in[PIN_{pinName}];\n")
def writePWMPin(outputLines:list[str], pinName:str, pwmIndex:int, allowGPIO:bool):
if allowGPIO:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = pwm_en[{pwmIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = pwm_en[{pwmIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = pwm_en[{pwmIndex}] ? pwm_out[{pwmIndex}] : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = pwm_en[{pwmIndex}] ? {IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
@@ -265,14 +265,14 @@
def writeSPIPin(outputLines:list[str], pinName:str, spiIndex:int, isOutput:bool, pinType:str, allowGPIO:bool):
if allowGPIO:
if isOutput:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = spi_en[{spiIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = spi_en[{spiIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = spi_en[{spiIndex}] ? spi_{pinType.lower()}[{spiIndex}] : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = spi_en[{spiIndex}] ? {IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = spi_en[{spiIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = spi_en[{spiIndex}] ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = spi_en[{spiIndex}] ? 1'b0 : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = spi_en[{spiIndex}] ? {IO_INPUT} : gpio_oe[PIN_{pinName}];\n")
- outputLines.append(f" assign spi_{pinType.lower()}[{spiIndex}] = spi_en[{spiIndex}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign spi_{pinType.lower()}[{spiIndex}] = spi_en[{spiIndex}] ? io_in[PIN_{pinName}] : 1'b0;\n")
else:
if isOutput:
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
@@ -282,16 +282,16 @@
outputLines.append(f" assign gpio_input[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = 1'b0;\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = {IO_INPUT};\n")
- outputLines.append(f" assign spi_{pinType.lower()}[{spiIndex}] = inputBuffer[PIN_{pinName}];\n")
+ outputLines.append(f" assign spi_{pinType.lower()}[{spiIndex}] = io_in[PIN_{pinName}];\n")
def writeVGAPin(outputLines:list[str], pinName:str, pinType:str, pinIndex:int, allowGPIO:bool):
if allowGPIO:
if pinIndex >= 0:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = vgaEnable ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = vgaEnable ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = vgaEnable ? vga_{pinType.lower()}[{pinIndex}] : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = vgaEnable ?{IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = vgaEnable ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = vgaEnable ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = vgaEnable ? vga_{pinType.lower()} : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = vgaEnable ?{IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
@@ -306,7 +306,7 @@
def writeBlinkPin(outputLines:list[str], pinName:str, blinkIndex:int, allowGPIO:bool):
if allowGPIO:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = blinkEnabled ? 1'b0 : gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = blinkEnabled ? 1'b0 : gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = blinkEnabled ? blink[{blinkIndex}] : gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = blinkEnabled ? {IO_OUTPUT} : gpio_oe[PIN_{pinName}];\n")
else:
@@ -317,11 +317,11 @@
def writeUndefinedPin(outputLines:list[str], pinName:str, isOutput:bool, allowGPIO:bool):
if allowGPIO:
if isOutput:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = gpio_oe[PIN_{pinName}];\n")
else:
- outputLines.append(f" assign gpio_input[PIN_{pinName}] = gpio_oe[PIN_{pinName}] ? inputBuffer[PIN_{pinName}] : 1'b0;\n")
+ outputLines.append(f" assign gpio_input[PIN_{pinName}] = gpio_oe[PIN_{pinName}] ? io_in[PIN_{pinName}] : 1'b0;\n")
outputLines.append(f" assign io_out[PIN_{pinName}] = gpio_output[PIN_{pinName}];\n")
outputLines.append(f" assign io_oeb[PIN_{pinName}] = gpio_oe[PIN_{pinName}];\n")
else:
diff --git a/verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v b/verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v
index b2c20ea..c3d4eda 100644
--- a/verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v
+++ b/verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v
@@ -64,14 +64,6 @@
output wire[1:0] probe_blink
);
- // Buffer inputs
- wire[`MPRJ_IO_PADS-1:0] inputBuffer;
-
- genvar i;
- generate
- for (i = 0; i < `MPRJ_IO_PADS; i = i + 1) assign inputBuffer[i] = (io_in[i] === 1'dx) ? 1'b0 : io_in[i];
- endgenerate
-
// Test blink
localparam BLINK_CLOCK_DIV = 26;
reg blinkEnabled = 1'b1;
@@ -148,7 +140,7 @@
assign gpio_input[PIN_JTAG] = 1'b0;
assign io_out[PIN_JTAG] = 1'b0;
assign io_oeb[PIN_JTAG] = 1'b1;
- assign jtag = inputBuffer[PIN_JTAG];
+ assign jtag = io_in[PIN_JTAG];
// IO01-PIN_SDO: Output
localparam PIN_SDO = 1;
@@ -161,28 +153,28 @@
assign gpio_input[PIN_SDI] = 1'b0;
assign io_out[PIN_SDI] = 1'b0;
assign io_oeb[PIN_SDI] = 1'b1;
- assign sdi = inputBuffer[PIN_SDI];
+ assign sdi = io_in[PIN_SDI];
// IO03-PIN_CSB: Input
localparam PIN_CSB = 3;
assign gpio_input[PIN_CSB] = 1'b0;
assign io_out[PIN_CSB] = 1'b0;
assign io_oeb[PIN_CSB] = 1'b1;
- assign csb = inputBuffer[PIN_CSB];
+ assign csb = io_in[PIN_CSB];
// IO04-PIN_SCK: Input
localparam PIN_SCK = 4;
assign gpio_input[PIN_SCK] = 1'b0;
assign io_out[PIN_SCK] = 1'b0;
assign io_oeb[PIN_SCK] = 1'b1;
- assign sck = inputBuffer[PIN_SCK];
+ assign sck = io_in[PIN_SCK];
// IO05-PIN_UART1_RX: Input
localparam PIN_UART1_RX = 5;
assign gpio_input[PIN_UART1_RX] = 1'b0;
assign io_out[PIN_UART1_RX] = 1'b0;
assign io_oeb[PIN_UART1_RX] = 1'b1;
- assign uart_rx[1] = inputBuffer[PIN_UART1_RX];
+ assign uart_rx[1] = io_in[PIN_UART1_RX];
// IO06-PIN_UART1_TX: Output
localparam PIN_UART1_TX = 6;
@@ -192,10 +184,10 @@
// IO07-PIN_IRQ: Input
localparam PIN_IRQ = 7;
- assign gpio_input[PIN_IRQ] = irq_en ? 1'b0 : gpio_oe[PIN_IRQ] ? inputBuffer[PIN_IRQ] : 1'b0;
+ assign gpio_input[PIN_IRQ] = irq_en ? 1'b0 : gpio_oe[PIN_IRQ] ? io_in[PIN_IRQ] : 1'b0;
assign io_out[PIN_IRQ] = irq_en ? 1'b0 : gpio_output[PIN_IRQ];
assign io_oeb[PIN_IRQ] = irq_en ? 1'b1 : gpio_oe[PIN_IRQ];
- assign irq_in = irq_en ? inputBuffer[PIN_IRQ] : 1'b0;
+ assign irq_in = irq_en ? io_in[PIN_IRQ] : 1'b0;
// IO08-PIN_FLASH_CSB: Output
localparam PIN_FLASH_CSB = 8;
@@ -214,123 +206,123 @@
assign gpio_input[PIN_FLASH_IO0] = 1'b0;
assign io_out[PIN_FLASH_IO0] = flash_io0_write;
assign io_oeb[PIN_FLASH_IO0] = !flash_io0_we;
- assign flash_io0_read = !flash_io0_we ? inputBuffer[PIN_FLASH_IO0] : 1'b0;
+ assign flash_io0_read = !flash_io0_we ? io_in[PIN_FLASH_IO0] : 1'b0;
// IO11-PIN_FLASH_IO1: InOut
localparam PIN_FLASH_IO1 = 11;
assign gpio_input[PIN_FLASH_IO1] = 1'b0;
assign io_out[PIN_FLASH_IO1] = flash_io1_write;
assign io_oeb[PIN_FLASH_IO1] = !flash_io1_we;
- assign flash_io1_read = !flash_io1_we ? inputBuffer[PIN_FLASH_IO1] : 1'b0;
+ assign flash_io1_read = !flash_io1_we ? io_in[PIN_FLASH_IO1] : 1'b0;
// IO12-PIN_PWM0: Output
localparam PIN_PWM0 = 12;
- assign gpio_input[PIN_PWM0] = pwm_en[0] ? 1'b0 : gpio_oe[PIN_PWM0] ? inputBuffer[PIN_PWM0] : 1'b0;
+ assign gpio_input[PIN_PWM0] = pwm_en[0] ? 1'b0 : gpio_oe[PIN_PWM0] ? io_in[PIN_PWM0] : 1'b0;
assign io_out[PIN_PWM0] = pwm_en[0] ? pwm_out[0] : gpio_output[PIN_PWM0];
assign io_oeb[PIN_PWM0] = pwm_en[0] ? 1'b0 : gpio_oe[PIN_PWM0];
// IO13-PIN_PWM1: Output
localparam PIN_PWM1 = 13;
- assign gpio_input[PIN_PWM1] = pwm_en[1] ? 1'b0 : gpio_oe[PIN_PWM1] ? inputBuffer[PIN_PWM1] : 1'b0;
+ assign gpio_input[PIN_PWM1] = pwm_en[1] ? 1'b0 : gpio_oe[PIN_PWM1] ? io_in[PIN_PWM1] : 1'b0;
assign io_out[PIN_PWM1] = pwm_en[1] ? pwm_out[1] : gpio_output[PIN_PWM1];
assign io_oeb[PIN_PWM1] = pwm_en[1] ? 1'b0 : gpio_oe[PIN_PWM1];
// IO14-PIN_PWM2: Output
localparam PIN_PWM2 = 14;
- assign gpio_input[PIN_PWM2] = pwm_en[2] ? 1'b0 : gpio_oe[PIN_PWM2] ? inputBuffer[PIN_PWM2] : 1'b0;
+ assign gpio_input[PIN_PWM2] = pwm_en[2] ? 1'b0 : gpio_oe[PIN_PWM2] ? io_in[PIN_PWM2] : 1'b0;
assign io_out[PIN_PWM2] = pwm_en[2] ? pwm_out[2] : gpio_output[PIN_PWM2];
assign io_oeb[PIN_PWM2] = pwm_en[2] ? 1'b0 : gpio_oe[PIN_PWM2];
// IO15-PIN_PWM3: Output
localparam PIN_PWM3 = 15;
- assign gpio_input[PIN_PWM3] = pwm_en[3] ? 1'b0 : gpio_oe[PIN_PWM3] ? inputBuffer[PIN_PWM3] : 1'b0;
+ assign gpio_input[PIN_PWM3] = pwm_en[3] ? 1'b0 : gpio_oe[PIN_PWM3] ? io_in[PIN_PWM3] : 1'b0;
assign io_out[PIN_PWM3] = pwm_en[3] ? pwm_out[3] : gpio_output[PIN_PWM3];
assign io_oeb[PIN_PWM3] = pwm_en[3] ? 1'b0 : gpio_oe[PIN_PWM3];
// IO16-PIN_PWM4: Output
localparam PIN_PWM4 = 16;
- assign gpio_input[PIN_PWM4] = pwm_en[4] ? 1'b0 : gpio_oe[PIN_PWM4] ? inputBuffer[PIN_PWM4] : 1'b0;
+ assign gpio_input[PIN_PWM4] = pwm_en[4] ? 1'b0 : gpio_oe[PIN_PWM4] ? io_in[PIN_PWM4] : 1'b0;
assign io_out[PIN_PWM4] = pwm_en[4] ? pwm_out[4] : gpio_output[PIN_PWM4];
assign io_oeb[PIN_PWM4] = pwm_en[4] ? 1'b0 : gpio_oe[PIN_PWM4];
// IO17-PIN_PWM5: Output
localparam PIN_PWM5 = 17;
- assign gpio_input[PIN_PWM5] = pwm_en[5] ? 1'b0 : gpio_oe[PIN_PWM5] ? inputBuffer[PIN_PWM5] : 1'b0;
+ assign gpio_input[PIN_PWM5] = pwm_en[5] ? 1'b0 : gpio_oe[PIN_PWM5] ? io_in[PIN_PWM5] : 1'b0;
assign io_out[PIN_PWM5] = pwm_en[5] ? pwm_out[5] : gpio_output[PIN_PWM5];
assign io_oeb[PIN_PWM5] = pwm_en[5] ? 1'b0 : gpio_oe[PIN_PWM5];
// IO18-PIN_PWM6: Output
localparam PIN_PWM6 = 18;
- assign gpio_input[PIN_PWM6] = pwm_en[6] ? 1'b0 : gpio_oe[PIN_PWM6] ? inputBuffer[PIN_PWM6] : 1'b0;
+ assign gpio_input[PIN_PWM6] = pwm_en[6] ? 1'b0 : gpio_oe[PIN_PWM6] ? io_in[PIN_PWM6] : 1'b0;
assign io_out[PIN_PWM6] = pwm_en[6] ? pwm_out[6] : gpio_output[PIN_PWM6];
assign io_oeb[PIN_PWM6] = pwm_en[6] ? 1'b0 : gpio_oe[PIN_PWM6];
// IO19-PIN_UART2_RX: Input
localparam PIN_UART2_RX = 19;
- assign gpio_input[PIN_UART2_RX] = uart_en[2] ? 1'b0 : gpio_oe[PIN_UART2_RX] ? inputBuffer[PIN_UART2_RX] : 1'b0;
+ assign gpio_input[PIN_UART2_RX] = uart_en[2] ? 1'b0 : gpio_oe[PIN_UART2_RX] ? io_in[PIN_UART2_RX] : 1'b0;
assign io_out[PIN_UART2_RX] = uart_en[2] ? 1'b0 : gpio_output[PIN_UART2_RX];
assign io_oeb[PIN_UART2_RX] = uart_en[2] ? 1'b1 : gpio_oe[PIN_UART2_RX];
- assign uart_rx[2] = uart_en[2] ? inputBuffer[PIN_UART2_RX] : 1'b1;
+ assign uart_rx[2] = uart_en[2] ? io_in[PIN_UART2_RX] : 1'b1;
// IO20-PIN_UART2_TX: Output
localparam PIN_UART2_TX = 20;
- assign gpio_input[PIN_UART2_TX] = uart_en[2] ? 1'b0 : gpio_oe[PIN_UART2_TX] ? inputBuffer[PIN_UART2_TX] : 1'b0;
+ assign gpio_input[PIN_UART2_TX] = uart_en[2] ? 1'b0 : gpio_oe[PIN_UART2_TX] ? io_in[PIN_UART2_TX] : 1'b0;
assign io_out[PIN_UART2_TX] = uart_en[2] ? uart_tx[2] : gpio_output[PIN_UART2_TX];
assign io_oeb[PIN_UART2_TX] = uart_en[2] ? 1'b0 : gpio_oe[PIN_UART2_TX];
// IO21-PIN_PWM7: Output
localparam PIN_PWM7 = 21;
- assign gpio_input[PIN_PWM7] = pwm_en[7] ? 1'b0 : gpio_oe[PIN_PWM7] ? inputBuffer[PIN_PWM7] : 1'b0;
+ assign gpio_input[PIN_PWM7] = pwm_en[7] ? 1'b0 : gpio_oe[PIN_PWM7] ? io_in[PIN_PWM7] : 1'b0;
assign io_out[PIN_PWM7] = pwm_en[7] ? pwm_out[7] : gpio_output[PIN_PWM7];
assign io_oeb[PIN_PWM7] = pwm_en[7] ? 1'b0 : gpio_oe[PIN_PWM7];
// IO22-PIN_SPI0_CLK: Output
localparam PIN_SPI0_CLK = 22;
- assign gpio_input[PIN_SPI0_CLK] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CLK] ? inputBuffer[PIN_SPI0_CLK] : 1'b0;
+ assign gpio_input[PIN_SPI0_CLK] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CLK] ? io_in[PIN_SPI0_CLK] : 1'b0;
assign io_out[PIN_SPI0_CLK] = spi_en[0] ? spi_clk[0] : gpio_output[PIN_SPI0_CLK];
assign io_oeb[PIN_SPI0_CLK] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CLK];
// IO23-PIN_SPI0_MOSI: Output
localparam PIN_SPI0_MOSI = 23;
- assign gpio_input[PIN_SPI0_MOSI] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_MOSI] ? inputBuffer[PIN_SPI0_MOSI] : 1'b0;
+ assign gpio_input[PIN_SPI0_MOSI] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_MOSI] ? io_in[PIN_SPI0_MOSI] : 1'b0;
assign io_out[PIN_SPI0_MOSI] = spi_en[0] ? spi_mosi[0] : gpio_output[PIN_SPI0_MOSI];
assign io_oeb[PIN_SPI0_MOSI] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_MOSI];
// IO24-PIN_SPI0_MISO: Input
localparam PIN_SPI0_MISO = 24;
- assign gpio_input[PIN_SPI0_MISO] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_MISO] ? inputBuffer[PIN_SPI0_MISO] : 1'b0;
+ assign gpio_input[PIN_SPI0_MISO] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_MISO] ? io_in[PIN_SPI0_MISO] : 1'b0;
assign io_out[PIN_SPI0_MISO] = spi_en[0] ? 1'b0 : gpio_output[PIN_SPI0_MISO];
assign io_oeb[PIN_SPI0_MISO] = spi_en[0] ? 1'b1 : gpio_oe[PIN_SPI0_MISO];
- assign spi_miso[0] = spi_en[0] ? inputBuffer[PIN_SPI0_MISO] : 1'b0;
+ assign spi_miso[0] = spi_en[0] ? io_in[PIN_SPI0_MISO] : 1'b0;
// IO25-PIN_SPI0_CS: Output
localparam PIN_SPI0_CS = 25;
- assign gpio_input[PIN_SPI0_CS] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CS] ? inputBuffer[PIN_SPI0_CS] : 1'b0;
+ assign gpio_input[PIN_SPI0_CS] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CS] ? io_in[PIN_SPI0_CS] : 1'b0;
assign io_out[PIN_SPI0_CS] = spi_en[0] ? spi_cs[0] : gpio_output[PIN_SPI0_CS];
assign io_oeb[PIN_SPI0_CS] = spi_en[0] ? 1'b0 : gpio_oe[PIN_SPI0_CS];
// IO26-PIN_UART3_RX: Input
localparam PIN_UART3_RX = 26;
- assign gpio_input[PIN_UART3_RX] = uart_en[3] ? 1'b0 : gpio_oe[PIN_UART3_RX] ? inputBuffer[PIN_UART3_RX] : 1'b0;
+ assign gpio_input[PIN_UART3_RX] = uart_en[3] ? 1'b0 : gpio_oe[PIN_UART3_RX] ? io_in[PIN_UART3_RX] : 1'b0;
assign io_out[PIN_UART3_RX] = uart_en[3] ? 1'b0 : gpio_output[PIN_UART3_RX];
assign io_oeb[PIN_UART3_RX] = uart_en[3] ? 1'b1 : gpio_oe[PIN_UART3_RX];
- assign uart_rx[3] = uart_en[3] ? inputBuffer[PIN_UART3_RX] : 1'b1;
+ assign uart_rx[3] = uart_en[3] ? io_in[PIN_UART3_RX] : 1'b1;
// IO27-PIN_UART3_TX: Output
localparam PIN_UART3_TX = 27;
- assign gpio_input[PIN_UART3_TX] = uart_en[3] ? 1'b0 : gpio_oe[PIN_UART3_TX] ? inputBuffer[PIN_UART3_TX] : 1'b0;
+ assign gpio_input[PIN_UART3_TX] = uart_en[3] ? 1'b0 : gpio_oe[PIN_UART3_TX] ? io_in[PIN_UART3_TX] : 1'b0;
assign io_out[PIN_UART3_TX] = uart_en[3] ? uart_tx[3] : gpio_output[PIN_UART3_TX];
assign io_oeb[PIN_UART3_TX] = uart_en[3] ? 1'b0 : gpio_oe[PIN_UART3_TX];
// IO28-PIN_BLINK0: Output
localparam PIN_BLINK0 = 28;
- assign gpio_input[PIN_BLINK0] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK0] ? inputBuffer[PIN_BLINK0] : 1'b0;
+ assign gpio_input[PIN_BLINK0] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK0] ? io_in[PIN_BLINK0] : 1'b0;
assign io_out[PIN_BLINK0] = blinkEnabled ? blink[0] : gpio_output[PIN_BLINK0];
assign io_oeb[PIN_BLINK0] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK0];
// IO29-PIN_BLINK1: Output
localparam PIN_BLINK1 = 29;
- assign gpio_input[PIN_BLINK1] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK1] ? inputBuffer[PIN_BLINK1] : 1'b0;
+ assign gpio_input[PIN_BLINK1] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK1] ? io_in[PIN_BLINK1] : 1'b0;
assign io_out[PIN_BLINK1] = blinkEnabled ? blink[1] : gpio_output[PIN_BLINK1];
assign io_oeb[PIN_BLINK1] = blinkEnabled ? 1'b0 : gpio_oe[PIN_BLINK1];
diff --git a/verilog/rtl/Peripherals/PWM/PWMDevice.v b/verilog/rtl/Peripherals/PWM/PWMDevice.v
index 7597e20..b24a5a8 100644
--- a/verilog/rtl/Peripherals/PWM/PWMDevice.v
+++ b/verilog/rtl/Peripherals/PWM/PWMDevice.v
@@ -109,7 +109,7 @@
wire[OUTPUTS-1:0] compareRegisterOutputRequest;
wire[(32 * OUTPUTS) - 1:0] compareRegisterOutputData;
- Mux #(.WIDTH(32), .INPUTS(OUTPUTS)) mux(
+ Mux #(.WIDTH(32), .INPUTS(OUTPUTS), .DEFAULT(~32'b0)) mux(
.select(compareRegisterOutputRequest),
.in(compareRegisterOutputData),
.out(peripheralBus_dataRead),
diff --git a/verilog/rtl/Peripherals/PWM/PWM_top.v b/verilog/rtl/Peripherals/PWM/PWM_top.v
index 900c916..3920335 100644
--- a/verilog/rtl/Peripherals/PWM/PWM_top.v
+++ b/verilog/rtl/Peripherals/PWM/PWM_top.v
@@ -36,7 +36,7 @@
wire[DEVICE_COUNT-1:0] deviceOutputRequest;
wire[(32 * DEVICE_COUNT) - 1:0] deviceOutputData;
- Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT)) mux(
+ Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT), .DEFAULT(~32'b0)) mux(
.select(deviceOutputRequest),
.in(deviceOutputData),
.out(peripheralBus_dataRead),
diff --git a/verilog/rtl/Peripherals/Peripherals_top.v b/verilog/rtl/Peripherals/Peripherals_top.v
index 67f7f90..a97c72e 100644
--- a/verilog/rtl/Peripherals/Peripherals_top.v
+++ b/verilog/rtl/Peripherals/Peripherals_top.v
@@ -245,7 +245,7 @@
spi_requestOutput: peripheralBus_dataRead <= spi_peripheralBus_dataRead;
pwm_requestOutput: peripheralBus_dataRead <= pwm_peripheralBus_dataRead;
gpio_requestOutput: peripheralBus_dataRead <= gpio_peripheralBus_dataRead;
- default: peripheralBus_dataRead <= 32'b0;
+ default: peripheralBus_dataRead <= ~32'b0;
endcase
end
diff --git a/verilog/rtl/Peripherals/SPI/SPI_top.v b/verilog/rtl/Peripherals/SPI/SPI_top.v
index 2c043b2..567bc46 100644
--- a/verilog/rtl/Peripherals/SPI/SPI_top.v
+++ b/verilog/rtl/Peripherals/SPI/SPI_top.v
@@ -39,7 +39,7 @@
wire[DEVICE_COUNT-1:0] deviceBusy;
wire[DEVICE_COUNT-1:0] deviceOutputRequest;
wire[(32 * DEVICE_COUNT) - 1:0] deviceOutputData;
- Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT)) mux(
+ Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT), .DEFAULT(~32'b0)) mux(
.select(deviceOutputRequest),
.in(deviceOutputData),
.out(peripheralBus_dataRead),
diff --git a/verilog/rtl/Peripherals/UART/UART_top.v b/verilog/rtl/Peripherals/UART/UART_top.v
index ca417e6..542abe7 100644
--- a/verilog/rtl/Peripherals/UART/UART_top.v
+++ b/verilog/rtl/Peripherals/UART/UART_top.v
@@ -38,7 +38,7 @@
wire[DEVICE_COUNT-1:0] deviceBusy;
wire[DEVICE_COUNT-1:0] deviceOutputRequest;
wire[(32 * DEVICE_COUNT) - 1:0] deviceOutputData;
- Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT)) mux(
+ Mux #(.WIDTH(32), .INPUTS(DEVICE_COUNT), .DEFAULT(~32'b0)) mux(
.select(deviceOutputRequest),
.in(deviceOutputData),
.out(peripheralBus_dataRead),
diff --git a/verilog/rtl/Utility/Mux.v b/verilog/rtl/Utility/Mux.v
index 4fa8756..5e10865 100644
--- a/verilog/rtl/Utility/Mux.v
+++ b/verilog/rtl/Utility/Mux.v
@@ -1,6 +1,7 @@
module Mux #(
parameter WIDTH = 1,
- parameter INPUTS = 2
+ parameter INPUTS = 2,
+ parameter DEFAULT = 'b0
)(
input wire[INPUTS-1:0] select,
input wire[(WIDTH*INPUTS)-1:0] in,
@@ -13,7 +14,7 @@
always @(*) begin
case (1'b1)
select[0]: out <= in[WIDTH-1:0];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 2) begin
@@ -21,7 +22,7 @@
case (1'b1)
select[0]: out <= in[WIDTH-1:0];
select[1]: out <= in[(1 * WIDTH) + WIDTH - 1:1 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 3) begin
@@ -30,7 +31,7 @@
select[0]: out <= in[WIDTH-1:0];
select[1]: out <= in[(1 * WIDTH) + WIDTH - 1:1 * WIDTH];
select[2]: out <= in[(2 * WIDTH) + WIDTH - 1:2 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 4) begin
@@ -40,7 +41,7 @@
select[1]: out <= in[(1 * WIDTH) + WIDTH - 1:1 * WIDTH];
select[2]: out <= in[(2 * WIDTH) + WIDTH - 1:2 * WIDTH];
select[3]: out <= in[(3 * WIDTH) + WIDTH - 1:3 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 5) begin
@@ -51,7 +52,7 @@
select[2]: out <= in[(2 * WIDTH) + WIDTH - 1:2 * WIDTH];
select[3]: out <= in[(3 * WIDTH) + WIDTH - 1:3 * WIDTH];
select[4]: out <= in[(4 * WIDTH) + WIDTH - 1:4 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 6) begin
@@ -63,7 +64,7 @@
select[3]: out <= in[(3 * WIDTH) + WIDTH - 1:3 * WIDTH];
select[4]: out <= in[(4 * WIDTH) + WIDTH - 1:4 * WIDTH];
select[5]: out <= in[(5 * WIDTH) + WIDTH - 1:5 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 7) begin
@@ -76,7 +77,7 @@
select[4]: out <= in[(4 * WIDTH) + WIDTH - 1:4 * WIDTH];
select[5]: out <= in[(5 * WIDTH) + WIDTH - 1:5 * WIDTH];
select[6]: out <= in[(6 * WIDTH) + WIDTH - 1:6 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else if (INPUTS == 8) begin
@@ -90,7 +91,7 @@
select[5]: out <= in[(5 * WIDTH) + WIDTH - 1:5 * WIDTH];
select[6]: out <= in[(6 * WIDTH) + WIDTH - 1:6 * WIDTH];
select[7]: out <= in[(7 * WIDTH) + WIDTH - 1:7 * WIDTH];
- default: out <= {WIDTH{1'b0}};
+ default: out <= DEFAULT;
endcase
end
end else begin
