Added buffers to irq lines from GPIO and PWM peripherals.
diff --git a/verilog/rtl/Peripherals/GPIO/GPIODevice.v b/verilog/rtl/Peripherals/GPIO/GPIODevice.v
index fdfca26..948445e 100644
--- a/verilog/rtl/Peripherals/GPIO/GPIODevice.v
+++ b/verilog/rtl/Peripherals/GPIO/GPIODevice.v
@@ -20,7 +20,7 @@
input wire[IO_COUNT-1:0] gpio_input,
output wire[IO_COUNT-1:0] gpio_output,
output wire[IO_COUNT-1:0] gpio_oe,
- output wire gpio_irq
+ output reg gpio_irq
);
// Device select
@@ -93,7 +93,7 @@
// IRQ register: Default 0x0
wire[31:0] irqEnableRegisterOutputData;
- wire oirqEnableRegisterOutputRequest;
+ wire irqEnableRegisterOutputRequest;
wire[IO_COUNT-1:0] irqEnable;
OutputRegister #(.WIDTH(IO_COUNT), .ADDRESS(8'h03), .DEFAULT({IO_COUNT{1'b0}})) irqEnableRegister(
.clk(clk),
@@ -118,6 +118,10 @@
wire[IO_COUNT-1:0] pinIRQ = irqEnable & gpio_oe & gpio_input;
- assign gpio_irq = |pinIRQ;
+
+ always @(posedge clk) begin
+ if (rst) gpio_irq <= 1'b0;
+ else gpio_irq <= |pinIRQ;
+ end
endmodule
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diff --git a/verilog/rtl/Peripherals/PWM/PWMOutput.v b/verilog/rtl/Peripherals/PWM/PWMOutput.v
index c1ca2e4..d226582 100644
--- a/verilog/rtl/Peripherals/PWM/PWMOutput.v
+++ b/verilog/rtl/Peripherals/PWM/PWMOutput.v
@@ -10,8 +10,8 @@
input wire[WIDTH-1:0] counterValue,
output wire pwm_out,
- output wire compareRise,
- output wire compareFall
+ output reg compareRise,
+ output reg compareFall
);
reg [WIDTH-1:0] currentCompareValue = {WIDTH{1'b0}};
@@ -40,12 +40,23 @@
reg lastState = 1'b0;
always @(posedge clk) begin
- if (rst) lastState <= 1'b0;
- else lastState <= state;
+ if (rst) begin
+ lastState <= 1'b0;
+ compareRise <= 1'b0;
+ compareFall <= 1'b0;
+ end else begin
+ lastState <= state;
+
+ if (state != state) begin
+ compareRise <= state;
+ compareFall <= !state;
+ end else begin
+ compareRise <= 1'b0;
+ compareFall <= 1'b0;
+ end
+ end
end
- assign compareRise = (lastState != state) && state;
- assign compareFall = (lastState != state) && !state;
assign pwm_out = state;
endmodule
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