Added additional core memory tests to verify read from flash and writes to gpio.
diff --git a/README.md b/README.md
index de96f76..b4d77c3 100644
--- a/README.md
+++ b/README.md
@@ -41,6 +41,7 @@
## RTL
### verify-coreArch-rtl: Success
### verify-corePC-rtl: Success
+### verify-coreMemory-rtl: Success
### verify-flash-rtl: Success
### verify-memory-rtl: Success
### verify-peripheralsGPIO-rtl: Success
@@ -51,7 +52,8 @@
## GL
### verify-corePC-gl: Success
-### verify-flash-gl: Not run
+### verify-coreMemory-rtl: Not run
+### verify-flash-gl: Success
### verify-memory-gl: Success
### verify-peripheralsGPIO-gl: Success
### verify-peripheralsPWM-gl: Success
diff --git a/verilog/dv/.gitignore b/verilog/dv/.gitignore
index e50b205..281d833 100644
--- a/verilog/dv/.gitignore
+++ b/verilog/dv/.gitignore
@@ -12,4 +12,5 @@
coreArch/DUT-ExperiarSoC.signature
coreArch/coreArch.disass
!coreArch/coreArch.elf
+!coreMemory/test.hex
!flash/test.hex
\ No newline at end of file
diff --git a/verilog/dv/coreMemory/GenerateTestInstructions.py b/verilog/dv/coreMemory/GenerateTestInstructions.py
index fcf7cec..dda3ec2 100644
--- a/verilog/dv/coreMemory/GenerateTestInstructions.py
+++ b/verilog/dv/coreMemory/GenerateTestInstructions.py
@@ -12,9 +12,20 @@
AddTest(0x1100_0000)
AddTest(0x1200_0000)
- print("Commands:")
+ print("SRAM Commands:")
PrintInstructionData((0b0000_0000_0000 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0011 << 7) | 0b0000011)
PrintInstructionData((0b000_0000 << 25) | (0b0_0011 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0100 << 7) | 0b0100011)
+ print("Flash Commands:")
+ PrintInstructionData((0x0000_0000 & 0xFFFF_F000) | (0b0_0001 << 7) | 0b0110111)
+ PrintInstructionData((0x1400_0000 & 0xFFFF_F000) | (0b0_0010 << 7) | 0b0110111)
+ PrintInstructionData((0b0000_0000_0000 << 20) | (0b0_0010 << 15) | (0b010 << 12) | (0b0_0011 << 7) | 0b0000011)
+ PrintInstructionData((0b000_0000 << 25) | (0b0_0011 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0000 << 7) | 0b0100011)
+
+ print("Peripheral Commands:")
+ PrintInstructionData((0x1303_1004 & 0xFFFF_F000) | (0b0_0001 << 7) | 0b0110111)
+ PrintInstructionData((0x0000_4000 & 0xFFFF_F000) | (0b0_0011 << 7) | 0b0110111)
+ PrintInstructionData((0b000_0000 << 25) | (0b0_0011 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0100 << 7) | 0b0100011)
+
if __name__ == "__main__":
main()
\ No newline at end of file
diff --git a/verilog/dv/coreMemory/coreMemory.c b/verilog/dv/coreMemory/coreMemory.c
index 0b78f60..fc53f88 100644
--- a/verilog/dv/coreMemory/coreMemory.c
+++ b/verilog/dv/coreMemory/coreMemory.c
@@ -45,32 +45,20 @@
#define CORE0_REG_STEP_ADDR ((uint32_t*)0x30810008)
#define CORE0_REG_INSTR_ADDR ((uint32_t*)0x30810010)
#define CORE0_REG_IREG_ADDR ((uint32_t*)0x30811000)
-#define CORE0_SRAM_ADDR ((uint32_t*)0x30000000)
-
-#define CORE1_CONFIG_ADDR ((uint32_t*)0x31800000)
-#define CORE1_STATUS_ADDR ((uint32_t*)0x31800004)
-#define CORE1_REG_PC_ADDR ((uint32_t*)0x31810000)
-#define CORE1_REG_JUMP_ADDR ((uint32_t*)0x31810004)
-#define CORE1_REG_STEP_ADDR ((uint32_t*)0x31810008)
-#define CORE1_REG_INSTR_ADDR ((uint32_t*)0x31810010)
-#define CORE1_REG_IREG_ADDR ((uint32_t*)0x31811000)
-#define CORE1_SRAM_ADDR ((uint32_t*)0x31000000)
#define CORE0_SRAM ((uint32_t*)0x30000000)
#define CORE1_SRAM ((uint32_t*)0x31000000)
#define VGA_SRAM ((uint32_t*)0x32000000)
#define SRAM_BANK_SIZE 0x200
+#define FLASH_DATA ((uint32_t*)0x34000000)
+#define FLASH_CONFIGURATION ((uint32_t*)0x34001000)
+#define FLASH_BASE_ADDRESS ((uint32_t*)0x34001004)
+#define FLASH_CACHED_ADDRESS ((uint32_t*)0x34001008)
+
#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
#define MPRJ_WB_DATA_LOCATION 0x30008000
-#define CORE_RUN 0x1
-#define CORE_HALT 0x0
-#define CORE_RUNNING_NOERROR 0x10
-
-#define RV32I_NOP 0x00000013
-#define RV32I_JMP_PREV 0xFFDFF06F
-
void wbWrite (uint32_t* location, uint32_t value)
{
// Write the address
@@ -150,9 +138,19 @@
reg_wb_enable = 1;
// Enable GPIO
+ // Flash interface
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ // Test control signals
reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ // Peripheral test output
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1) {}
@@ -160,21 +158,58 @@
// Setup test output
bool testPass = true;
wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000);
- wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000);
+ wbWrite (GPIO0_OE_WRITE_ADDR, ~0x07000);
+ // Enable flash for later test
+ wbWrite (FLASH_CONFIGURATION, 0x1);
+ if (wbRead (FLASH_CONFIGURATION) != 0x1) testPass = false;
+
+ // Set the base address
+ // This will probably be the default value
+ wbWrite (FLASH_BASE_ADDRESS, 0x0);
+ if (wbRead (FLASH_BASE_ADDRESS) != 0x0) testPass = false;
+
+ // Setup for sram tests
wbWrite (CORE0_SRAM + 3, 0x0000a183);
wbWrite (CORE0_SRAM + 4, 0x0030a223);
+ // Test core local sram
if (!testMemory (0x30000000, 0x000000b7, 0x12345678)) testPass = false;
nextTest (testPass);
+ // Test core0 sram via wishbone bus
if (!testMemory (0x30000000, 0x100000b7, 0x9ABCDEF0)) testPass = false;
nextTest (testPass);
+ // Test core1 sram
if (!testMemory (0x31000000, 0x110000b7, 0x849A5C12)) testPass = false;
nextTest (testPass);
+ // Test video sram
if (!testMemory (0x32000000, 0x120000b7, 0xBE091D57)) testPass = false;
+ nextTest (testPass);
+
+ // Test flash
+ wbWrite (CORE0_SRAM + 2, 0x000000b7);
+ wbWrite (CORE0_SRAM + 3, 0x14000137);
+ wbWrite (CORE0_SRAM + 4, 0x00012183);
+ wbWrite (CORE0_SRAM + 5, 0x0030a023);
+ wbWrite (CORE0_REG_PC_ADDR, 0x8);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ if (wbRead ((uint32_t*)(0x30000000)) != 0x03020100) testPass = false;
+ nextTest (testPass);
+
+ // Test peripheral by performing gpio write
+ wbWrite (CORE0_SRAM + 2, 0x130310b7);
+ wbWrite (CORE0_SRAM + 3, 0x000041b7);
+ wbWrite (CORE0_SRAM + 4, 0x0030a223);
+ wbWrite (CORE0_REG_PC_ADDR, 0x8);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+ wbWrite (CORE0_REG_STEP_ADDR, 0x0);
// Finish test
nextTest (testPass);
diff --git a/verilog/dv/coreMemory/coreMemory_tb.v b/verilog/dv/coreMemory/coreMemory_tb.v
index d3abe19..d1365d6 100644
--- a/verilog/dv/coreMemory/coreMemory_tb.v
+++ b/verilog/dv/coreMemory/coreMemory_tb.v
@@ -29,6 +29,13 @@
wire succesOutput = mprj_io[12];
wire nextTestOutput = mprj_io[13];
+ wire gpioTestOutput = mprj_io[14];
+
+ wire user_flash_csb = mprj_io[8];
+ wire user_flash_clk = mprj_io[9];
+ wire user_flash_io0 = mprj_io[10];
+ wire user_flash_io1;
+ assign mprj_io[11] = user_flash_io1;
pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -40,8 +47,8 @@
// Need to add pulls (can be up or down) to all unsed io so that input data is known
assign mprj_io[2:0] = 3'b0;
- assign mprj_io[11:4] = 8'b0;
- assign mprj_io[37:14] = 24'b0;
+ assign mprj_io[7:4] = 4'b0;
+ assign mprj_io[37:15] = 23'b0;
initial begin
clock = 0;
@@ -58,7 +65,7 @@
`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (500) begin
+ repeat (600) begin
repeat (1000) @(posedge clock);
//$display("+1000 cycles");
end
@@ -77,6 +84,10 @@
@(posedge nextTestOutput);
@(posedge nextTestOutput);
@(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+ @(posedge nextTestOutput);
+
+ @(posedge gpioTestOutput);
// Wait for management core to output a output test result
@(posedge nextTestOutput);
@@ -182,5 +193,16 @@
.io3() // not used
);
+ spiflash #(
+ .FILENAME("test.hex")
+ ) testflash (
+ .csb(user_flash_csb),
+ .clk(user_flash_clk),
+ .io0(user_flash_io0),
+ .io1(user_flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
endmodule
`default_nettype wire
diff --git a/verilog/dv/coreMemory/test.hex b/verilog/dv/coreMemory/test.hex
new file mode 100644
index 0000000..c64984d
--- /dev/null
+++ b/verilog/dv/coreMemory/test.hex
@@ -0,0 +1,4 @@
+@00000000
+00 01 02 03 54 60 70 A2 A0 B1 C2 D3 E4 F5 06 17
+@0000F000
+81 2C 23 CB F6 DF F0 EF E7 A0 23 FE 88 05 05 13
