Fixed wishbone slave stall signal staying on for an extra clock cycle.

verilog/rtl/CaravelHost/WBAddressExtension.v

diff --git a/verilog/rtl/CaravelHost/WBAddressExtension.v b/verilog/rtl/CaravelHost/WBAddressExtension.v
index c5c10e3..a0eca25 100644
--- a/verilog/rtl/CaravelHost/WBAddressExtension.v
+++ b/verilog/rtl/CaravelHost/WBAddressExtension.v
@@ -88,6 +88,7 @@
 
 				STATE_FINISH: begin
 					state <= STATE_IDLE;
+					stall <= 1'b0;
 					acknowledge <= 1'b0;
 				end
 

verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v

diff --git a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
index f4f6fe1..ef96a12 100644
--- a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
+++ b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
@@ -101,6 +101,7 @@
 
 				STATE_FINISH: begin
 					state <= STATE_IDLE;
+					stall <= 1'b0;
 					acknowledge <= 1'b0;
 				end
 

verilog/rtl/Flash/WBFlashInterface.v

diff --git a/verilog/rtl/Flash/WBFlashInterface.v b/verilog/rtl/Flash/WBFlashInterface.v
index a09ec56..fb22c24 100644
--- a/verilog/rtl/Flash/WBFlashInterface.v
+++ b/verilog/rtl/Flash/WBFlashInterface.v
@@ -80,6 +80,7 @@
 
 				STATE_FINISH: begin
 					state <= STATE_IDLE;
+					stall <= 1'b0;
 					acknowledge <= 1'b0;
 				end
 

verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v

diff --git a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
index f8fcd0b..5cd9d14 100644
--- a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
+++ b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
@@ -88,6 +88,7 @@
 
 				STATE_FINISH: begin
 					state <= STATE_IDLE;
+					stall <= 1'b0;
 					acknowledge <= 1'b0;
 				end