Fixed that the previous change used the full counter value rather than the scaled counter value for comparing to the top value.

verilog/rtl/Peripherals/PWM/PWMDevice.v

diff --git a/verilog/rtl/Peripherals/PWM/PWMDevice.v b/verilog/rtl/Peripherals/PWM/PWMDevice.v
index fb7a8ca..d9a43c9 100644
--- a/verilog/rtl/Peripherals/PWM/PWMDevice.v
+++ b/verilog/rtl/Peripherals/PWM/PWMDevice.v
@@ -159,7 +159,7 @@
 				topCompare <= topCompareRegisterWriteData;
 			end else begin
 				if (counterEnable) begin
-					if (nextCounter == topCompare) baseCounter <= 'b0;
+					if (counterValue == topCompare) baseCounter <= 'b0;
 					else baseCounter <= nextCounter;
 				end else begin
 					baseCounter <= 'b0;