Fixed valid time ranges in PWM test. Also added message saying valid range if the timing test fails.
diff --git a/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v b/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
index 6c06022..b2b5b5a 100644
--- a/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
+++ b/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
@@ -120,13 +120,15 @@
@(posedge pwmOutputs[0]);
timerLength = $realtime - timerStart;
$display("Device 0 Output 2 Low Time: ", timerLength);
- if (timerLength < 499800000 || timerLength > 500200000) timingValid = 1'b0;
+ if (timerLength < 499800 || timerLength > 500200) timingValid = 1'b0;
+ else $display("Invalid time, should be between 499800 and 500200");
// Measure device 0 ouput value 2 period
@(negedge pwmOutputs[0]);
timerLength = $realtime - timerStart;
$display("Device 0 Output 2 Period: ", timerLength);
- if (timerLength < 999800000 || timerLength > 1000200000) timingValid = 1'b0;
+ if (timerLength < 999800 || timerLength > 1000200) timingValid = 1'b0;
+ else $display("Invalid time, should be between 999800 and 1000200");
@(posedge nextTestOutput);
//----------------Device 0 ouput value 3----------------//
@@ -139,13 +141,15 @@
@(posedge pwmOutputs[1]);
timerLength = $realtime - timerStart;
$display("Device 0 Output 3 Low Time: ", timerLength);
- if (timerLength < 699800000 || timerLength > 700200000) timingValid = 1'b0;
+ if (timerLength < 699800 || timerLength > 700200) timingValid = 1'b0;
+ else $display("Invalid time, should be between 699800 and 700200");
// Measure device 0 ouput value 3 period
@(negedge pwmOutputs[1]);
timerLength = $realtime - timerStart;
$display("Device 0 Output 3 Period: ", timerLength);
- if (timerLength < 999800000 || timerLength > 1000200000) timingValid = 1'b0;
+ if (timerLength < 999800 || timerLength > 1000200) timingValid = 1'b0;
+ else $display("Invalid time, should be between 999800 and 1000200");
@(posedge nextTestOutput);
//----------------Device 1 ouput value 0----------------//
@@ -158,13 +162,15 @@
@(posedge pwmOutputs[2]);
timerLength = $realtime - timerStart;
$display("Device 1 Output 0 Low Time: ", timerLength);
- if (timerLength < 799900000 || timerLength > 800100000) timingValid = 1'b0;
+ if (timerLength < 199900 || timerLength > 200100) timingValid = 1'b0;
+ else $display("Invalid time, should be between 199900 and 200100");
// Measure device 1 ouput value 0 period
@(negedge pwmOutputs[2]);
timerLength = $realtime - timerStart;
$display("Device 1 Output 0 Period: ", timerLength);
- if (timerLength < 999900000 || timerLength > 1000100000) timingValid = 1'b0;
+ if (timerLength < 999900 || timerLength > 1000100) timingValid = 1'b0;
+ else $display("Invalid time, should be between 999900 and 1000100");
// Wait for management core to output the final output test result
@(posedge nextTestOutput);
diff --git a/verilog/dv/video/video_tb.v b/verilog/dv/video/video_tb.v
index e8029d5..aa1c6f2 100644
--- a/verilog/dv/video/video_tb.v
+++ b/verilog/dv/video/video_tb.v
@@ -106,12 +106,14 @@
timerLength = $realtime - timerStart;
$display("H Sync pulse period: %t", timerLength);
if (timerLength < 390 || timerLength > 410) timingValid = 1'b0;
+ else $display("Invalid time, should be between 390 and 410");
// Measure hsync period
@(negedge vgaHSync);
timerLength = $realtime - timerStart;
$display("H Sync period: %t", timerLength);
if (timerLength < 3290 || timerLength > 3310) timingValid = 1'b0;
+ else $display("Invalid time, should be between 3290 and 3310");
@(negedge vgaVSync);
timerStart = $realtime;
@@ -121,12 +123,14 @@
timerLength = $realtime - timerStart;
$display("V Sync pulse period: %t", timerLength);
if (timerLength < 13190 || timerLength > 13210) timingValid = 1'b0;
+ else $display("Invalid time, should be between 13190 and 13210");
// Measure vsync period
@(negedge vgaVSync);
timerLength = $realtime - timerStart;
$display("V Sync period: %t", timerLength);
if (timerLength < 2072390 || timerLength > 2072410) timingValid = 1'b0;
+ else $display("Invalid time, should be between 2072390 and 2072410");
// Test tight memory mode
@(posedge nextTestOutput);
@@ -139,12 +143,14 @@
timerLength = $realtime - timerStart;
$display("H Sync pulse period: %t", timerLength);
if (timerLength < 390 || timerLength > 410) timingValid = 1'b0;
+ else $display("Invalid time, should be between 390 and 410");
// Measure hsync period
@(negedge vgaHSync);
timerLength = $realtime - timerStart;
$display("H Sync period: %t", timerLength);
if (timerLength < 3290 || timerLength > 3310) timingValid = 1'b0;
+ else $display("Invalid time, should be between 3290 and 3310");
@(negedge vgaVSync);
timerStart = $realtime;
@@ -154,12 +160,14 @@
timerLength = $realtime - timerStart;
$display("V Sync pulse period: %t", timerLength);
if (timerLength < 13190 || timerLength > 13210) timingValid = 1'b0;
+ else $display("Invalid time, should be between 13190 and 13210");
// Measure vsync period
@(negedge vgaVSync);
timerLength = $realtime - timerStart;
$display("V Sync period: %t", timerLength);
if (timerLength < 2072390 || timerLength > 2072410) timingValid = 1'b0;
+ else $display("Invalid time, should be between 2072390 and 2072410");
// Wait for test to finish
@(posedge nextTestOutput);
