Fixed UART test not checking for the correct status bit. Also added some extra checks to make sure data leaves the FIFO buffers correctly.

verilog/dv/peripheralsUART/peripheralsUART.c

diff --git a/verilog/dv/peripheralsUART/peripheralsUART.c b/verilog/dv/peripheralsUART/peripheralsUART.c
index c96a07a..d4f1c00 100644
--- a/verilog/dv/peripheralsUART/peripheralsUART.c
+++ b/verilog/dv/peripheralsUART/peripheralsUART.c
@@ -153,7 +153,7 @@
 	wbWrite (CARAVEL_UART_TX__ADDR, testData[0]);
 
 	// Check that the data is there
-	if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0) testPass = false;
+	if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0x8) testPass = false;
 	nextTest (testPass);
 
 	// Check that no data has arrived at the SoC UART device
@@ -167,6 +167,10 @@
 	wbWrite (CARAVEL_UART_TX__ADDR, testData[2]);
 	wbWrite (CARAVEL_UART_TX__ADDR, testData[3]);
 
+	// Make sure all of the data has been sent
+	if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0) testPass = false;
+	nextTest (testPass);
+
 	// Read back data from peripheral
 	if (wbRead (SOC_UART0_RX_ADDR) != testData[0]) testPass = false;
 	if (wbRead (SOC_UART0_RX_ADDR) != testData[1]) testPass = false;
@@ -174,17 +178,29 @@
 	if (wbRead (SOC_UART0_RX_ADDR) != testData[3]) testPass = false;
 	nextTest (testPass);
 
+	// Make sure all of the data is marked as read
+	if (wbRead (SOC_UART0_STATUS_ADDR) != 0) testPass = false;
+	nextTest (testPass);
+
 	// Send data from peripheral
 	wbWrite (SOC_UART0_TX__ADDR, testData[0]);
 	wbWrite (SOC_UART0_TX__ADDR, testData[1]);
 	wbWrite (SOC_UART0_TX__ADDR, testData[2]);
 	wbWrite (SOC_UART0_TX__ADDR, testData[3]);
 
+	// Make sure all of the data has been sent
+	if (wbRead (SOC_UART0_STATUS_ADDR) != 0) testPass = false;
+	nextTest (testPass);
+
 	// Read back data from caravel
 	if (wbRead (CARAVEL_UART_RX_ADDR) != testData[0]) testPass = false;
 	if (wbRead (CARAVEL_UART_RX_ADDR) != testData[1]) testPass = false;
 	if (wbRead (CARAVEL_UART_RX_ADDR) != testData[2]) testPass = false;
 	if (wbRead (CARAVEL_UART_RX_ADDR) != testData[3]) testPass = false;
+	nextTest (testPass);
+
+	// Make sure all of the data is marked as read
+	if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0) testPass = false;
 
 	// Finish test
 	nextTest (testPass);

verilog/dv/peripheralsUART/peripheralsUART_tb.v

diff --git a/verilog/dv/peripheralsUART/peripheralsUART_tb.v b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
index 0d5d2e9..738b21e 100644
--- a/verilog/dv/peripheralsUART/peripheralsUART_tb.v
+++ b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
@@ -65,6 +65,13 @@
 		@(posedge nextTestOutput);
 		@(posedge nextTestOutput);
 		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
 
 		// Wait for management core to output a output test result
 		@(posedge nextTestOutput);