Test Updated
diff --git a/verilog/dv/asm/fadd_fsub.s b/verilog/dv/asm/fadd_fsub.s
new file mode 100644
index 0000000..1305af3
--- /dev/null
+++ b/verilog/dv/asm/fadd_fsub.s
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x44545333
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fadd.s f16, f1, f0
+ fadd.s f17, f3, f2
+ fadd.s f18, f5, f4
+ fadd.s f19, f7, f6
+ fadd.s f20, f9, f8
+ fadd.s f21, f11, f10
+ fadd.s f22, f13, f12
+ fadd.s f23, f15, f14
+ fsub.s f24, f0, f1
+ fsub.s f25, f1, f0
+ fsub.s f26, f3, f2
+ fsub.s f27, f5, f4
+ fsub.s f28, f7, f6
+ fsub.s f29, f9, f8
+ fsub.s f30, f11, f10
+ fsub.s f31, f13, f12
+
+
+
diff --git a/verilog/dv/asm/fclass_f2i.s b/verilog/dv/asm/fclass_f2i.s
new file mode 100644
index 0000000..f88b026
--- /dev/null
+++ b/verilog/dv/asm/fclass_f2i.s
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x44545333
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fcvt.w.s x1, f1
+ fcvt.wu.s x2, f2
+ fcvt.w.s x3, f3
+ fcvt.wu.s x4, f4
+ fcvt.w.s x5, f5
+ fcvt.wu.s x6, f6
+ fcvt.w.s x7, f7
+ fcvt.wu.s x8, f8
+ fclass.s x9, f9
+ fclass.s x10, f10
+ fclass.s x11, f11
+ fclass.s x12, f12
+ fclass.s x13, f13
+ fclass.s x14, f14
+ fclass.s x15, f15
+
+
+
diff --git a/verilog/dv/asm/fmadd_fmsub.s b/verilog/dv/asm/fmadd_fmsub.s
new file mode 100644
index 0000000..d9fefbe
--- /dev/null
+++ b/verilog/dv/asm/fmadd_fmsub.s
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x445453
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fmadd.s f16, f1, f0, f1
+ fmadd.s f17, f3, f2, f3
+ fmadd.s f18, f5, f4, f5
+ fmadd.s f19, f7, f6, f7
+ fmadd.s f20, f9, f8, f9
+ fmadd.s f21, f11, f10, f11
+ fmadd.s f22, f13, f12, f13
+ fmadd.s f23, f15, f14, f15
+ fmsub.s f16, f1, f0, f0
+ fmsub.s f17, f3, f2, f2
+ fmsub.s f18, f5, f4, f4
+ fmsub.s f19, f7, f6, f6
+ fmsub.s f20, f9, f8, f8
+ fmsub.s f21, f11, f10, f11
+ fmsub.s f22, f13, f12, f12
+ fmsub.s f23, f15, f14, f14
+
+
diff --git a/verilog/dv/asm/fmin_fmax_compare.s b/verilog/dv/asm/fmin_fmax_compare.s
new file mode 100644
index 0000000..696a503
--- /dev/null
+++ b/verilog/dv/asm/fmin_fmax_compare.s
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x445453
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ flt.s x1, f1, f0
+ flt.s x2, f3, f2
+ flt.s x3, f5, f4
+ flt.s x4, f7, f6
+ fle.s x5, f9, f8
+ fle.s x6, f11, f10
+ fle.s x7, f13, f12
+ fle.s x8, f15, f14
+ fmin.s f16, f1, f0
+ fmin.s f17, f3, f2
+ fmin.s f18, f5, f4
+ fmin.s f19, f7, f6
+ fmax.s f20, f9, f8
+ fmax.s f21, f11, f10
+ fmax.s f22, f13, f12
+ fmax.s f23, f15, f14
+
+
diff --git a/verilog/dv/asm/fmul.s b/verilog/dv/asm/fmul.s
new file mode 100644
index 0000000..dda0946
--- /dev/null
+++ b/verilog/dv/asm/fmul.s
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x445453
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fmul.s f16, f1, f0
+ fmul.s f17, f3, f2
+ fmul.s f18, f5, f4
+ fmul.s f19, f7, f6
+ fmul.s f20, f9, f8
+ fmul.s f21, f11, f10
+ fmul.s f22, f13, f12
+ fmul.s f23, f15, f14
+
+
diff --git a/verilog/dv/asm/fmv.s b/verilog/dv/asm/fmv.s
new file mode 100644
index 0000000..353c9e3
--- /dev/null
+++ b/verilog/dv/asm/fmv.s
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x44545333
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
diff --git a/verilog/dv/asm/fnmadd_fnmsub.s b/verilog/dv/asm/fnmadd_fnmsub.s
new file mode 100644
index 0000000..f7f9062
--- /dev/null
+++ b/verilog/dv/asm/fnmadd_fnmsub.s
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x445453
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fnmadd.s f16, f1, f0, f1
+ fnmadd.s f17, f3, f2, f3
+ fnmadd.s f18, f5, f4, f5
+ fnmadd.s f19, f7, f6, f7
+ fnmadd.s f20, f9, f8, f9
+ fnmadd.s f21, f11, f10, f11
+ fnmadd.s f22, f13, f12, f13
+ fnmadd.s f23, f15, f14, f15
+ fnmsub.s f16, f1, f0, f0
+ fnmsub.s f17, f3, f2, f2
+ fnmsub.s f18, f5, f4, f4
+ fnmsub.s f19, f7, f6, f6
+ fnmsub.s f20, f9, f8, f8
+ fnmsub.s f21, f11, f10, f11
+ fnmsub.s f22, f13, f12, f12
+ fnmsub.s f23, f15, f14, f14
+
+
diff --git a/verilog/dv/asm/sign_i2f.s b/verilog/dv/asm/sign_i2f.s
new file mode 100644
index 0000000..f5472a3
--- /dev/null
+++ b/verilog/dv/asm/sign_i2f.s
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ li x5, 0x40B60EBF
+ fmv.w.x f0, x5
+ li x5, 0x4208ED91
+ fmv.w.x f1, x5
+ li x5, 0x3FF78D50
+ fmv.w.x f2, x5
+ li x5, 0xC0ADD2F2
+ fmv.w.x f3, x5
+ li x5, 0xC6B97C00
+ fmv.w.x f4, x5
+ li x5, 0x463C087B
+ fmv.w.x f5, x5
+ li x5, 0x4158F5C3
+ fmv.w.x f6, x5
+ li x5, 0xC3F7999A
+ fmv.w.x f7, x5
+ li x5, 0xC236B021
+ fmv.w.x f8, x5
+ li x5, 0x4147EB85
+ fmv.w.x f9, x5
+ li x5, 0x44545333
+ fmv.w.x f10, x5
+ li x5, 0xC2095C29
+ fmv.w.x f11, x5
+ li x5, 0x3EB33333
+ fmv.w.x f12, x5
+ li x5, 0xBB195AAF
+ fmv.w.x f13, x5
+ li x5, 0x380FDD58
+ fmv.w.x f14, x5
+ li x5, 0xBCA75DB8
+ fmv.w.x f15, x5
+ fsgnj.s f16, f1, f0
+ fsgnj.s f17, f3, f2
+ fsgnj.s f18, f5, f4
+ fsgnjn.s f19, f7, f6
+ fsgnjn.s f20, f9, f8
+ fsgnjn.s f21, f11, f10
+ fsgnjx.s f22, f13, f12
+ fsgnjx.s f23, f15, f14
+ fsgnjx.s f24, f0, f1
+ li x1, 0x40B60EBF
+ li x2, 0x4208ED91
+ li x3, 0x3EB33333
+ li x4, 0xBCA75DB8
+ li x5, 0xC2095C29
+ li x6, 0xC3F7999A
+ li x7, 0xC6B97C00
+ fcvt.s.w f25, x1
+ fcvt.s.wu f26, x2
+ fcvt.s.w f27, x3
+ fcvt.s.wu f28, x4
+ fcvt.s.w f29, x5
+ fcvt.s.wu f30, x6
+ fcvt.s.w f31, x7
+
diff --git a/verilog/dv/hex/Add_Sub.hex b/verilog/dv/hex/Add_Sub.hex
new file mode 100644
index 0000000..819378a
--- /dev/null
+++ b/verilog/dv/hex/Add_Sub.hex
@@ -0,0 +1,18 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 44 54 52 B7 33 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+00 00 F8 53 00 21 F8 D3 00 42 F9 53 00 63 F9 D3
+00 84 FA 53 00 A5 FA D3 00 C6 FB 53 00 E7 FB D3
+08 10 7C 53 08 00 FC D3 08 21 FD 53 08 42 FD D3
+08 63 FE 53 08 84 FE D3 08 A5 FF 53 08 C6 FF D3
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/FMADD_FMSUB.hex b/verilog/dv/hex/FMADD_FMSUB.hex
new file mode 100644
index 0000000..90cd4a1
--- /dev/null
+++ b/verilog/dv/hex/FMADD_FMSUB.hex
@@ -0,0 +1,18 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 00 44 52 B7 45 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+08 00 F8 43 18 21 F8 C3 28 42 F9 43 38 63 F9 C3
+48 84 FA 43 58 A5 FA C3 68 C6 FB 43 78 E7 FB C3
+00 00 F8 47 10 21 F8 C7 20 42 F9 47 30 63 F9 C7
+40 84 FA 47 58 A5 FA C7 60 C6 FB 47 70 E7 FB C7
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/FMUL.hex b/verilog/dv/hex/FMUL.hex
new file mode 100644
index 0000000..8427254
--- /dev/null
+++ b/verilog/dv/hex/FMUL.hex
@@ -0,0 +1,16 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 00 44 52 B7 45 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+10 00 F8 53 10 21 F8 D3 10 42 F9 53 10 63 F9 D3
+10 84 FA 53 10 A5 FA D3 10 C6 FB 53 10 E7 FB D3
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/FNMADD_FNMSUB.hex b/verilog/dv/hex/FNMADD_FNMSUB.hex
new file mode 100644
index 0000000..f77a3d3
--- /dev/null
+++ b/verilog/dv/hex/FNMADD_FNMSUB.hex
@@ -0,0 +1,18 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 00 44 52 B7 45 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+08 00 F8 4F 18 21 F8 CF 28 42 F9 4F 38 63 F9 CF
+48 84 FA 4F 58 A5 FA CF 68 C6 FB 4F 78 E7 FB CF
+00 00 F8 4B 10 21 F8 CB 20 42 F9 4B 30 63 F9 CB
+40 84 FA 4B 58 A5 FA CB 60 C6 FB 4B 70 E7 FB CB
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/Fclass_Float_to_Int.hex b/verilog/dv/hex/Fclass_Float_to_Int.hex
new file mode 100644
index 0000000..6b599ce
--- /dev/null
+++ b/verilog/dv/hex/Fclass_Float_to_Int.hex
@@ -0,0 +1,18 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 44 54 52 B7 33 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+C0 00 F0 D3 C0 11 71 53 C0 01 F1 D3 C0 12 72 53
+C0 02 F2 D3 C0 13 73 53 C0 03 F3 D3 C0 14 74 53
+E0 04 94 D3 E0 05 15 53 E0 05 95 D3 E0 06 16 53
+E0 06 96 D3 E0 07 17 53 E0 07 97 D3 00 00 00 10
+00 00 0F FF
diff --git a/verilog/dv/hex/I2F_Conversion_Sign.hex b/verilog/dv/hex/I2F_Conversion_Sign.hex
new file mode 100644
index 0000000..cf83384
--- /dev/null
+++ b/verilog/dv/hex/I2F_Conversion_Sign.hex
@@ -0,0 +1,21 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 44 54 52 B7 33 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+20 00 88 53 20 21 88 D3 20 42 89 53 20 63 99 D3
+20 84 9A 53 20 A5 9A D3 20 C6 AB 53 20 E7 AB D3
+20 10 2C 53 40 B6 10 B7 EB F0 80 93 42 08 F1 37
+D9 11 01 13 3E B3 31 B7 33 31 81 93 BC A7 62 37
+DB 82 02 13 C2 09 62 B7 C2 92 82 93 C3 F7 A3 37
+99 A3 03 13 C6 B9 83 B7 C0 03 83 93 D0 00 FC D3
+D0 11 7D 53 D0 01 FD D3 D0 12 7E 53 D0 02 FE D3
+D0 13 7F 53 D0 03 FF D3 00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/Min_Max_Comparison.hex b/verilog/dv/hex/Min_Max_Comparison.hex
new file mode 100644
index 0000000..53b1844
--- /dev/null
+++ b/verilog/dv/hex/Min_Max_Comparison.hex
@@ -0,0 +1,18 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 00 44 52 B7 45 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+A0 00 90 D3 A0 21 91 53 A0 42 91 D3 A0 63 92 53
+A0 84 82 D3 A0 A5 83 53 A0 C6 83 D3 A0 E7 84 53
+28 00 88 53 28 21 88 D3 28 42 89 53 28 63 89 D3
+28 84 9A 53 28 A5 9A D3 28 C6 9B 53 28 E7 9B D3
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/Move.hex b/verilog/dv/hex/Move.hex
new file mode 100644
index 0000000..1ebfdd0
--- /dev/null
+++ b/verilog/dv/hex/Move.hex
@@ -0,0 +1,14 @@
+@00000000
+40 B6 12 B7 EB F2 82 93 F0 02 80 53 42 08 F2 B7
+D9 12 82 93 F0 02 80 D3 3F F7 92 B7 D5 02 82 93
+F0 02 81 53 C0 AD D2 B7 2F 22 82 93 F0 02 81 D3
+C6 B9 82 B7 C0 02 82 93 F0 02 82 53 46 3C 12 B7
+87 B2 82 93 F0 02 82 D3 41 58 F2 B7 5C 32 82 93
+F0 02 83 53 C3 F7 A2 B7 99 A2 82 93 F0 02 83 D3
+C2 36 B2 B7 02 12 82 93 F0 02 84 53 41 47 F2 B7
+B8 52 82 93 F0 02 84 D3 44 54 52 B7 33 32 82 93
+F0 02 85 53 C2 09 62 B7 C2 92 82 93 F0 02 85 D3
+3E B3 32 B7 33 32 82 93 F0 02 86 53 BB 19 62 B7
+AA F2 82 93 F0 02 86 D3 38 0F E2 B7 D5 82 82 93
+F0 02 87 53 BC A7 62 B7 DB 82 82 93 F0 02 87 D3
+00 00 00 10 00 00 0F FF
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
new file mode 100755
index 0000000..1eb3375
--- /dev/null
+++ b/verilog/dv/hex/uart.hex
@@ -0,0 +1,21 @@
+@00000000
+00 00 42 B7 49 A2 82 93 F4 02 80 D3 00 00 62 B7
+82 32 82 93 F4 02 81 53 00 00 32 B7 04 22 82 93
+F4 02 81 D3 00 00 42 B7 C5 F2 82 93 F4 02 82 53
+00 00 52 B7 91 E2 82 93 F4 02 82 D3 00 00 62 B7
+A4 02 82 93 F4 02 83 53 00 00 62 B7 A9 22 82 93
+F4 02 83 D3 00 00 62 B7 9E E2 82 93 F4 02 84 53
+00 00 E2 B7 CB 02 82 93 F4 02 84 D3 00 00 E2 B7
+C8 72 82 93 F4 02 85 53 00 00 E2 B7 CD 92 82 93
+F4 02 85 D3 00 00 B2 B7 03 E2 82 93 F4 02 86 53
+00 00 E2 B7 F0 92 82 93 F4 02 86 D3 00 00 C2 B7
+CF 02 82 93 F4 02 87 53 00 00 C2 B7 D7 82 82 93
+F4 02 87 D3 00 00 C2 B7 C6 82 82 93 F4 02 88 53
+24 20 88 D3 24 41 89 53 24 62 89 D3 24 83 9A 53
+24 A4 9A D3 24 C5 9B 53 24 E6 AB D3 24 07 AC 53
+24 20 AC D3 00 00 41 B7 49 A1 81 93 00 00 E2 37
+CB 02 02 13 00 00 62 B7 82 32 82 93 00 00 E3 37
+C8 73 03 13 00 00 33 B7 04 23 83 93 00 00 E4 37
+CD 94 04 13 D4 01 FD 53 D4 02 7D D3 D4 02 FE 53
+D4 13 7E D3 D4 13 FF 53 D4 14 7F D3 00 00 00 10
+00 00 0F FF
