commit 448da49fab590e594e52755b747b87a525bc597c
author hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 18:27:48 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 18:27:48 2022 +0500
tree 7edfd952aebfd03960a9461a0ba0e9c0c8743df0
parent 16e3e504c1642d2dc6d98c52d2e01bc61043bdd0

FSM_TOP port declaration updated

verilog/rtl/FPU/FPU_FSM_TOP.v

diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 0fc1ac3..e03e0c6 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -49,22 +49,23 @@
 `include "LZD_comb.v"
 */
 
-module FPU_FSM_TOP(vccd1,vssd1,r_Rx_Serial,clk,rst_l,FPU_sp_result);
+module FPU_FSM_TOP(
 
 `ifdef USE_POWER_PINS
-    inout vccd1;	// User area 1 1.8V supply
-    inout vssd1;	// User area 1 digital ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
 `endif
     // FPU UART
-    input r_Rx_Serial;
+    input r_Rx_Serial,
     // FPU UART
 
     // FPU FSM 
-    input clk,rst_l;
+    input clk,
+    input rst_l,
     
-    output [31:0] FPU_sp_result;
+    output [31:0] FPU_sp_result
     // FPU FSM 
-
+);
     wire o_Rx_DV;
     wire [7:0]o_Rx_Byte;
     wire Active_Process;