CLK per bit mapping added
diff --git a/verilog/dv/FPU_Single/FPU_Single.c b/verilog/dv/FPU_Single/FPU_Single.c
index ee87546..850fe86 100644
--- a/verilog/dv/FPU_Single/FPU_Single.c
+++ b/verilog/dv/FPU_Single/FPU_Single.c
@@ -65,8 +65,10 @@
// Configure LA probes as inputs to the cpu put zero
// Configure LA probes as outputs from the cpu put one
+ reg_la0_oenb = reg_la0_iena = 0xFFFF0000; // configuring [31:16] as input
reg_la1_oenb = reg_la1_iena = 0x00000000; // configuring [63:32] as output
reg_la2_oenb = reg_la2_iena = 0x00000002; // 65 bit as input to user proj and output from cpu for reset
+ reg_la0_data = 0x015C0000; // CLk per Bits
reg_la2_data = 0x00000000; // reset
reg_la2_data = 0x00000002;
reg_la2_oenb = reg_la2_iena = 0x00000000; // 64 anf 65 bit as input to user proj and output from cpu
diff --git a/verilog/dv/FPU_Single/FPU_Single_tb.v b/verilog/dv/FPU_Single/FPU_Single_tb.v
index aabca98..e7176c3 100644
--- a/verilog/dv/FPU_Single/FPU_Single_tb.v
+++ b/verilog/dv/FPU_Single/FPU_Single_tb.v
@@ -107,7 +107,7 @@
wait(mprj_io_0 == 32'h380FDD58);
*/
// Observe Output pins for F2I and fclass
-
+ /*
wait(mprj_io_0 == 32'h00000022);
wait(mprj_io_0 == 32'h00000002);
wait(mprj_io_0 == 32'hFFFFFFFB);
@@ -122,7 +122,18 @@
wait(mprj_io_0 == 32'h00000002);
wait(mprj_io_0 == 32'h00000040);
wait(mprj_io_0 == 32'h00000002);
-
+ */
+ // Observe Output pins for Fmul
+
+ wait(mprj_io_0 == 32'h4342C190);
+ wait(mprj_io_0 == 32'hC128167B);
+ wait(mprj_io_0 == 32'hCD883D35);
+ wait(mprj_io_0 == 32'hC5D1D74D);
+ wait(mprj_io_0 == 32'hC40EAAFC);
+ wait(mprj_io_0 == 32'h8292A6E7);
+ wait(mprj_io_0 == 32'hBA56B228);
+ wait(mprj_io_0 == 32'hB53C1C1E);
+
$display("MPRJ-IO state = %h", mprj_io_0[31:0]);
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index e03e0c6..92fc3f8 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -62,6 +62,7 @@
// FPU FSM
input clk,
input rst_l,
+ input [15:0] CLKS_PER_BIT,
output [31:0] FPU_sp_result
// FPU FSM
@@ -148,7 +149,7 @@
.i_Clock(clk),
.rst_ni(rst_l),
.i_Rx_Serial(r_Rx_Serial),
- .CLKS_PER_BIT(16'd348),
+ .CLKS_PER_BIT(CLKS_PER_BIT),
.o_Rx_DV(o_Rx_DV),
.o_Rx_Byte(o_Rx_Byte)
);
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 8442ee0..4e5125e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -74,6 +74,7 @@
wire rst;
wire rx_i;
wire [31:0] FPU_sp_result;
+ wire [15:0] CLKS_PER_BIT;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
@@ -101,7 +102,7 @@
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
-
+ assign CLKS_PER_BIT = (la_oenb[31:16] == 16'h0000) ? la_data_in[31:16] : 16'd348;
// Initiation of TOP Module
FPU_FSM_TOP FPU_Single_Precision_Top (
@@ -112,7 +113,8 @@
.clk(clk),
.rst_l(rst),
.r_Rx_Serial(rx_i),
- .FPU_sp_result(FPU_sp_result)
+ .FPU_sp_result(FPU_sp_result),
+ .CLKS_PER_BIT(CLKS_PER_BIT)
);
endmodule
