Small error resolved
diff --git a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v index 5d78cd6..9b83be6 100644 --- a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v +++ b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
@@ -11,7 +11,7 @@ //declaration of putptu ports input [man+man+3:0] Post_Normalization_input_Mantissa; -input [exp:0] Post_Normalization_input_exponent; +input [exp+1:0] Post_Normalization_input_exponent; input Post_Normalization_input_Carry,Post_Normalization_input_Eff_sub,Post_Normalization_input_Eff_add,Post_Normalization_input_Guard,Post_Normalization_input_Round,Post_Normalization_input_Sticky; //declaration of putptu ports @@ -20,18 +20,19 @@ output Post_Normalization_output_Guard,Post_Normalization_output_Round,Post_Normalization_output_Sticky; //declaration of interim wires -wire [exp:0] Post_Normaliaation_Bit_Shamt_interim; -wire [exp:0] Post_Normaliaation_Bit_Shamt_1; +wire [exp+1:0] Post_Normaliaation_Bit_Shamt_interim; +wire [exp+1:0] Post_Normaliaation_Bit_Shamt_1; wire [23:0] Post_Normaliaation_Bit_input_LZD; wire [lzd:0] Post_Normaliaation_Bit_output_LZD; wire Post_Normaliaation_Bit_exp_LZD_Comp; -wire [exp:0] Post_Normaliaation_Bit_Shift_Amount; +wire [exp+1:0] Post_Normaliaation_Bit_Shift_Amount; wire [man+man+3:0] Post_Normalization_Shifter_Output_Sub,Post_Normalization_Shifter_Output_add,Post_Normalization_Shifter_input_add; wire [man+man+3:0] Post_Normalization_Mantissa_interim_48; -wire [exp:0] Post_Normaliaation_EFF_Sub_interim_Exponent; +wire [exp+1:0] Post_Normaliaation_EFF_Sub_interim_Exponent; wire [exp+1:0] Post_Normaliaation_EFF_add_interim_Exponent; - +//Calculation of number of Zero concatinations in LZD's output +localparam [2:0] Post_Normalization_wire_Concatination_Amount = (man == 32'd22) ? 3'd4 : (exp == 32'd4) ? 3'd2 : (man == 32'd6 ) ? 3'd5 : 3'd0 ; //instantition of LZD FMADD_PN_LZD Lzd_PN_AD ( @@ -45,16 +46,16 @@ //subtraction lane assign Post_Normaliaation_Bit_Shamt_interim = Post_Normalization_input_exponent - 1'b1; -assign Post_Normaliaation_Bit_Shamt_1 = (Post_Normalization_input_Eff_sub) ? Post_Normaliaation_Bit_Shamt_interim : 8'h00; +assign Post_Normaliaation_Bit_Shamt_1 = (Post_Normalization_input_Eff_sub) ? Post_Normaliaation_Bit_Shamt_interim : {exp+2{1'b0}}; assign Post_Normaliaation_Bit_input_LZD = (Post_Normalization_input_Eff_sub) ? { { 24-(man+2){1'b0} },Post_Normalization_input_Mantissa[man+man+3:man+2]} : {man+2{1'b0}}; assign Post_Normaliaation_Bit_exp_LZD_Comp = Post_Normalization_input_exponent > Post_Normaliaation_Bit_output_LZD; -assign Post_Normaliaation_Bit_Shift_Amount = (Post_Normaliaation_Bit_exp_LZD_Comp) ? { {exp-4 {1'b0}},Post_Normaliaation_Bit_output_LZD} : Post_Normaliaation_Bit_Shamt_1 ; +assign Post_Normaliaation_Bit_Shift_Amount = (Post_Normaliaation_Bit_exp_LZD_Comp) ? {{Post_Normalization_wire_Concatination_Amount{1'b0}},Post_Normaliaation_Bit_output_LZD} : Post_Normaliaation_Bit_Shamt_1 ; assign Post_Normalization_Shifter_Output_Sub = Post_Normalization_input_Mantissa << Post_Normaliaation_Bit_Shift_Amount; assign Post_Normaliaation_EFF_Sub_interim_Exponent = Post_Normalization_input_exponent - Post_Normaliaation_Bit_Shift_Amount ; //additio lanse -assign Post_Normaliaation_EFF_add_interim_Exponent = {1'b0,Post_Normalization_input_exponent} + Post_Normalization_input_Carry ; +assign Post_Normaliaation_EFF_add_interim_Exponent = Post_Normalization_input_exponent + Post_Normalization_input_Carry ; assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : 48'h000000000000; assign Post_Normalization_Shifter_Output_add = (Post_Normalization_input_Carry) ? { Post_Normalization_input_Carry,Post_Normalization_Shifter_input_add[man+man+3:1] } : Post_Normalization_Shifter_input_add[man+man+3:0] ;
diff --git a/verilog/rtl/FPU/FMADD_Exponent_Matching.v b/verilog/rtl/FPU/FMADD_Exponent_Matching.v index 57fe640..a6c9b82 100644 --- a/verilog/rtl/FPU/FMADD_Exponent_Matching.v +++ b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
@@ -1,6 +1,6 @@ //module is responsible for matching the exponents for addition -module FMADD_Exponent_Matching (Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B,Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B,Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B,Exponent_Matching_input_opcode,Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B,Exponent_Matching_output_Exp,Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Sign,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add,Exponent_Matching_output_Exp_Diff_Check); +module FMADD_Exponent_Matching (Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B,Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B,Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B,Exponent_Matching_input_opcode,Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B,Exponent_Matching_output_Exp,Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Sign,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add,Exponent_Matching_output_Exp_Diff_Check,Exponent_Matching_output_A_gt_B); //defination of prameters parameter std =31; @@ -9,7 +9,7 @@ //declaration of inptu port input Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B; -input [exp:0] Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B; +input [exp+1:0] Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B; input [man+man+3:0] Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B; // opcode[0] = Fadd @@ -19,16 +19,17 @@ //declaration of putptu ports output Exponent_Matching_output_Sign , Exponent_Matching_output_Exp_Diff_Check; output [man+man+3:0] Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B; -output [exp:0] Exponent_Matching_output_Exp; +output [exp+1:0] Exponent_Matching_output_Exp; output Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add; +output Exponent_Matching_output_A_gt_B; //main funtionality //declaration for wires wire Exponent_Matching_Bit_Exp_A_ge_B,Exponent_Matching_Bit_Exp_A_gt_B,Exponent_Matching_Bit_Exp_A_eq_B,Exponent_Matching_Bit_Man_a_ge_Man_B,Exponent_Matching_Bit_Eff_sub,Exponent_Matching_Bit_Eff_add; wire [4*man+7:0] Exponent_Matching_Shifter_input,Exponent_Matching_Shifter_output; -wire [exp:0] Exponent_Matching_Exp_Sub_input_1 , Exponent_Matching_Exp_Sub_input_2; -wire [exp:0] Exponent_Matching_Shif_Amount; +wire [exp+1:0] Exponent_Matching_Exp_Sub_input_1 , Exponent_Matching_Exp_Sub_input_2; +wire [exp+1:0] Exponent_Matching_Shif_Amount; //check for exp_A >= exp_B assign Exponent_Matching_Bit_Exp_A_gt_B = Exponent_Matching_input_Exp_A > Exponent_Matching_input_Exp_B; @@ -65,8 +66,8 @@ assign Exponent_Matching_output_Exp = Exponent_Matching_Exp_Sub_input_1; //Decision for the exponent difference on the basis of which this is t be decided that either 1 or 0 will be added in the compliment_B and recompliment of the final answer (Please refer to the documentation fo detailed analyssis) -assign Exponent_Matching_output_Exp_Diff_Check = Exponent_Matching_Shif_Amount >= 8'b00110000 ; - +assign Exponent_Matching_output_Exp_Diff_Check = &(~Exponent_Matching_Shifter_output[4*man+7:man+man+4]) ; +assign Exponent_Matching_output_A_gt_B = (Exponent_Matching_Bit_Exp_A_gt_B) | ( (Exponent_Matching_Bit_Exp_A_ge_B) & (Exponent_Matching_Bit_Man_a_ge_Man_B) ); //decision fo rrounding bits assign Exponent_Matching_output_Guard = Exponent_Matching_Shifter_output[man+man+3] ;
diff --git a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v index 32ec8c9..cc7e802 100644 --- a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v +++ b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
@@ -1,5 +1,4 @@ - -module FMADD_PN_MUL( FMADD_PN_MUL_input_sign, FMADD_PN_MUL_input_exp_DB, FMADD_PN_MUL_input_multiplied_man, FMADD_PN_MUL_input_lzd, FMADD_PN_MUL_input_rm, FMADD_PN_MUL_input_A_neg, FMADD_PN_MUL_input_A_pos, FMADD_PN_MUL_input_A_sub, FMADD_PN_MUL_input_B_neg, FMADD_PN_MUL_input_B_pos, FMADD_PN_MUL_input_B_sub, FMADD_PN_MUL_output_no, FMADD_PN_MUL_output_overflow, FMADD_PN_MUL_output_sticky_PN); +module FMADD_PN_MUL( FMADD_PN_MUL_input_sign, FMADD_PN_MUL_input_exp_DB, FMADD_PN_MUL_input_multiplied_man, FMADD_PN_MUL_input_lzd, FMADD_PN_MUL_input_rm, FMADD_PN_MUL_input_A_neg, FMADD_PN_MUL_input_A_pos, FMADD_PN_MUL_input_A_sub, FMADD_PN_MUL_input_B_neg, FMADD_PN_MUL_input_B_pos, FMADD_PN_MUL_input_B_sub, FMADD_PN_MUL_output_no, FMADD_PN_MUL_output_sticky_PN); @@ -18,8 +17,7 @@ input [2 : 0]FMADD_PN_MUL_input_rm; -output [man+man+exp+5 : 0]FMADD_PN_MUL_output_no;//57 bit output having sign, 8bit exp and 48bit mantissa -output FMADD_PN_MUL_output_overflow; +output [man+man+exp+6 : 0]FMADD_PN_MUL_output_no;//58 bit output having sign, 9bit exp and 48bit mantissa output FMADD_PN_MUL_output_sticky_PN; wire [lzd : 0]FMADD_PN_MUL_input_lzd_shifts = FMADD_PN_MUL_input_lzd + 1'b1; @@ -55,11 +53,14 @@ wire [4 : 0]FMADD_PN_MUL_wire_lzd_true_sub_49; wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_4; wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_5; +wire FMADD_PN_MUL_wire_condition_8 ; +wire [exp+1 : 0] FMADD_PN_MUL_wire_exp_interim_6 ; +/* wire FMADD_PN_MUL_wire_exception_cond1; wire [man+man+exp+5 : 0]FMADD_PN_MUL_wire_output_interim_1; wire FMADD_PN_MUL_wire_exception_cond2; - +*/ assign FMADD_PN_MUL_wire_op_1 = (FMADD_PN_MUL_input_A_pos) & (FMADD_PN_MUL_input_B_pos) ; assign FMADD_PN_MUL_wire_op_2 = (FMADD_PN_MUL_input_A_neg) & (FMADD_PN_MUL_input_B_pos) | (FMADD_PN_MUL_input_A_pos) & (FMADD_PN_MUL_input_B_neg) ; @@ -136,28 +137,17 @@ assign FMADD_PN_MUL_wire_exp_interim_5 = FMADD_PN_MUL_wire_condition_7 ? FMADD_PN_MUL_wire_exp_interim_4 : FMADD_PN_MUL_wire_exp_interim_3 ; -wire [exp+1 : 0] FMADD_PN_MUL_wire_exp_interim_6 ; -wire FMADD_PN_MUL_wire_condition_8 ; - +// In case hidden bit of the mantissa is 1 and exponent is all 0 then add 1 in the exponent assign FMADD_PN_MUL_wire_condition_8 = ((FMADD_PN_MUL_wire_man_final[man+man+3]) & FMADD_PN_MUL_wire_pos_into_sub_subnormal & (&(!FMADD_PN_MUL_wire_exp_interim_5))); assign FMADD_PN_MUL_wire_exp_interim_6 = (FMADD_PN_MUL_wire_condition_8) ? (FMADD_PN_MUL_wire_exp_interim_5 + 1'b1) : (FMADD_PN_MUL_wire_exp_interim_5) ; -//Selection of what exception to output in case of overflow, max normal number or infinity - -assign FMADD_PN_MUL_wire_exception_cond1 = (FMADD_PN_MUL_input_rm == 3'b000 | FMADD_PN_MUL_input_rm == 3'b100) | ((!FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b011)) | ((FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b010)); -assign FMADD_PN_MUL_wire_output_interim_1 = (FMADD_PN_MUL_wire_exception_cond1) ? ({ FMADD_PN_MUL_input_sign, ({exp+1{1'b1}}), ({man+man+4{1'b0}}) }) : ({ FMADD_PN_MUL_input_sign, ({{exp{1'b1}}, 1'b0}), ({man+man+4{1'b1}}) }); -//condition to select output, either exception or result from main, in case 9th bit (singke precision) of exp is high or bits from 8:0 are high then it is overflow -assign FMADD_PN_MUL_wire_exception_cond2 = FMADD_PN_MUL_wire_exp_interim_6[exp+1] | (&FMADD_PN_MUL_wire_exp_interim_6[exp : 0]); -//Selecting what to output exception or result coming form main -assign FMADD_PN_MUL_output_no = (FMADD_PN_MUL_wire_exception_cond2) ? (FMADD_PN_MUL_wire_output_interim_1) : ({FMADD_PN_MUL_input_sign, (FMADD_PN_MUL_wire_exp_interim_6[exp : 0]), FMADD_PN_MUL_wire_man_final}) ; -//In case cond2 is high overflow flag is set to one -assign FMADD_PN_MUL_output_overflow = FMADD_PN_MUL_wire_exception_cond2; - -//in case shifts are greater than M+N or subnormal numbers are getting multiplied with each other then sticky_PN will get high. -assign FMADD_PN_MUL_output_sticky_PN = FMADD_PN_MUL_wire_shifts_overflow; +assign FMADD_PN_MUL_output_no = {FMADD_PN_MUL_input_sign, FMADD_PN_MUL_wire_exp_interim_6, FMADD_PN_MUL_wire_man_final}; //If mantissa after all the processing is zero than it means it has became zero due to shifting and sticky is one. assign FMADD_PN_MUL_wire_shifts_overflow = (!(|FMADD_PN_MUL_wire_man_final)) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub); +//in case shifts are greater than M+N or subnormal numbers are getting multiplied with each other then sticky_PN will get high. +assign FMADD_PN_MUL_output_sticky_PN = FMADD_PN_MUL_wire_shifts_overflow; + endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v index e79a7ba..8e9a69f 100644 --- a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v +++ b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
@@ -1,13 +1,9 @@ -// Designed by : ALi Raza Zaidi //mains modue of FMADD +//including coommon blocks -//mains modue of FMADD - -/*//including coommon blocks - -`include "FMADD_M_G.v" +/*`include "FMADD_M_G.v" `include "FMADD_Ext.v" `include "F_LZD_Main.v" `include "fma_LZD_L0.v" @@ -30,31 +26,6 @@ -//including coommon blocks -/* -`include "FMADD_mantissa_generator.v" -`include "FMADD_extender.v" -`include "fma_LZD.v" -`include "fma_LZD_L0.v" -`include "fma_LZD_L1.v" -`include "fma_LZD_L2.v" -`include "fma_LZD_L3.v" -`include "fma_LZD_L4.v" - -//including Multiplication LANE -`include "FMADD_exponent_addition.v" -`include "FMADD_mantissa_multiplication.v" -`include "FMADD_mul_post_normalization.v" -`include "FMADD_mul_rounding_block.v" - -//Includign Addition/Subtraction LANE -`include "FMADD_exponent_matching.v" -`include "FMADD_mantissa_addition.v" -`include "FMADD_add_post_normalization.v" -`include "FMADD_add_rounding_Block.v" -*/ - - module FPU_FMADD_SUBB_Top (FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B, FMADD_SUBB_input_IEEE_C, FMADD_SUBB_input_opcode,rst_l,FMADD_SUBB_input_Frm,FMADD_SUBB_output_IEEE_FMADD, FMADD_SUBB_output_S_Flags_FMADD, FMADD_SUBB_output_IEEE_FMUL, FMADD_SUBB_output_S_Flags_FMUL ); parameter std =31; @@ -123,7 +94,7 @@ //extend module : This module is responsible for making the input representable in IEEE exteded format wire [std+1 : 0] input_Extender_B; -wire [1+exp+2*(man+2):0] output_interim_Extender_A,output_interim_Extender_B; +wire [2+exp+2*(man+2):0] output_interim_Extender_A,output_interim_Extender_B; //selection of the second operand of the extender : If addition is the inputted instruction B goes to extender otherwise C goes to the Extender assign input_Extender_B = (| FMADD_SUBB_input_opcode[1:0]) ? output_interim_M_G_B : output_interim_M_G_C; @@ -202,8 +173,8 @@ defparam Leading_Zero_detection.lzd = lzd; //post normalaization Module -wire [1+exp+2*(man+2):0] output_interim_post_normalization_IEEE; -wire output_interim_post_normalization_mul_overflow_flag, output_interim_post_normalization_mul_sticky; +wire [2+exp+2*(man+2):0] output_interim_post_normalization_IEEE_A; +wire output_interim_post_normalization_mul_sticky; FMADD_PN_MUL Post_Normalization_Mul ( . FMADD_PN_MUL_input_sign (output_interim_exponent_addition_sign), @@ -216,8 +187,7 @@ . FMADD_PN_MUL_input_B_pos (output_interim_B_pos_exp), . FMADD_PN_MUL_input_A_neg (output_interim_A_neg_exp), . FMADD_PN_MUL_input_B_neg (output_interim_B_neg_exp), - . FMADD_PN_MUL_output_no (output_interim_post_normalization_IEEE), - . FMADD_PN_MUL_output_overflow (output_interim_post_normalization_mul_overflow_flag), + . FMADD_PN_MUL_output_no (output_interim_post_normalization_IEEE_A), . FMADD_PN_MUL_output_sticky_PN(output_interim_post_normalization_mul_sticky), . FMADD_PN_MUL_input_rm(FMADD_SUBB_input_Frm) ); @@ -233,9 +203,8 @@ wire [2:0] output_interim_rounding_Block_S_Flag; FMADD_ROUND_MUL Rounding_Block_Mul ( - .FMADD_ROUND_MUL_input_overflow(output_interim_post_normalization_mul_overflow_flag), .FMADD_ROUND_MUL_input_sticky_PN(output_interim_post_normalization_mul_sticky), - .FMADD_ROUND_MUL_input_no(output_interim_post_normalization_IEEE), + .FMADD_ROUND_MUL_input_no(output_interim_post_normalization_IEEE_A), .FMADD_ROUND_MUL_input_rm(FMADD_SUBB_input_Frm), .FMADD_ROUND_MUL_output_no(output_rounding_Block), .FMADD_ROUND_MUL_output_S_Flags(output_interim_rounding_Block_S_Flag) @@ -248,8 +217,9 @@ ///=interim wires and register for FMADD Lane //ppelining registers -wire [1+exp+2*(man+2):0] input_interim_ADD_LANE_A; -wire [1+exp+2*(man+2):0] input_interim_ADD_LANE_B; +wire [2+exp+2*(man+2):0] input_interim_ADD_LANE_A; +wire [2+exp+2*(man+2):0] input_interim_ADD_LANE_B; +wire [2+exp+2*(man+2):0] output_interim_post_normalization_IEEE; //inputs to the FMADD LANE assign input_interim_ADD_LANE_A = ( |(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_A : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_post_normalization_IEEE : 57'h000000000000000 ; @@ -259,20 +229,23 @@ wire output_interim_Exponent_Mathcing_Sign; wire [man+man+3:0] output_interim_Exponent_Mathcing_Mantissa_A; wire [man+man+3:0] output_interim_Exponent_Mathcing_Mantissa_B; -wire [exp:0] output_interim_Exponent_Mathcing_Exponent; +wire [exp+1:0] output_interim_Exponent_Mathcing_Exponent; wire output_interim_Exponent_Mathcing_Eff_add; wire output_interim_Exponent_Mathcing_Eff_sub; wire output_interim_Exponent_Mathcing_Guard; wire output_interim_Exponent_Mathcing_Round; wire output_interim_Exponent_Mathcing_Sticky; wire output_interim_Exponent_Mathcing_Exp_Diff_Check; +wire output_interim_Exponent_Mathcing_A_gt_B; +assign output_interim_post_normalization_IEEE = ( (&(~output_interim_post_normalization_IEEE_A[1+exp+2*(man+2):man+man+4])) & (~underflow_FMUL) ) ? {output_interim_post_normalization_IEEE_A[2+exp+2*(man+2)],{exp+1{1'b0}},1'b1,output_interim_post_normalization_IEEE_A[man+man+3:0] } : output_interim_post_normalization_IEEE_A ; + FMADD_Exponent_Matching Exponent_Matching ( - .Exponent_Matching_input_Sign_A ( input_interim_ADD_LANE_A[1+exp+2*(man+2)] ), - .Exponent_Matching_input_Sign_B( input_interim_ADD_LANE_B[1+exp+2*(man+2)] ), - .Exponent_Matching_input_Exp_A( input_interim_ADD_LANE_A[exp+2*(man+2): man+man+4] ), - .Exponent_Matching_input_Exp_B( input_interim_ADD_LANE_B[exp+2*(man+2): man+man+4] ), + .Exponent_Matching_input_Sign_A ( input_interim_ADD_LANE_A[2+exp+2*(man+2)] ), + .Exponent_Matching_input_Sign_B( input_interim_ADD_LANE_B[2+exp+2*(man+2)] ), + .Exponent_Matching_input_Exp_A( input_interim_ADD_LANE_A[1+exp+2*(man+2): man+man+4] ), + .Exponent_Matching_input_Exp_B( input_interim_ADD_LANE_B[1+exp+2*(man+2): man+man+4] ), .Exponent_Matching_input_Mantissa_A( input_interim_ADD_LANE_A[man+man+3 : 0] ), .Exponent_Matching_input_Mantissa_B( input_interim_ADD_LANE_B[man+man+3 : 0] ), .Exponent_Matching_input_opcode( { FMADD_SUBB_input_opcode[1] | FMADD_SUBB_input_opcode[4] | FMADD_SUBB_input_opcode[6] , FMADD_SUBB_input_opcode[0] | FMADD_SUBB_input_opcode[5] | FMADD_SUBB_input_opcode[3]} ), @@ -285,7 +258,8 @@ .Exponent_Matching_output_Sticky( output_interim_Exponent_Mathcing_Sticky), .Exponent_Matching_output_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub), .Exponent_Matching_output_Eff_add( output_interim_Exponent_Mathcing_Eff_add), - .Exponent_Matching_output_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check) + .Exponent_Matching_output_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check), + .Exponent_Matching_output_A_gt_B (output_interim_Exponent_Mathcing_A_gt_B) ); defparam Exponent_Matching.std = std; defparam Exponent_Matching.exp = exp; @@ -301,7 +275,8 @@ .Mantissa_Addition_input_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub), .Mantissa_Addition_output_Mantissa(output_interim_Mantissa_Addition_Mantissa ), .Mantissa_Addition_output_Carry(output_interim_Mantissa_Addition_Carry), - .Mantissa_Addition_input_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check) + .Mantissa_Addition_input_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check), + .Mantissa_Addition_input_A_gt_B(output_interim_Exponent_Mathcing_A_gt_B) ); defparam Mantissa_Addition.std = std; defparam Mantissa_Addition.exp = exp; @@ -336,7 +311,7 @@ wire [exp:0] output_interim_Rounding_Block_Exp; wire [man:0] output_interim_Rounding_Block_Mantissa; wire output_interim_Rounding_Block_Sign; -wire [1:0] output_interim_Rounding_Block_S_flags; +wire [2:0] output_interim_Rounding_Block_S_flags; wire [2:0] input_rounding_block_Add_frm; assign input_rounding_block_Add_frm = (|FMADD_SUBB_input_opcode[6:3] | (|FMADD_SUBB_input_opcode[1:0]) ) ? FMADD_SUBB_input_Frm : 3'b000; @@ -364,7 +339,8 @@ //addition Lane output POrts assign FMADD_SUBB_output_IEEE_FMADD = ( ((|FMADD_SUBB_input_opcode[1:0]) | (|FMADD_SUBB_input_opcode[6:3]) ) & (rst_l) ) ? { output_interim_Rounding_Block_Sign, output_interim_Rounding_Block_Exp ,output_interim_Rounding_Block_Mantissa } :{ std+1 {1'b0} } ; -assign FMADD_SUBB_output_S_Flags_FMADD = ( ( (|FMADD_SUBB_input_opcode[1:0]) | (|FMADD_SUBB_input_opcode[6:3]) ) & (rst_l) ) ? {output_interim_Rounding_Block_S_flags[1],1'b0,output_interim_Rounding_Block_S_flags[0]} : 3'b00; +assign FMADD_SUBB_output_S_Flags_FMADD = ( ( (|FMADD_SUBB_input_opcode[1:0]) | (|FMADD_SUBB_input_opcode[6:3]) ) & (rst_l) ) ? {output_interim_Rounding_Block_S_flags[1],output_interim_Rounding_Block_S_flags[2],output_interim_Rounding_Block_S_flags[0]} : 3'b00; endmodule +
diff --git a/verilog/rtl/FPU/FMADD_extender.v b/verilog/rtl/FPU/FMADD_extender.v index 3cd243a..2b929d8 100644 --- a/verilog/rtl/FPU/FMADD_extender.v +++ b/verilog/rtl/FPU/FMADD_extender.v
@@ -10,11 +10,11 @@ //output declaration -output [1+exp+2*(man+2):0] Extender_output_A,Extender_output_B; +output [2+exp+2*(man+2):0] Extender_output_A,Extender_output_B; //main functionlity -assign Extender_output_A = {Extender_input_A,{man+2{1'b0}}} ; -assign Extender_output_B = {Extender_input_B,{man+2{1'b0}}} ; +assign Extender_output_A = {Extender_input_A[std+1],1'b0,Extender_input_A[std:0],{man+2{1'b0}}} ; +assign Extender_output_B = {Extender_input_B[std+1],1'b0,Extender_input_B[std:0],{man+2{1'b0}}} ; -endmodule +endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_mantissa_addition.v b/verilog/rtl/FPU/FMADD_mantissa_addition.v index d50180d..1436610 100644 --- a/verilog/rtl/FPU/FMADD_mantissa_addition.v +++ b/verilog/rtl/FPU/FMADD_mantissa_addition.v
@@ -1,7 +1,7 @@ //mantissa addition module -module FMADD_Mantissa_Addition( Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B,Mantissa_Addition_input_Eff_Sub,Mantissa_Addition_output_Mantissa, Mantissa_Addition_output_Carry,Mantissa_Addition_input_Exp_Diff_Check ); +module FMADD_Mantissa_Addition( Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B,Mantissa_Addition_input_Eff_Sub,Mantissa_Addition_output_Mantissa, Mantissa_Addition_output_Carry,Mantissa_Addition_input_Exp_Diff_Check,Mantissa_Addition_input_A_gt_B ); //declaration of paramters parameter std =31; @@ -11,7 +11,7 @@ //declaration of input ports input [man+man+3:0] Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B; input Mantissa_Addition_input_Eff_Sub; -input Mantissa_Addition_input_Exp_Diff_Check; +input Mantissa_Addition_input_Exp_Diff_Check, Mantissa_Addition_input_A_gt_B; /* opcode[0]= fadd; @@ -19,9 +19,12 @@ */ -wire [man+man+3:0] interim_mantissa_B,interim_mantissa_B_adder; -wire Mantissa_Addition_interim_Carry; -wire [man+man+3:0] Mantissa_Addition_Compliment_B; +wire [man+man+3:0] interim_mantissa_B_adder; +wire Mantissa_Addition_interim_Carry,Mantissa_Addition_interim_Compliment_Carry; +wire [man+man+3:0] Mantissa_Addition_Compliment_B,Mantissa_Addition_Compliment_1_Factor; +wire [man+man+3:0] Mantissa_Addition_Compliment_Lane_input,Mantissa_Addition_Adder_Lane_input_A,Mantissa_Addition_Adder_Lane_input_B; +wire Mantissa_Addition_Compliment_Addend; + //declartion of output piorts output Mantissa_Addition_output_Carry; @@ -29,12 +32,24 @@ //Main functionality -assign Mantissa_Addition_Compliment_B = ( (~(Mantissa_Addition_input_Mantissa_B)) + (~Mantissa_Addition_input_Exp_Diff_Check) ); -assign interim_mantissa_B = (Mantissa_Addition_input_Eff_Sub) ? Mantissa_Addition_Compliment_B : Mantissa_Addition_input_Mantissa_B ; -assign {Mantissa_Addition_interim_Carry,interim_mantissa_B_adder} = {1'b0, interim_mantissa_B} + {1'b0,Mantissa_Addition_input_Mantissa_A}; +//decision of two operands for the final adders +assign Mantissa_Addition_Compliment_Lane_input = (Mantissa_Addition_input_A_gt_B) ? Mantissa_Addition_input_Mantissa_B : Mantissa_Addition_input_Mantissa_A; +assign Mantissa_Addition_Adder_Lane_input_A = (Mantissa_Addition_input_A_gt_B) ? Mantissa_Addition_input_Mantissa_A : Mantissa_Addition_input_Mantissa_B; -assign Mantissa_Addition_output_Mantissa = ( (~Mantissa_Addition_interim_Carry) & Mantissa_Addition_input_Eff_Sub ) ? ( ~(interim_mantissa_B_adder) + (~Mantissa_Addition_input_Exp_Diff_Check) ) : interim_mantissa_B_adder; +//compliment of the Smaller operand of the two +assign Mantissa_Addition_Compliment_Addend = (~Mantissa_Addition_input_Exp_Diff_Check); +assign Mantissa_Addition_Compliment_1_Factor = (~Mantissa_Addition_Compliment_Lane_input); +assign {Mantissa_Addition_interim_Compliment_Carry,Mantissa_Addition_Compliment_B} = ( {1'b0,Mantissa_Addition_Compliment_1_Factor} + {1'b0,Mantissa_Addition_Compliment_Addend} ); + +//Opernad two of the Adder lane +assign Mantissa_Addition_Adder_Lane_input_B = (Mantissa_Addition_input_Eff_Sub) ? Mantissa_Addition_Compliment_B : Mantissa_Addition_Compliment_Lane_input ; + + +assign {Mantissa_Addition_interim_Carry,interim_mantissa_B_adder} = {1'b0, Mantissa_Addition_Adder_Lane_input_A} + {1'b0,Mantissa_Addition_Adder_Lane_input_B}; + + +assign Mantissa_Addition_output_Mantissa = ( (~Mantissa_Addition_interim_Carry) & Mantissa_Addition_input_Eff_Sub & (~Mantissa_Addition_interim_Compliment_Carry) ) ? ( ~(interim_mantissa_B_adder) + (Mantissa_Addition_Compliment_Addend) ) : interim_mantissa_B_adder; assign Mantissa_Addition_output_Carry = Mantissa_Addition_interim_Carry;
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Addition.v b/verilog/rtl/FPU/FMADD_rounding_block_Addition.v index 509e51c..0e509c1 100644 --- a/verilog/rtl/FPU/FMADD_rounding_block_Addition.v +++ b/verilog/rtl/FPU/FMADD_rounding_block_Addition.v
@@ -17,7 +17,7 @@ output [man:0] Rounding_Block_output_Mantissa; output [exp:0] Rounding_Block_output_Exponent; output Rounding_Block_output_Sign; -output [1:0] Rounding_Block_output_S_Flags; +output [2:0] Rounding_Block_output_S_Flags; //interim wires wire Rounding_Block_Bit_pos_inf; @@ -44,17 +44,19 @@ assign { Rounding_Block_Bit_Carry, Rounding_Block_interim_Mantissa} = {1'b0,Rounding_Block_input_Mantissa} + Rounding_Block_Bit_Round_up ; assign Rounding_Block_Shifter_output = (Rounding_Block_Bit_Carry) ? { Rounding_Block_Bit_Carry , Rounding_Block_interim_Mantissa[man+1:1]} : Rounding_Block_interim_Mantissa[man+1:0] ; assign Rounding_Block_interim_exponent = Rounding_Block_input_Exponent + Rounding_Block_Bit_Carry; -assign Roinding_Block_Overflow_check = (Rounding_Block_interim_exponent == 9'h0ff ); +assign Roinding_Block_Overflow_check = (Rounding_Block_interim_exponent[exp+1] | (& Rounding_Block_input_Exponent[exp:0]) ); -assign Rounding_Block_final_exponent = (Roinding_Block_Overflow_check) ? {exp+1{1'b1}} : Rounding_Block_interim_exponent[exp:0] ; +assign Rounding_Block_final_exponent = (Roinding_Block_Overflow_check) ? ( ((Rounding_Block_input_Frm ==3'b000 | Rounding_Block_input_Frm == 3'b100 | (Rounding_Block_input_Frm == 3'b011 & (~Rounding_Block_input_Sign)) | (Rounding_Block_input_Frm == 3'b010 & (Rounding_Block_input_Sign)) ) ) ? {exp+1{1'b1}} : ((Rounding_Block_input_Frm ==3'b001 | (Rounding_Block_input_Frm == 3'b010 & (~Rounding_Block_input_Sign))) | (Rounding_Block_input_Frm == 3'b011 & (Rounding_Block_input_Sign)) ) ? {{exp{1'b1}},1'b0} : {exp+1{1'b0}} ) : Rounding_Block_interim_exponent[exp:0] ; assign Rounding_Block_output_Exponent = (Rounding_Block_Shifter_output[man+1] ) ? Rounding_Block_final_exponent : {exp+1{1'b0}} ; -assign Rounding_Block_output_Mantissa = (Roinding_Block_Overflow_check) ? {man+1 {1'b0}} : Rounding_Block_Shifter_output[man:0]; +assign Rounding_Block_output_Mantissa = (Roinding_Block_Overflow_check) ? ( ((Rounding_Block_input_Frm ==3'b000 | Rounding_Block_input_Frm == 3'b100 | (Rounding_Block_input_Frm == 3'b011 & (~Rounding_Block_input_Sign)) | (Rounding_Block_input_Frm == 3'b010 & (Rounding_Block_input_Sign)) ) ) ? {man+1{1'b0}} : ((Rounding_Block_input_Frm ==3'b001 | (Rounding_Block_input_Frm == 3'b010 & (~Rounding_Block_input_Sign))) | (Rounding_Block_input_Frm == 3'b011 & (Rounding_Block_input_Sign)) ) ? {man+1{1'b1}} : {man+1{1'b0}} ) : Rounding_Block_Shifter_output[man:0]; assign Rounding_Block_output_Sign = Rounding_Block_input_Sign; + //delcaration of inexact flag -assign Rounding_Block_output_S_Flags[0] = Rounding_Block_input_Round | Rounding_Block_input_Guard | Rounding_Block_input_Sticky; +assign Rounding_Block_output_S_Flags[0] = Rounding_Block_input_Sticky | Rounding_Block_input_Guard | Rounding_Block_input_Round | Roinding_Block_Overflow_check ; //declaration of overflow flag assign Rounding_Block_output_S_Flags[1] = Roinding_Block_Overflow_check ; - +//declaration of under flow flag +assign Rounding_Block_output_S_Flags[2] = (~Rounding_Block_Shifter_output[man+1]) & ( (Rounding_Block_input_Sticky) | (Rounding_Block_input_Guard) | (Rounding_Block_input_Round) ) ; endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v index cc5705b..e330e87 100644 --- a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v +++ b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
@@ -1,21 +1,25 @@ -module FMADD_ROUND_MUL (FMADD_ROUND_MUL_input_overflow, FMADD_ROUND_MUL_input_sticky_PN, FMADD_ROUND_MUL_input_no, FMADD_ROUND_MUL_input_rm, FMADD_ROUND_MUL_output_no, FMADD_ROUND_MUL_output_S_Flags); -parameter std=31; -parameter man =22; -parameter exp = 7; +module FMADD_ROUND_MUL (FMADD_ROUND_MUL_input_sticky_PN, FMADD_ROUND_MUL_input_no, FMADD_ROUND_MUL_input_rm, FMADD_ROUND_MUL_output_no, FMADD_ROUND_MUL_output_S_Flags); + +parameter std = 31; +parameter man = 22; +parameter exp = 7; parameter biad = 127; +//man+man+exp+6 == sign +//man+man+exp+5 : man+man+4 == 9bit exp +//man+man+exp+4 : man+man+4 == 8bit exp +//man+man+3 : 0 == 48bit mantissa +//man+man+3 : man+2 == 24 bit mantissa -input [man+man+exp+5 : 0]FMADD_ROUND_MUL_input_no; +input [man+man+exp+6 : 0]FMADD_ROUND_MUL_input_no; input [2 : 0] FMADD_ROUND_MUL_input_rm; -input FMADD_ROUND_MUL_input_overflow; input FMADD_ROUND_MUL_input_sticky_PN; output [std : 0] FMADD_ROUND_MUL_output_no; output [2 : 0]FMADD_ROUND_MUL_output_S_Flags; - wire FMADD_ROUND_MUL_output_inexact, FMADD_ROUND_MUL_output_underflow, FMADD_ROUND_MUL_output_overflow; wire FMADD_ROUND_MUL_wire_guard, FMADD_ROUND_MUL_wire_round, FMADD_ROUND_MUL_wire_sticky; wire FMADD_ROUND_MUL_wire_condition_inf, FMADD_ROUND_MUL_wire_condition_rnte, FMADD_ROUND_MUL_wire_condition_rntmm; @@ -24,35 +28,50 @@ wire [man+1 : 0] FMADD_ROUND_MUL_wire_rounded_man; wire [exp : 0] FMADD_ROUND_MUL_wire_rounded_exp; wire [man : 0] FMADD_ROUND_MUL_wire_final_man; - -assign FMADD_ROUND_MUL_output_S_Flags = {FMADD_ROUND_MUL_output_overflow,FMADD_ROUND_MUL_output_underflow,FMADD_ROUND_MUL_output_inexact}; +wire FMADD_ROUND_MUL_wire_overflow_PN; +wire FMADD_ROUND_MUL_wire_exception_cond1; +wire [std : 0] FMADD_ROUND_MUL_wire_output_interim_1; +wire FMADD_ROUND_MUL_wire_exception_cond2; assign FMADD_ROUND_MUL_wire_guard = FMADD_ROUND_MUL_input_no[man+1]; assign FMADD_ROUND_MUL_wire_round = FMADD_ROUND_MUL_input_no[man]; assign FMADD_ROUND_MUL_wire_sticky = |FMADD_ROUND_MUL_input_no[man-1 : 0]; -assign FMADD_ROUND_MUL_wire_condition_inf = ((FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_guard | (FMADD_ROUND_MUL_wire_sticky)) & ((FMADD_ROUND_MUL_input_rm == 3'b011 & ~FMADD_ROUND_MUL_input_no[man+2+man+2+exp+1])|(FMADD_ROUND_MUL_input_rm == 3'b010 & FMADD_ROUND_MUL_input_no[man+2+man+2+exp+1]))); +assign FMADD_ROUND_MUL_wire_condition_inf = ((FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_guard | (FMADD_ROUND_MUL_wire_sticky)) & ((FMADD_ROUND_MUL_input_rm == 3'b011 & ~FMADD_ROUND_MUL_input_no[man+man+exp+6])|(FMADD_ROUND_MUL_input_rm == 3'b010 & FMADD_ROUND_MUL_input_no[man+man+exp+6]))); assign FMADD_ROUND_MUL_wire_condition_rnte = (FMADD_ROUND_MUL_input_rm == 3'b000 & ((FMADD_ROUND_MUL_wire_guard & (FMADD_ROUND_MUL_wire_round | (FMADD_ROUND_MUL_wire_sticky))) | (FMADD_ROUND_MUL_wire_guard & ((~FMADD_ROUND_MUL_wire_round) & ~(FMADD_ROUND_MUL_wire_sticky)) & FMADD_ROUND_MUL_input_no[man+2]))); assign FMADD_ROUND_MUL_wire_condition_rntmm = (FMADD_ROUND_MUL_input_rm == 3'b100 & ((FMADD_ROUND_MUL_wire_guard & (FMADD_ROUND_MUL_wire_round | (FMADD_ROUND_MUL_wire_sticky))) | (FMADD_ROUND_MUL_wire_guard & ((~FMADD_ROUND_MUL_wire_round) & ~(FMADD_ROUND_MUL_wire_sticky))))); -assign FMADD_ROUND_MUL_wire_condition_sticky = FMADD_ROUND_MUL_input_sticky_PN & (((!FMADD_ROUND_MUL_input_no[man+man+exp+5]) & (FMADD_ROUND_MUL_input_rm == 3'b011)) | (FMADD_ROUND_MUL_input_no[man+man+exp+5] & (FMADD_ROUND_MUL_input_rm == 3'b010))); +assign FMADD_ROUND_MUL_wire_condition_sticky = FMADD_ROUND_MUL_input_sticky_PN & (((!FMADD_ROUND_MUL_input_no[man+man+exp+6]) & (FMADD_ROUND_MUL_input_rm == 3'b011)) | (FMADD_ROUND_MUL_input_no[man+man+exp+6] & (FMADD_ROUND_MUL_input_rm == 3'b010))); //FMADD_ROUND_MUL_wire_condition_sticky logic for rounding on the basis os STICKY bit coming from previous module, inc is done incase sticky_pn == 1 and sign == 0 and rm == 3 OR sticky_pn == 1 and sign ==1 and rm == 10 // Add 1 in case rounding says so. Input_overflow is added so that inc becomes ineffective in case overflow is high -assign FMADD_ROUND_MUL_wire_inc = (FMADD_ROUND_MUL_wire_condition_inf | FMADD_ROUND_MUL_wire_condition_rnte | FMADD_ROUND_MUL_wire_condition_rntmm | FMADD_ROUND_MUL_wire_condition_sticky) & (!FMADD_ROUND_MUL_input_overflow); -assign FMADD_ROUND_MUL_wire_rounded_man = FMADD_ROUND_MUL_input_no[man+2+man+1 : man+2] + FMADD_ROUND_MUL_wire_inc; +assign FMADD_ROUND_MUL_wire_inc = (FMADD_ROUND_MUL_wire_condition_inf | FMADD_ROUND_MUL_wire_condition_rnte | FMADD_ROUND_MUL_wire_condition_rntmm | FMADD_ROUND_MUL_wire_condition_sticky) & (!FMADD_ROUND_MUL_output_overflow); +assign FMADD_ROUND_MUL_wire_rounded_man = FMADD_ROUND_MUL_input_no[man+man+3 : man+2] + FMADD_ROUND_MUL_wire_inc; //If hidden bit before rounding is zero and after rounding is one then add one in exponent other wise don't -assign FMADD_ROUND_MUL_wire_rounded_exp = ((!FMADD_ROUND_MUL_input_no[man+2+man+1]) & (FMADD_ROUND_MUL_wire_rounded_man[man+1])) ? -FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2] + 1'b1 : FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2]; +//this occur only for near subnormal outputs +assign FMADD_ROUND_MUL_wire_rounded_exp = ((!FMADD_ROUND_MUL_input_no[man+man+3]) & (FMADD_ROUND_MUL_wire_rounded_man[man+1])) ? +FMADD_ROUND_MUL_input_no[man+man+exp+4 : man+man+4] + 1'b1 : FMADD_ROUND_MUL_input_no[man+man+exp+4 : man+man+4]; +wire [56:0] check; +assign check = ({ FMADD_ROUND_MUL_input_no[man+man+exp+6], ({{exp{1'b1}}, 1'b0}), ({man+man+4{1'b1}}) }); + + + +//Selection of what exception to output in case of overflow, max normal number or infinity +assign FMADD_ROUND_MUL_wire_exception_cond1 = (FMADD_ROUND_MUL_input_rm == 3'b000 | FMADD_ROUND_MUL_input_rm == 3'b100) | ((!FMADD_ROUND_MUL_input_no[man+man+exp+6]) & (FMADD_ROUND_MUL_input_rm == 3'b011)) | ((FMADD_ROUND_MUL_input_no[man+man+exp+6]) & (FMADD_ROUND_MUL_input_rm == 3'b010)); +assign FMADD_ROUND_MUL_wire_output_interim_1 = (FMADD_ROUND_MUL_wire_exception_cond1) ? ({ FMADD_ROUND_MUL_input_no[man+man+exp+6], ({exp+1{1'b1}}), ({man+1{1'b0}}) }) : ({ FMADD_ROUND_MUL_input_no[man+man+exp+6], ({{exp{1'b1}}, 1'b0}), ({man+1{1'b1}}) }); +//condition to select output, either exception or result from main, in case 9th bit (single precision) of exp is high or bits from 8:0 are high then it is overflow +assign FMADD_ROUND_MUL_wire_exception_cond2 = FMADD_ROUND_MUL_input_no[man+man+exp+5] | (&FMADD_ROUND_MUL_input_no[man+man+exp+4 : man+man+4]); + +//Selecting what to output exception or result coming form main +assign FMADD_ROUND_MUL_output_no = (FMADD_ROUND_MUL_wire_exception_cond2) ? (FMADD_ROUND_MUL_wire_output_interim_1) : ({FMADD_ROUND_MUL_input_no[man+man+exp+6], (FMADD_ROUND_MUL_wire_rounded_exp), (FMADD_ROUND_MUL_wire_rounded_man[man:0])}) ; +//In case cond2 is high overflow flag is set to one +assign FMADD_ROUND_MUL_output_overflow = FMADD_ROUND_MUL_wire_exception_cond2; //overflow occurs in case the exp and man before rounding is complete zero. assign FMADD_ROUND_MUL_output_underflow = &(!(FMADD_ROUND_MUL_input_no[(man+man+exp+4) : (man+man+3)])); //Inexact is high in case any of the GRS are high or if overflow has occured -assign FMADD_ROUND_MUL_output_inexact = FMADD_ROUND_MUL_wire_guard | FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_sticky | FMADD_ROUND_MUL_input_sticky_PN | FMADD_ROUND_MUL_input_overflow; -//overflow is detected in previous module of PN -assign FMADD_ROUND_MUL_output_overflow = FMADD_ROUND_MUL_input_overflow; - -assign FMADD_ROUND_MUL_output_no = {FMADD_ROUND_MUL_input_no[man+man+exp+5], (FMADD_ROUND_MUL_wire_rounded_exp), FMADD_ROUND_MUL_wire_rounded_man[man:0]}; - +assign FMADD_ROUND_MUL_output_inexact = FMADD_ROUND_MUL_wire_guard | FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_sticky | FMADD_ROUND_MUL_input_sticky_PN | FMADD_ROUND_MUL_output_overflow; +//Concatinating all flags +assign FMADD_ROUND_MUL_output_S_Flags = {FMADD_ROUND_MUL_output_overflow,FMADD_ROUND_MUL_output_underflow,FMADD_ROUND_MUL_output_inexact}; endmodule
diff --git a/verilog/rtl/FPU/FPU_Input_Validation.v b/verilog/rtl/FPU/FPU_Input_Validation.v index 7d6fcfe..08a577e 100644 --- a/verilog/rtl/FPU/FPU_Input_Validation.v +++ b/verilog/rtl/FPU/FPU_Input_Validation.v
@@ -287,7 +287,7 @@ assign INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( INPUT_VALIDATION_Bit_double_infinity & (INPUT_VALIDATION_input_ieee_A[std] & INPUT_VALIDATION_input_ieee_B[std]) ) ); -assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd = (INPUT_VALIDATION_input_opcode[0] & (INPUT_VALIDATION_Bit_double_zero & ( (~INPUT_VALIDATION_input_ieee_A[std]) & (~INPUT_VALIDATION_input_ieee_B[std]) ) ) ) ; +assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd = (INPUT_VALIDATION_input_opcode[0] & ((INPUT_VALIDATION_Bit_double_zero & ( (~INPUT_VALIDATION_input_ieee_A[std]) & (~INPUT_VALIDATION_input_ieee_B[std]) ) ) | (INPUT_VALIDATION_Bit_Equal & INPUT_VALIDATION_Bit_xor_sign )) ) ; assign INPUT_VALIDATION_Bit_negitive_zero_Caught_Fadd = (INPUT_VALIDATION_input_opcode[0] & (INPUT_VALIDATION_Bit_double_zero & ( INPUT_VALIDATION_Bit_xor_sign ) ) ) ; @@ -305,7 +305,7 @@ assign INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fsubb = ( INPUT_VALIDATION_input_opcode[1] & ( INPUT_VALIDATION_Bit_double_infinity & (INPUT_VALIDATION_Bit_xor_sign) ) ); //the resulting infinicty in this case would be a negative infinity -assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb = (INPUT_VALIDATION_input_opcode[1] & ( (INPUT_VALIDATION_Bit_Equal) | ( ( (~INPUT_VALIDATION_input_ieee_A[std]) | (INPUT_VALIDATION_input_ieee_A[std] & (INPUT_VALIDATION_input_ieee_B[std]) ) ) & INPUT_VALIDATION_Bit_double_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb); +assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb = (INPUT_VALIDATION_input_opcode[1] & ( (INPUT_VALIDATION_Bit_Equal & (~INPUT_VALIDATION_Bit_xor_sign)) | ( ( (~INPUT_VALIDATION_input_ieee_A[std]) | (INPUT_VALIDATION_input_ieee_A[std] & (INPUT_VALIDATION_input_ieee_B[std]) ) ) & INPUT_VALIDATION_Bit_double_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb); assign INPUT_VALIDATION_Bit_negitive_zero_Caught_Fsubb = (INPUT_VALIDATION_input_opcode[1] & (INPUT_VALIDATION_Bit_double_zero & (INPUT_VALIDATION_input_ieee_A[std] & (~INPUT_VALIDATION_input_ieee_B[std])) ) );