CLKs per bit added
diff --git a/verilog/dv/FPU_Bfloat/FPU_Bfloat.c b/verilog/dv/FPU_Bfloat/FPU_Bfloat.c
index 7a575db..b9035ba 100644
--- a/verilog/dv/FPU_Bfloat/FPU_Bfloat.c
+++ b/verilog/dv/FPU_Bfloat/FPU_Bfloat.c
@@ -65,8 +65,10 @@
// Configure LA probes as inputs to the cpu put zero
// Configure LA probes as outputs from the cpu put one
- reg_la0_oenb = reg_la0_iena = 0x00000000; // configuring as output
+ reg_la0_oenb = reg_la0_iena = 0xFFFF0000; // CLK per bit
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // CLK per bit
reg_la2_oenb = reg_la2_iena = 0x00000002; // 65 bit as input to user proj and output from cpu for reset
+ reg_la0_data = 0x015C0000; // CLKs per bit
reg_la2_data = 0x00000000; // reset
reg_la2_data = 0x00000002;
reg_la2_oenb = reg_la2_iena = 0x00000000; // 64 anf 65 bit as input to user proj and output from cpu
diff --git a/verilog/dv/FPU_Bfloat/FPU_Bfloat_tb.v b/verilog/dv/FPU_Bfloat/FPU_Bfloat_tb.v
index d6a7970..b8c7622 100644
--- a/verilog/dv/FPU_Bfloat/FPU_Bfloat_tb.v
+++ b/verilog/dv/FPU_Bfloat/FPU_Bfloat_tb.v
@@ -74,7 +74,7 @@
wait(mprj_io_0 == 16'hC178);
*/
// Observe Output pins [23:8] for Fsign and I2F
-
+ /*
wait(mprj_io_0 == 16'h449A);
wait(mprj_io_0 == 16'h3042);
wait(mprj_io_0 == 16'h491E);
@@ -90,7 +90,7 @@
wait(mprj_io_0 == 16'h475D);
wait(mprj_io_0 == 16'h4641);
wait(mprj_io_0 == 16'h475D);
-
+ */
// Observe Output pins [23:8] for FClass and F2I
/*
wait(mprj_io_0 == 16'h04d0);
@@ -125,16 +125,16 @@
wait(mprj_io_0 == 16'hBCF0);
*/
// Observe Output pins [23:8] for FMUL
- /*
- wait(mprj_io_0 == 16'h60C2);
- wait(mprj_io_0 == 16'h30A7);
- wait(mprj_io_0 == 16'h67FF);
- wait(mprj_io_0 == 16'h78DF);
- wait(mprj_io_0 == 16'h7C00);
- wait(mprj_io_0 == 16'h5124);
- wait(mprj_io_0 == 16'h6058);
+
+ wait(mprj_io_0 == 16'h5D44);
+ wait(mprj_io_0 == 16'h2D29);
+ wait(mprj_io_0 == 16'h63ED);
+ wait(mprj_io_0 == 16'h7508);
+ wait(mprj_io_0 == 16'h79BA);
+ wait(mprj_io_0 == 16'h4DA1);
+ wait(mprj_io_0 == 16'h5C80);
wait(mprj_io_0 == 16'h0000);
- */
+
$display("MPRJ-IO state = %h", mprj_io[23:8]);
`ifdef GL
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index b2f55b8..8095aac 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -62,6 +62,7 @@
// FPU FSM
input clk,
input rst_l,
+ input [15:0] CLKS_PER_BIT,
output [15:0] FPU_hp_result
// FPU FSM
@@ -148,7 +149,7 @@
.i_Clock(clk),
.rst_ni(rst_l),
.i_Rx_Serial(r_Rx_Serial),
- .CLKS_PER_BIT(16'd348),
+ .CLKS_PER_BIT(CLKS_PER_BIT),
.o_Rx_DV(o_Rx_DV),
.o_Rx_Byte(o_Rx_Byte)
);
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 49cc795..4e8077a 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -73,6 +73,7 @@
wire rst;
wire rx_i;
wire [15:0] FPU_hp_result;
+ wire [15:0] CLKS_PER_BIT;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
@@ -91,14 +92,14 @@
assign irq = 3'b000; // Unused
// Ouptut at LA bits [31:16]
- assign la_data_out[15:0] = 16'h0000;
- assign la_data_out[31:16] = (&la_oenb[31:16]) ? FPU_hp_result : 16'h0000;
- assign la_data_out[127:32] = {(127-BITS){1'b0}};
+ assign la_data_out[31:0] = 32'h00000000;
+ assign la_data_out[47:32] = (&la_oenb[47:32]) ? FPU_hp_result : 16'h0000;
+ assign la_data_out[127:48] = {79{1'b0}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
-
+ assign CLKS_PER_BIT = (la_oenb[31:16] == 16'h0000) ? la_data_in[31:16] : 16'd348;
// Initiation of TOP Module
FPU_FSM_TOP FPU_Bfloat16_Precision_Top (
@@ -109,6 +110,7 @@
.clk(clk),
.rst_l(rst),
.r_Rx_Serial(rx_i),
+ .CLKS_PER_BIT(CLKS_PER_BIT),
.FPU_hp_result(FPU_hp_result)
);
