1. b7fad20 [CI] update run-xor by manarabdelaty · 3 years ago
  2. 9b861b2 Add pattern to dv Makefile and drop obselete openlane wrapper dir by manarabdelaty · 3 years ago
  3. b07e408 Update README.md by Manar · 3 years ago
  4. 7b7b2f6 Update index.rst by Manar · 3 years ago
  5. 722391b Merge branch 'main' of github.com:efabless/caravel_user_project_analog into main by Tim Edwards · 3 years ago
  6. e982ef8 Update README.md by Manar · 3 years ago
  7. 9422266 Modified the wrapper to extend the analog pins out 4um like the rest of by Tim Edwards · 3 years ago
  8. 1f15094 [CI] Add github workflows for running the precheck/dv/caravan_build by manarabdelaty · 3 years ago
  9. a1553af Add docs dir by manarabdelaty · 3 years ago
  10. 892f0d2 Update Makefile by manarabdelaty · 3 years ago
  11. ff42add Update info.yaml to have the user_level_netlist point to the rtl netlist by manarabdelaty · 3 years ago
  12. 35111e9 Corrected ngspice testbenches for change in the name of the parameter by Tim Edwards · 3 years ago
  13. dba051e Modifications to the wrapper testbench schematic (not quite working by Tim Edwards · 3 years ago
  14. 5cc020d Added xschem schematic and symbol for the analog project wrapper, and a by Tim Edwards · 3 years ago
  15. a26abdd Redid the layout for the example analog project based on the updated by Tim Edwards · 3 years ago
  16. 60e4dcb Update Makefile by manarabdelaty · 3 years ago
  17. 8a1d5f2 Corrected the info.yaml file to point to the caravan.v file as the by Tim Edwards · 3 years ago
  18. 6bb2165 Added layout for the user_analog_project_wrapper example. by Tim Edwards · 3 years ago
  19. 5ea70cb Changed the schematics so that the resistor does not set a W by Tim Edwards · 3 years ago
  20. 796099e Corrected the schematic for the proper orientation of the topmost by Tim Edwards · 3 years ago
  21. dfc24ad Added xschem schematic of the POR and testbench simulations and results. by Tim Edwards · 3 years ago
  22. fb13001 Simple layout, unwired (needs modifications to the project wrapper) by Tim Edwards · 3 years ago
  23. a44a60b Preliminary work on the analog user project example. Added verilog RTL and by Tim Edwards · 3 years ago
  24. 6af7408 Initial commit by manarabdelaty · 3 years ago