Modified the xschem schematics so that the wrapper level correctly
represents the metal resistors that were added to the layout to
maintain all the pins on isolated nets.  The LVS with the xschem
netlist is now correct with the modified layout.  The verilog
netlist has not yet been updated.
7 files changed
tree: 686edc225872336525566264f1e19560d81e6419
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  11. Makefile

Caravel Analog User

License CI Caravan Build

:exclamation: Important Note

Please fill in your project documentation in this file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.