commit: 69bd32615214a41d3cddee598a4df9a5378f842b
[log] [tgz]
author: manarabdelaty <manarabdelatty@aucegypt.edu>
Wed Apr 07 15:58:03 2021 +0200
committer: manarabdelaty <manarabdelatty@aucegypt.edu>
Wed Apr 07 15:58:03 2021 +0200
tree: 90a66a6eeaa4458995c10d69d6017485c9c469b3
parent: a8b460780b87b0f651a2140baa05d912fa1c1a2a [diff]

Updated DV tests

verilog/dv/Makefile[Renamed from verilog/dv/user_proj_example/Makefile - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Renamed from verilog/dv/user_proj_example/io_ports/io_ports.c - diff]
verilog/dv/io_ports/io_ports_tb.v[Renamed from verilog/dv/user_proj_example/io_ports/io_ports_tb.v - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Renamed from verilog/dv/user_proj_example/la_test1/la_test1.c - diff]
verilog/dv/la_test1/la_test1_tb.v[Renamed from verilog/dv/user_proj_example/la_test1/la_test1_tb.v - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Renamed from verilog/dv/user_proj_example/la_test2/la_test2.c - diff]
verilog/dv/la_test2/la_test2_tb.v[Renamed from verilog/dv/user_proj_example/la_test2/la_test2_tb.v - diff]
verilog/dv/user_proj_example/README.md[Deleted - diff]
verilog/dv/user_proj_example/io_ports/Makefile[Deleted - diff]
verilog/dv/user_proj_example/la_test1/Makefile[Deleted - diff]
verilog/dv/user_proj_example/la_test2/Makefile[Deleted - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Copied from verilog/dv/user_proj_example/io_ports/io_ports_tb.v - diff]
verilog/rtl/uprj_netlists.v[Added - diff]

19 files changed

tree: 90a66a6eeaa4458995c10d69d6017485c9c469b3

README.md

Caravel Project Example