Removed old test cases that do not work for this user project
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/io_ports/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
deleted file mode 100644
index d204e4a..0000000
--- a/verilog/dv/io_ports/io_ports.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-/*
- IO Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
-
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spi_enable = 1;
- // reg_spimaster_cs = 0x10001;
- // reg_spimaster_control = 0x0801;
-
- // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // Configure lower 8-IOs as user output
- // Observe counter value in the testbench
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-}
-
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
deleted file mode 100644
index cf66d3f..0000000
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module io_ports_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
-
- assign mprj_io_0 = mprj_io[7:0];
- // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("io_ports.vcd");
- $dumpvars(0, io_ports_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- // Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
-
- `ifdef GL
- $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
- `else
- $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #300000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
- power1 <= 1'b1;
- #100;
- power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("io_ports.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/la_test1/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
deleted file mode 100644
index cad69d1..0000000
--- a/verilog/dv/la_test1/la_test1.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-// --------------------------------------------------------
-
-/*
- MPRJ Logic Analyzer Test:
- - Observes counter value through LA probes [31:0]
- - Sets counter initial value through LA probes [63:32]
- - Flags when counter value exceeds 500 through the management SoC gpio
- - Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
- int j;
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spi_enable = 1;
- // reg_spimaster_cs = 0x00000;
-
- // reg_spimaster_control = 0x0801;
-
- // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flad the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- // reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- // Now, apply the configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0x00000000;
-
- while (1) {
- if (reg_la0_data_in > 0x1F4) {
- reg_mprj_datal = 0xAB410000;
- break;
- }
- }
- print("\n");
- print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
- reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
deleted file mode 100644
index e0fff24..0000000
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module la_test1_tb;
- reg clock;
- reg RSTB;
- reg CSB;
-
- reg power1, power2;
-
- wire gpio;
- wire uart_tx;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- // assign mprj_io[3] = 1'b1;
-
- initial begin
- $dumpfile("la_test1.vcd");
- $dumpvars(0, la_test1_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (250) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test LA (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test LA (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB40);
- $display("LA Test 1 started");
- wait(checkbits == 16'hAB41);
- wait(checkbits == 16'hAB51);
- $display("LA Test 2 passed");
- #10000;
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- assign mprj_io[3] = 1; // Force CSB high.
- assign mprj_io[0] = 0; // Disable debug mode
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("la_test1.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/la_test2/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
deleted file mode 100644
index 25fad48..0000000
--- a/verilog/dv/la_test2/la_test2.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-/*
- MPRJ LA Test:
- - Sets counter clk through LA[64]
- - Sets counter rst through LA[65]
- - Observes count value for five clk cycle through LA[31:0]
-*/
-
-int clk = 0;
-int i;
-
-void main()
-{
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- reg_spi_enable = 1;
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
-
- // All GPIO pins are configured to be output
- // Used to flad the start/end of a test
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure All LA probes as inputs to the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- // Configure LA[64] LA[65] as outputs from the cpu
- reg_la2_oenb = reg_la2_iena = 0x00000003;
-
- // Set clk & reset to one
- reg_la2_data = 0x00000003;
-
- // DELAY
- for (i=0; i<5; i=i+1) {}
-
- // Toggle clk & de-assert reset
- for (i=0; i<11; i=i+1) {
- clk = !clk;
- reg_la2_data = 0x00000000 | clk;
- }
-
- // reg_mprj_datal = 0xAB610000;
-
- while (1){
- if (reg_la0_data_in >= 0x05) {
- reg_mprj_datal = 0xAB610000;
- break;
- }
-
- }
-
-}
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
deleted file mode 100644
index 6ef965d..0000000
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module la_test2_tb;
- reg clock;
- reg RSTB;
- reg CSB;
-
- reg power1, power2;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("la_test2.vcd");
- $dumpvars(0, la_test2_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (75) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB60);
- $display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
- wait(checkbits == 16'hAB61);
- $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- assign mprj_io[3] = 1; // Force CSB high.
- assign mprj_io[0] = 0; // Disable debug mode
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("la_test2.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(),
- .io3()
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/mprj_stimulus/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
deleted file mode 100644
index d049848..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-
-// --------------------------------------------------------
-
-void main()
-{
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flag the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- uint32_t testval;
-
- reg_mprj_datal = 0x00000000;
- reg_mprj_datah = 0x00000000;
-
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- /* TEST: Recast channels 35 to 32 to allow input to user project */
- /* This is done locally only: Do not run reg_mprj_xfer! */
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0x00000000;
-
- reg_mprj_datal = 0xAB410000;
- reg_mprj_datah = 0x00000000;
-
- // Test ability to force data on channel 37
- // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
-
- reg_mprj_datah = 0x0f0f0fc0;
- reg_mprj_datah = 0x00000000;
- reg_mprj_datah = 0x0f0f0fca;
- reg_mprj_datah = 0x0000000a;
- reg_mprj_datah = 0x0f0f0fc0;
- reg_mprj_datah = 0x00000000;
- reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000005;
-
- // Test ability to read back data generated by the user project
- // on the "monitored" outputs. Read from the lower 16 bits and
- // copy the value to the upper 16 bits.
-
- testval = reg_mprj_datal;
- reg_mprj_datal = (testval << 16);
- testval = reg_mprj_datal;
- reg_mprj_datal = (testval << 16);
-
- // Flag end of the test
- reg_mprj_datal = 0xAB510000;
-}
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
deleted file mode 100644
index 68addd0..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype wire
-
-`timescale 1 ns / 1 ps
-
-module mprj_stimulus_tb;
- // Signals declaration
- reg clock;
- reg RSTB;
- reg power1, power2;
- reg CSB;
- wire gpio;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
- wire [3:0] status;
-
- // Signals Assignment
- assign checkbits = mprj_io[31:16];
- assign status = mprj_io[35:32];
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("mprj_stimulus.vcd");
- $dumpvars(0, mprj_stimulus_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (100) begin
- repeat (1000) @(posedge clock);
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB40);
- $display("Monitor: mprj_stimulus test started");
- wait(status == 4'ha);
- wait(status == 4'h5);
-
- // Values reflect copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h1968 || checkbits == 16'h1969); // They're off because the difference between GL and RTL
- wait(checkbits == 16'h1DCD || checkbits == 16'h1DCE); // They're off because the difference between GL and RTL
-
- wait(checkbits == 16'hAB51);
- $display("Monitor: mprj_stimulus test Passed");
- #10000;
- $finish;
- end
-
- // Reset Operation
- initial begin
- CSB <= 1'b1;
- RSTB <= 1'b0;
- #2000;
- RSTB <= 1'b1; // Release reset
- #1000000;
- CSB <= 1'b0; // Stop driving CSB
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
-
- spiflash #(
- .FILENAME("mprj_stimulus.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
\ No newline at end of file
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
deleted file mode 100644
index 3fd0b56..0000000
--- a/verilog/dv/wb_port/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-
-
-PWDD := $(shell pwd)
-BLOCKS := $(shell basename $(PWDD))
-
-# ---- Include Partitioned Makefiles ----
-
-CONFIG = caravel_user_project
-
-
-include $(MCW_ROOT)/verilog/dv/make/env.makefile
-include $(MCW_ROOT)/verilog/dv/make/var.makefile
-include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-
-
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
deleted file mode 100644
index 4f59055..0000000
--- a/verilog/dv/wb_port/wb_port.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include <defs.h>
-#include <stub.c>
-
-/*
- Wishbone Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Checks counter value through the wishbone port
-*/
-
-void main()
-{
-
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spi_enable = 1;
- reg_wb_enable = 1;
- // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- reg_mprj_slave = 0x00002710;
- if (reg_mprj_slave == 0x2B3D) {
- reg_mprj_datal = 0xAB610000;
- }
-}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
deleted file mode 100644
index d5c2983..0000000
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-module wb_port_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
-
- assign mprj_io[3] = 1'b1;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("wb_port.vcd");
- $dumpvars(0, wb_port_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (70) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB60);
- $display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'hAB61);
- `ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
- `else
- $display("Monitor: Mega-Project WB (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #100000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("wb_port.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
\ No newline at end of file
