Before shrinking the main macro
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index a1fa371..852a64d 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,58 +1,4 @@
{
- "PDK" : "sky130A",
- "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
- "CARAVEL_ROOT" : "../../caravel",
- "CLOCK_NET" : "mprj.clk",
- "CLOCK_PERIOD" : "10",
- "CLOCK_PORT" : "user_clock2",
- "CLOCK_TREE_SYNTH" : "0",
- "DESIGN_NAME" : "user_project_wrapper",
- "DIE_AREA" : "0 0 2920 3520",
- "DIODE_INSERTION_STRATEGY" : "0",
- "EXTRA_GDS_FILES" : "../../gds/monitor.gds",
- "EXTRA_LEFS" : "../../lef/monitor.lef",
- "FILL_INSERTION" : "0",
- "FP_IO_HEXTEND" : "4.8",
- "FP_IO_HLENGTH" : "2.4",
- "FP_IO_HTHICKNESS_MULT" : "4",
- "FP_IO_VEXTEND" : "4.8",
- "FP_IO_VLENGTH" : "2.4",
- "FP_IO_VTHICKNESS_MULT" : "4",
- "FP_PDN_CHECK_NODES" : "0",
- "FP_PDN_CORE_RING" : "1",
- "FP_PDN_CORE_RING_HOFFSET" : "14",
- "FP_PDN_CORE_RING_HSPACING" : "1.7",
- "FP_PDN_CORE_RING_HWIDTH" : "3.1",
- "FP_PDN_CORE_RING_VOFFSET" : "14",
- "FP_PDN_CORE_RING_VSPACING" : "1.7",
- "FP_PDN_CORE_RING_VWIDTH" : "3.1",
- "FP_PDN_ENABLE_RAILS" : "0",
- "FP_PDN_HOFFSET" : "5",
- "FP_PDN_HPITCH" : "180",
- "FP_PDN_HSPACING" : "15.5",
- "FP_PDN_HWIDTH" : "3.1",
- "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1",
- "FP_PDN_VOFFSET" : "5",
- "FP_PDN_VPITCH" : "180",
- "FP_PDN_VSPACING" : "15.5",
- "FP_PDN_VWIDTH" : "3.1",
- "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg",
- "FP_SIZING" : "absolute",
- "GLB_RT_MAXLAYER" : "5",
- "GND_NETS" : "vssd1 vssd2 vssa1 vssa2",
- "MACRO_PLACEMENT_CFG" : "macro.cfg",
- "MAGIC_ZEROIZE_ORIGIN" : "0",
- "PL_RANDOM_GLB_PLACEMENT" : "1",
- "PL_RESIZER_BUFFER_INPUT_PORTS" : "0",
- "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0",
- "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0",
- "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0",
- "RUN_CVC" : "0",
- "SYNTH_TOP_LEVEL" : "1",
- "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS",
- "TAP_DECAP_INSERTION" : "0",
- "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2",
- "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],
- "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/monitor.v"]
+
}
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4b826d4..d651326 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -47,7 +47,11 @@
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vccd1 vssd1"
+ prj vccd1 vssd1 \
+ SRAM1 vccd1 vssd1 \
+ SRAM12 vccd1 vssd1"
+
+
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -55,19 +59,20 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project.v \
$script_dir/../../verilog/rtl/monitor.v \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/monitor.lef \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
+ $script_dir/../../lef/user_project.lef \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/monitor.gds \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
+ $script_dir/../../gds/user_project.gds \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
# set ::env(GLB_RT_MAXLAYER) 5
@@ -86,7 +91,36 @@
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-set ::env(FP_PDN_ENABLE_RAILS) 0
+set ::env(MACRO_PLACE_HALO) 3
+set ::env(MACRO_PLACE_CHANNEL) "100 100"
+
+set ::env(NO_GLB_RT_OBS) "li1 1600.00 1500.00 2280.0 1914.0, \
+ met1 1600.00 1500.00 2280.0 1914.0, \
+ met2 1600.00 1500.00 2280.0 1914.0, \
+ met3 1600.00 1500.00 2280.0 1914.0, \
+ met4 1600.00 1500.00 2280.0 1914.0, \
+ met5 0 0 2920 3520"
+
+
+set ::env(GLB_RT_ALLOW_CONGESTION) "1"
+
+#Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1.
+#1 = most reduction, 0 = least reduction
+set ::env(GLB_RT_LAYER_ADJUSTMENTS) 0.8,0.8,0.7,0,0,0
+
+# Not too many iterations
+set ::env(DRT_OPT_ITERS) 10
+
+# per layer adjustment
+# 0 -> 1: 1 means don't use the layer
+# l2 is met1
+
+# set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
+set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..09e64a5 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,10 @@
-mprj 1175 1690 N
+prj 1000 650 N
+
+# sky130_sram_1kbyte_1rw1w_32x256_8
+# 476 x 395
+SRAM1 400 100 N
+
+
+# sky130_sram_2kbyte_1rw1w_32x512_8
+# 680 x 414
+SRAM12 1600 1850 N
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index 284a97c..9f95ef2 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -1,3 +1,3 @@
// Caravel user project includes
$USER_PROJECT_VERILOG/gl/user_project_wrapper.v
-$USER_PROJECT_VERILOG/gl/user_proj_example.v
+$USER_PROJECT_VERILOG/gl/monitor.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f5047d5..3150275 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,3 @@
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/gl/monitor.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..1fdc7a9 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,11 @@
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/user_project.v
+-v $(USER_PROJECT_VERILOG)/rtl/monitor.v
+-v $(USER_PROJECT_VERILOG)/../thirdparty/bextdep/bextdep.v
+-v $(USER_PROJECT_VERILOG)/../thirdparty/bextdep/bextdep_pps.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v
+
+
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..b454fbc 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -20,9 +20,13 @@
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
+ `include "gl/monitor.v"
+ `include "gl/user_project.v"
`include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
+
`else
+ `include "user_project.v"
+ `include "monitor.v"
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
+
`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..d4edcb2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -28,6 +28,13 @@
*
*-------------------------------------------------------------
*/
+`define WMASK_SIZE 4
+`define ADDR_SIZE 16
+`define DATA_SIZE 32
+`define SELECT_SIZE 4
+`define MAX_CHIPS 2
+`define PORT_SIZE `ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+2
+`define TOTAL_SIZE `PORT_SIZE+`PORT_SIZE+`SELECT_SIZE
module user_project_wrapper #(
parameter BITS = 32
@@ -78,46 +85,147 @@
output [2:0] user_irq
);
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
+// Shared control/data to the SRAMs
+ wire [7:0] addrA0;
+ wire [31:0] dinA0;
+
+ wire webA;
+ wire [3:0] wmaskA;
+ wire [7:0] addrA1;
+ wire csbA0;
+ wire csbA1;
+
+
+ wire [8:0] addrB0;
+ wire [31:0] dinB0;
+
+ wire webB;
+ wire [3:0] wmaskB;
+ wire [8:0] addrB1;
+ wire csbB0;
+ wire csbB1;
-user_proj_example mprj (
+ wire [`DATA_SIZE-1:0] sram1_dout0;
+ wire [`DATA_SIZE-1:0] sram1_dout1;
+ wire [`DATA_SIZE-1:0] sram12_dout0;
+ wire [`DATA_SIZE-1:0] sram12_dout1;
+
+
+
+user_project prj (
`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
+ //vdda1, // User area 1 3.3V supply
+ //vdda2, // User area 2 3.3V supply
+ //vssa1, // User area 1 analog ground
+ //vssa2, // User area 2 analog ground
+ vccd1, // User area 1 1.8V supply
+ //vccd2, // User area 2 1.8v supply
+ vssd1, // User area 1 digital ground
+ //vssd2, // User area 2 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
+ // Wishbone Slave ports (WB MI A)
+ wb_clk_i,
+ wb_rst_i,
+ wbs_stb_i,
+ wbs_cyc_i,
+ wbs_we_i,
+ wbs_sel_i,
+ wbs_dat_i,
+ wbs_adr_i,
+ wbs_ack_o,
+ wbs_dat_o,
- // MGMT SoC Wishbone Slave
+ // Logic Analyzer Signals
+ la_data_in,
+ la_data_out,
+ la_oenb,
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+ // IOs
+ io_in,
+ io_out,
+ io_oeb,
- // Logic Analyzer
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ analog_io,
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
+ // Independent clock (on independent integer divider)
+ user_clock2,
- // IO Pads
+ // User maskable interrupt signals
+ user_irq,
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
+ // Shared control/data to the SRAMs
+ addrA0,
+ dinA0,
+
+ webA,
+ wmaskA,
+ addrA1,
+ csbA0,
+ csbA1,
+
+ addrB0,
+ dinB0,
+
+ webB,
+ wmaskB,
+ addrB1,
+ csbB0,
+ csbB1,
- // IRQ
- .irq(user_irq)
+ sram1_dout0,
+ sram1_dout1,
+ sram12_dout0,
+ sram12_dout1
+
);
+
+
+
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 ( wb_clk_i),
+ .csb0 (csbA0),
+ .web0 (webA),
+ .wmask0 (wmaskA),
+ .addr0 (addrA0),
+ .din0 (dinA0),
+ .dout0 (sram1_dout0),
+ .clk1 (wb_clk_i),
+ .csb1 (csbA1),
+ .addr1 (addrA1),
+ .dout1 (sram1_dout1)
+ );
+
+
+sky130_sram_2kbyte_1rw1r_32x512_8 SRAM12
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 ( wb_clk_i),
+ .csb0 (csbB0),
+ .web0 (webB),
+ .wmask0 (wmaskB),
+ .addr0 (addrB0),
+ .din0 (dinB0),
+ .dout0 (sram12_dout0),
+ .clk1 (wb_clk_i),
+ .csb1 (csbB1),
+ .addr1 (addrB1),
+ .dout1 (sram12_dout1)
+ );
+
endmodule // user_project_wrapper
-`default_nettype wire
+`default_nettype wire
\ No newline at end of file
