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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-022 / d49c4ed32edd86ac319ec59f55d0a6ffbd0fda4e
commitd49c4ed32edd86ac319ec59f55d0a6ffbd0fda4e[log] [tgz]
authorAng Li <angl@princeton.edu>Wed May 18 13:07:48 2022 -0400
committerAng Li <angl@princeton.edu>Wed May 18 13:07:48 2022 -0400
treeb4c30b7f965c8ee85c963afd8b34b3044d36a5e4
parent70e4c6925711cda6dbc141c3108ba2400b40d784 [diff]
[GDS/GL] PRGA top, li1 density ~ 0.49 > 0.4

* Applied patch https://github.com/RTimothyEdwards/open_pdks/pull/212/files
3 files changed
tree: b4c30b7f965c8ee85c963afd8b34b3044d36a5e4
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build

Design

We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile