commit	2eb0801d25577e5478ec7b7ddf14fefe03b33457	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Fri Nov 18 16:54:58 2022 -0800
committer	Jeff DiCorpo <jeffdi@efabless.com>	Fri Nov 18 16:54:58 2022 -0800
tree	68fb349fb7c06ec35ac0beefcc98c1589696affe
parent	b303a3291aeb16f2dd7ca7eb6595da734ad5d1d9 [diff]

final gds oasis

gds/tile_clb.gds[Deleted - diff]
gds/tile_clb.gds.gz[Added - diff]
mpw_precheck/logs/gds.info[Added - diff]
mpw_precheck/logs/git.info[Added - diff]
mpw_precheck/logs/klayout_beol_check.log[Added - diff]
mpw_precheck/logs/klayout_beol_check.total[Added - diff]
mpw_precheck/logs/klayout_feol_check.log[Added - diff]
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mpw_precheck/logs/klayout_met_min_ca_density_check.log[Added - diff]
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mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log[Added - diff]
mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total[Added - diff]
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mpw_precheck/logs/magic_drc_check.log[Added - diff]
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mpw_precheck/logs/pdks.info[Added - diff]
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mpw_precheck/logs/spdx_compliance_report.log[Added - diff]
mpw_precheck/logs/tools.info[Added - diff]
mpw_precheck/logs/xor_check.log[Added - diff]
mpw_precheck/logs/xor_check.total[Added - diff]
mpw_precheck/outputs/reports/klayout_beol_check.xml[Added - diff]
mpw_precheck/outputs/reports/klayout_feol_check.xml[Added - diff]
mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml[Added - diff]
mpw_precheck/outputs/reports/klayout_offgrid_check.xml[Added - diff]
mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml[Added - diff]
mpw_precheck/outputs/reports/klayout_zeroarea_check.xml[Added - diff]
mpw_precheck/outputs/reports/magic_drc_check.drc.report[Added - diff]
mpw_precheck/outputs/reports/magic_drc_check.rdb[Added - diff]
mpw_precheck/outputs/reports/magic_drc_check.tcl[Added - diff]
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mpw_precheck/outputs/reports/magic_drc_check.xml[Added - diff]
mpw_precheck/outputs/user_project_wrapper.filtered.v[Added - diff]
mpw_precheck/outputs/user_project_wrapper.magic.drc.mag[Added - diff]
mpw_precheck/outputs/user_project_wrapper.xor.gds[Added - diff]
mpw_precheck/outputs/user_project_wrapper_empty_erased.gds[Added - diff]
mpw_precheck/outputs/user_project_wrapper_erased.gds[Added - diff]
mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz[Added - diff]
signoff/.gitignore[Added - diff]
signoff/assigned_slot[Added - diff]
signoff/caravel_layout.png[Added - diff]
tapeout/logs/compose.log[Added - diff]
tapeout/logs/fill_final.log[Added - diff]
tapeout/logs/fill_initial.log[Added - diff]
tapeout/logs/fill_intermediate.log[Added - diff]
tapeout/logs/gds.info[Added - diff]
tapeout/logs/gen_gpio_defaults.log[Added - diff]
tapeout/logs/git.info[Added - diff]
tapeout/logs/git_clone.log[Added - diff]
tapeout/logs/klayout_beol.log[Added - diff]
tapeout/logs/klayout_feol.log[Added - diff]
tapeout/logs/klayout_fom_density.log[Added - diff]
tapeout/logs/klayout_gds2oas.log[Added - diff]
tapeout/logs/klayout_met_density.log[Added - diff]
tapeout/logs/klayout_missing_cells.log[Added - diff]
tapeout/logs/klayout_zero_area.log[Added - diff]
tapeout/logs/oasis.info[Added - diff]
tapeout/logs/pdks.info[Added - diff]
tapeout/logs/set_user_id.log[Added - diff]
tapeout/logs/ship_truck.log[Added - diff]
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tapeout/logs/uncompress.log[Added - diff]
tapeout/outputs/gds/caravel_000652b3.gds.gz.00.split[Added - diff]
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tapeout/outputs/klayout_beol_report.xml[Added - diff]
tapeout/outputs/klayout_beol_report.xml.summary[Added - diff]
tapeout/outputs/klayout_feol_report.xml[Added - diff]
tapeout/outputs/klayout_feol_report.xml.summary[Added - diff]
tapeout/outputs/klayout_fom_density_report.xml[Added - diff]
tapeout/outputs/klayout_fom_density_report.xml.summary[Added - diff]
tapeout/outputs/klayout_met_density_report.xml[Added - diff]
tapeout/outputs/klayout_met_density_report.xml.summary[Added - diff]
tapeout/outputs/mag/.magicrc[Added - diff]
tapeout/outputs/mag/caravel.mag[Added - diff]
tapeout/outputs/mag/gpio_defaults_block_0403.mag[Added - diff]
tapeout/outputs/mag/gpio_defaults_block_0801.mag[Added - diff]
tapeout/outputs/mag/gpio_defaults_block_1803.mag[Added - diff]
tapeout/outputs/mag/user_id_prog_zero.mag[Added - diff]
tapeout/outputs/mag/user_id_programming.mag[Added - diff]
tapeout/outputs/mag/user_id_textblock.mag[Added - diff]
tapeout/outputs/oas/caravel_000652b3.oas[Added - diff]
tapeout/outputs/verilog/gl/caravel.v[Added - diff]
tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v[Added - diff]
tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v[Added - diff]
tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v[Added - diff]
tapeout/outputs/verilog/gl/user_id_programming.v[Added - diff]
tapeout/outputs/verilog/rtl/caravel.v[Added - diff]

94 files changed

tree: 68fb349fb7c06ec35ac0beefcc98c1589696affe

README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
24-track routing channel with L1 tracks
Capable of implementing 16 out of 30 ISCAS'89 circuits

Design

We used a three level hierarchical design:

1x Caravel user project wrapper
- 1x PRGA top
  - 64x CLB tile