commit: 7b76767c5624c3146d276fd80e37eaf25d3aaa80
[log] [tgz]
author: duchungle <leduchung@gmail.com>
Tue Jun 07 14:08:00 2022 +0700
committer: duchungle <leduchung@gmail.com>
Tue Jun 07 14:08:00 2022 +0700
tree: 19fbc75bb4811573f83a48acd3e59792a058e9c1
parent: 3fafd5d2b47919680b0d2591b3c7c7bd21b6cebc [diff]

Update folders

verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/local-install.md[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/DCT_32P_TOP.v[Added - diff]
verilog/gl/DCT_V32P_TOP.v[Added - diff]
verilog/gl/aes_128.v[Added - diff]
verilog/gl/chacha.v[Added - diff]
verilog/gl/dct_v32p_wrapper.v[Added - diff]
verilog/gl/prince.v[Added - diff]
verilog/gl/prince_wrapper.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[Added - diff]
verilog/includes/includes.gl.caravel_user_project[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]

30 files changed

tree: 19fbc75bb4811573f83a48acd3e59792a058e9c1

README.md

Adaptive CORDIC-based 32-point DCT

:exclamation: Important Note

Please fill in your project documentation in this README.md file