Update nec_ir_receiver_tb.v
Improve testbench result display
diff --git a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
index b887cb8..03c558e 100644
--- a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
+++ b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
@@ -77,12 +77,20 @@
wait(checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
ir_drv.send_nec(cmd_addr, cmd_data);
- wait ((checkbits == 16'hAB61) && (addrbits == cmd_addr) && (databits == cmd_data));
- `ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
- `else
- $display("Monitor: Mega-Project WB (RTL) Passed");
- `endif
+ wait (checkbits == 16'hAB61);
+ if ((addrbits == cmd_addr) && (databits == cmd_data)) begin
+ `ifdef GL
+ $display("Monitor: Mega-Project WB (GL) Failed [0x%h -> 0x%h]", addrbits, databits);
+ `else
+ $display("Monitor: Mega-Project WB (RTL) Failed [0x%h -> 0x%h]", addrbits, databits);
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Mega-Project WB (GL) Passed");
+ `else
+ $display("Monitor: Mega-Project WB (RTL) Passed");
+ `endif
+ end
$finish;
end
