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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-010 / c0e0fff60ebe846eba4ec5c096f3714600ef4c5f
commitc0e0fff60ebe846eba4ec5c096f3714600ef4c5f[log] [tgz]
authorStaf Verhaegen <staf@fibraservi.eu>Wed Mar 23 10:43:13 2022 +0100
committerStaf Verhaegen <staf@fibraservi.eu>Wed Mar 23 10:43:13 2022 +0100
tree4170d0850681b5fa0f7b063a279ea2c54f7f9372
parentfbf90194a7b94c9cdde6de3a1435b67713155138 [diff]
Fix DRC errors and connect ESD clamp to SRAM vdd/vss
3 files changed
tree: 4170d0850681b5fa0f7b063a279ea2c54f7f9372
  1. .github/
  2. docs/
  3. doitcode/
  4. gds/
  5. netgen/
  6. verilog/
  7. xschem/
  8. caravel
  9. .gitignore
  10. dodo.py
  11. LICENSE
  12. Makefile
  13. README.md
  14. user_analog_project_wrapper.png
README.md

PDKMaster based memory compiler test chip

TBD

Source

The top level is fully generated from python code in the doitcode subdirectory. pydoit is used to generate the desig with the provided dodo.py file in the top directory. The code depends on some external modules that are assumed to be installed:

  • PDKMaster: python framework (under heavy development) to ease generation of circuits and corresponding DRC compliant layout. This based on a description of a technology with python souce code to allow easy porting to different technologies.
  • c4m-flexcell: a (currently minimal) standard cell library based on PDKMaster
  • c4m-flexmem: the source for the memory compiler
  • c4m-pdk-sky130: the source for the PDKMaster based PDK for the Sky130 technology.

License

The resulting GDS files is released under the LGPL 2.1 or later license. Some of the source code to generate the GDS is under the GPL 2.0 or later license.