| commit | 0f93045e465813987ab7316a51e955ab483481a7 | [log] [tgz] |
|---|---|---|
| author | Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal> | Tue Feb 22 09:18:53 2022 -0800 |
| committer | Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal> | Tue Feb 22 09:18:53 2022 -0800 |
| tree | a6b08e34ece87b95e5ace30a863b3f3f5d0b9ba7 | |
| parent | d99dcd5f8a7d6397ae243020a7f143fdc7ad21d9 [diff] [blame] |
added includes directory
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project new file mode 100644 index 0000000..31ab09b --- /dev/null +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,5 @@ +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v + + \ No newline at end of file