- e249385 qspim update by dineshannayya · 2 years, 5 months ago
- 5ca3ffc moved riscv core fom syntacore to yifive/ycr1 by dineshannayya · 2 years, 5 months ago
- 26ff4d8 riscv synth update by dineshannayya · 2 years, 5 months ago
- 94ec2c4 clean up riscv core sim setup by dineshannayya · 2 years, 5 months ago
- cdbfaab move qspim rtl to git repo by dineshannayya · 2 years, 5 months ago
- 259d11f qspim cleanup by dineshannayya · 2 years, 5 months ago
- 12ceeeb qspim is not link to git repo by dineshannayya · 2 years, 5 months ago
- 913984b qspim cleanup by dineshannayya · 2 years, 5 months ago
- 4f0e076 Riscv Regression and Interrupt cleanup by dineshannayya · 2 years, 5 months ago
- 71784d5 riscv compliance test cleanup by dineshannayya · 2 years, 5 months ago
- 3084fb7 tcm memory access bug fix and riscv regression update by dineshannayya · 2 years, 5 months ago
- ef03218 soft reset added uses la[0] pin by dineshannayya · 2 years, 6 months ago
- 27778af uart master interface added by dineshannayya · 2 years, 6 months ago
- f721bdb block diagram and doc update by dineshannayya · 2 years, 6 months ago
- 091855f MPW-4 submission with 8KB WishBone and 4KB TCM Memory by dineshannayya · 2 years, 6 months ago
- 5f1a056 add new caravel by dineshannayya · 2 years, 6 months ago
- 6427eb3 removed older version of caravel by dineshannayya · 2 years, 6 months ago
- 00a01d8 met5 density fix by dineshannayya · 2 years, 6 months ago
- 8af216d metal denisty fix for met5 by dineshannayya · 2 years, 6 months ago
- 9b054e5 pdn drc fix by dineshannayya · 2 years, 6 months ago
- 25be930 timing clean, syntacore gds link fix, 8KB SRAM added by dineshannayya · 2 years, 6 months ago
- bfcf072 area clean up by dineshannayya · 2 years, 6 months ago
- adbcb41 docker images hardcoded and pdk path local docker path/opt/pdk by dineshannayya · 2 years, 7 months ago
- 8cc93f7 full chip sta folder created by dineshannayya · 2 years, 7 months ago
- a47e71e Timing clean-up + Signature Register Added in PinMux by dineshannayya · 2 years, 7 months ago
- be39a45 wb host output timing fix by dineshannayya · 2 years, 7 months ago
- 31a8a64 syntacore ip area reduction by dineshannayya · 2 years, 7 months ago
- dc63d70 IP area optimization by dineshannayya · 2 years, 7 months ago
- 2923b11 wb_host regenerated by dineshannayya · 2 years, 7 months ago
- b4ef1e2 clk_ctl bug fix in wb_host by dineshannayya · 2 years, 7 months ago
- 85fa860 wbhost reset bug fix and clocking cleanup by dineshannayya · 2 years, 7 months ago
- 0a11a5f typical timing closed tape-in database by dineshannayya · 2 years, 7 months ago
- 21632be Adding clock skew inside the subIO + Precheck cleanup by dineshannayya · 2 years, 7 months ago
- 0e58c46 temporary deleting of riscv complaint submodule to pass the efabless precheck by dineshannayya · 2 years, 7 months ago
- 2e52dfd golden git module update by dineshannayya · 2 years, 7 months ago
- 2b14f54 sram blockage for magic drc fix by dineshannayya · 2 years, 7 months ago
- eee3c78 directory clean up by dineshannayya · 2 years, 8 months ago
- aea55d2 Rebase on caravel by dineshannayya · 2 years, 8 months ago
- d3e5c07 caraval rebase to mpw-3 tag by dineshannayya · 2 years, 8 months ago
- a0c4d75 removed caravel by dineshannayya · 2 years, 8 months ago
- 72f3073 rebase the caravel project by dineshannayya · 2 years, 8 months ago
- b878264 rebase caravel by dineshannayya · 2 years, 8 months ago
- b611e71 Basic Verification and Physical design cleanup by dineshannayya · 2 years, 8 months ago
- 0490d84 Block digram update by dineshannayya · 2 years, 8 months ago
- e4794a9 Document and Floor planning image update by dineshannayya · 2 years, 8 months ago
- db72072 caravel update by dineshannayya · 2 years, 8 months ago
- 1a0b518 caravel repo added by dineshannayya · 2 years, 9 months ago
- 72db49a Removed older version of caravel by dineshannayya · 2 years, 9 months ago
- beda1b5 drc clean project ver1.0 by dineshannayya · 2 years, 9 months ago
- 7a15cfe test bench clean-up by dineshannayya · 2 years, 9 months ago
- 5d4c4eb first version of riscduino with sdram removed, pinmux and sar_adc added by dineshannayya · 2 years, 9 months ago
- f7a2660 git module by dineshannayya · 2 years, 9 months ago
- c861bd7 caravel lite by dineshannayya · 2 years, 9 months ago
- 6aa879d comit gitmodule by dineshannayya · 2 years, 9 months ago
- f05de65 doc update by dineshannayya · 2 years, 9 months ago
- 3d4372b documentation update by dineshannayya · 2 years, 9 months ago
- 749c2dd MPW-3 caravel link updated by dineshannayya · 2 years, 9 months ago
- 2b4e8bb Readme and caravel link deleted by dineshannayya · 2 years, 9 months ago
- 259e0b6 riscv regression with coremark test passing by dineshannayya · 2 years, 10 months ago
- 5b1c9df sdram ctrl bug fix tRAS violation, changed the define to ASIC by dineshannayya · 2 years, 10 months ago
- 0013fc8 timer_irq connectivity bug fix by dineshannayya · 2 years, 10 months ago
- f54f9d1 riscv_regress simulation works through docker by dineshannayya · 2 years, 10 months ago
- 09ebd88 riscv regression suite, riscv_isa and riscv_compliance test integrated by dineshannayya · 2 years, 10 months ago
- 32dc94d Riscv Unalign access fix and sdr ctrl 8 bit address mode fix by dineshannayya · 2 years, 10 months ago
- 054bd1c modelsim compile cleanup by dineshannayya · 2 years, 10 months ago
- 70876fa synta core cleanup by dineshannayya · 2 years, 10 months ago
- eb233e6 pdk file are copied /opt/pdk inside the docker by dineshannayya · 2 years, 10 months ago
- 638dadf synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 2 years, 10 months ago
- d2f7180 antenna fix by dineshannayya · 2 years, 10 months ago
- 40fda88 openlane link pointing to dineshannaya/openlane by dineshannayya · 2 years, 10 months ago
- 063811b efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 2 years, 10 months ago
- a1366ef efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 2 years, 10 months ago
- 6b879de block diagram updated by dineshannayya · 2 years, 11 months ago
- 1224faa SPDX Non compliant text fix by dineshannayya · 2 years, 11 months ago
- c7e6bf6 usb1 host is integrated by dineshannayya · 2 years, 11 months ago
- 9500aca Register Map detail updated by dineshannayya · 2 years, 11 months ago
- 641f649 Register Map updated in Readme by dineshannayya · 2 years, 11 months ago
- 952cc0a README updated with i2c info by dineshannayya · 2 years, 11 months ago
- e2d5787 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 2 years, 11 months ago
- b970b3e i2cm integrated and share same uart io by dineshannayya · 2 years, 11 months ago
- b9ee857 spi master with qddr mode support added by dineshannayya · 2 years, 11 months ago
- dc214bb syntacore timing fix by dineshannayya · 2 years, 11 months ago
- a999a4e syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 2 years, 11 months ago
- d454c61 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years ago
- c2b8484 SPI Preftech logic added by dineshannayya · 3 years ago
- 7880d7e Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years ago
- 13a7e86 clk_skew power hook fix by dineshannayya · 3 years ago
- ad9b197 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years ago
- 2b3f3c6 full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years ago
- bd118ef sdram clock connectivity correction at u_skew hookup by dineshannayya · 3 years ago
- 44bb954 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years ago
- 2c7c99f Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years ago
- 8e6b8de Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years ago
- f076769 first version of pre-check clean database by dineshannayya · 3 years ago
- ab52204 Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years ago
- b136433 precheck cleanup by dineshannayya · 3 years ago
- b3be9ba License Text Added by dineshannayya · 3 years ago
- 5c21850 DRC clean user_project_wrapper by dineshannayya · 3 years ago
- 51f4af2 updated database by dineshannayya · 3 years ago
- 6f278d4 wb_host rtl and openlane setup added by dineshannayya · 3 years ago
