commit	e7feb5fa60ea7090f1bb45d4ec1011e4c2560b9b	[log] [tgz]
author	dinesha <dineshannayya@users.noreply.github.com>	Mon Jun 07 15:59:05 2021 +0000
committer	dinesha <dineshannayya@users.noreply.github.com>	Mon Jun 07 15:59:05 2021 +0000
tree	69118d826770318e31ca93ef1617aa3b46f8ccde
parent	66e9188e0610d874af3c5f6974addd4477e63d65 [diff]

syntacore directory update

verilog/rtl/lib/sync_fifo.sv[Added - diff]
verilog/rtl/lib/wb_interface.v[diff]
verilog/rtl/syntacore/scr1/LICENSE[Added - diff]
verilog/rtl/syntacore/scr1/Makefile[Added - diff]
verilog/rtl/syntacore/scr1/README.md[Added - diff]
verilog/rtl/syntacore/scr1/docs/img/scr1_cluster.svg[Added - diff]
verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf[Added - diff]
verilog/rtl/syntacore/scr1/docs/scr1_um.pdf[Added - diff]
verilog/rtl/syntacore/scr1/src/ahb_top.files[Added - diff]
verilog/rtl/syntacore/scr1/src/axi_top.files[Added - diff]
verilog/rtl/syntacore/scr1/src/core.files[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh[Added - diff]
verilog/rtl/syntacore/scr1/src/run_modemsim[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv[Added - diff]
verilog/rtl/syntacore/scr1/src/wb_top.files[Added - diff]
verilog/rtl/syntacore/scr1/synth/Makefile[Added - diff]
verilog/rtl/syntacore/scr1/synth/run_synth[Added - diff]
verilog/rtl/syntacore/scr1/synth/synth.tcl[Added - diff]

65 files changed

tree: 69118d826770318e31ca93ef1617aa3b46f8ccde

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.