document update
diff --git a/README.md b/README.md
index 602f95e..274f0c4 100644
--- a/README.md
+++ b/README.md
@@ -47,17 +47,16 @@
# Key features
```
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
- * industry-grade and silicon-proven Open-Source RISC-V core from syntacore
- * 2KB SRAM for TCM Memory
- * 2KB SRAM for Instruction cache
- * 2KB SRAM for Data cache
+ * 32 Bit RISC-V core
+ * 2KB SRAM for instruction cache
+ * 2KB SRAM for data cache
+ * 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master
* UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* UART Master
* Simple SPI Master
- * MBIST controller for 8KB Program memory
* 6 Channel ADC (in Progress)
* 6 PWM
* Pin Compatbible to arudino uno
@@ -129,9 +128,21 @@
## RISC V Core
-Riscduino SOC Integrated Syntacore SCR1 Open-source RISV-V compatible MCU-class core.
-It is industry-grade and silicon-proven IP. Git link: https://github.com/syntacore/scr1
-
+Riscduino SOC Integrated 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from
+Syntacore SCR1 (https://github.com/syntacore/scr1)
+### RISC V core customization for Riscduino SOC
+Following Design changes are done on the basic version of syntacore RISC core
+```
+ * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
+ * Instruction Request are changed from Single word to 4 Word Burst
+ * Multiplication and Divsion are changed to improve timing
+ * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
+ * 2KB instruction cache
+ * 2KB data cache
+ * Additional router are added towards instruction cache
+ * Additional router are added towards data cache
+ * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface
+```
### Block Diagram
<table>
<tr>
@@ -143,19 +154,14 @@
```
* RV32I or RV32E ISA base + optional RVM and RVC standard extensions
* Machine privilege mode only
- * 2 to 4 stage pipeline
+ * 2 to 5 stage pipeline
+ * 2KB icache
+ * 2KB dcache
* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
* Optional RISC-V Debug subsystem with JTAG interface
- * 2KB on-chip Tightly-Coupled Memory (TCM Memory)
- * 2KB on-chip instruction cache
- * 2KB on-chip data cache
+ * Optional on-chip Tightly-Coupled Memory
```
-### RISC V core customization Riscduino SOC
-
-
-* **Update**: Modified some of the system verilog syntax to basic verilog syntax to compile/synthesis in open source tool like simulator (iverilog) and synthesis (yosys).
-* **Modification**: Modified the AXI/AHB interface to wishbone interface towards instruction & data memory interface
# SOC Memory Map
diff --git a/docs/source/_static/Riscduino_Soc.png b/docs/source/_static/Riscduino_Soc.png
index c981979..94f5f0f 100644
--- a/docs/source/_static/Riscduino_Soc.png
+++ b/docs/source/_static/Riscduino_Soc.png
Binary files differ
