syntacore_scr1 directory removal
diff --git a/verilog/rtl/syntacore_scr1/LICENSE b/verilog/rtl/syntacore_scr1/LICENSE
deleted file mode 100644
index 0d753ad..0000000
--- a/verilog/rtl/syntacore_scr1/LICENSE
+++ /dev/null
@@ -1,23 +0,0 @@
-# Solderpad Hardware Licence Version 2.0
-
-This licence (the “Licence”) operates as a wraparound licence to the Apache License Version 2.0 (the “Apache License”) and grants to You the rights, and imposes the obligations, set out in the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following extensions. It must be read in conjunction with the Apache License. Section 1 below modifies definitions in the Apache License, and section 2 below replaces sections 2 of the Apache License. You may, at your option, choose to treat any Work released under this License as released under the Apache License (thus ignoring all sections written below entirely). Words in italics indicate changes rom the Apache License, but are indicative and not to be taken into account in interpretation.
-
-1. The definitions set out in the Apache License are modified as follows:
-
-Copyright any reference to ‘copyright’ (whether capitalised or not) includes ‘Rights’ (as defined below).
-
-Contribution also includes any design, as well as any work of authorship.
-
-Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the interfaces of the Work and Derivative Works thereof.
-
-Object form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works).
-
-Rights means copyright and any similar right including design right (whether registered or unregistered), semiconductor topography (mask) rights and database rights (but excluding Patents and Trademarks).
-
-Source form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files.
-
-Work also includes a design or work of authorship, whether in Source form or other Object form.
-
-2. Grant of Licence
-
-2.1 Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist.
diff --git a/verilog/rtl/syntacore_scr1/Makefile b/verilog/rtl/syntacore_scr1/Makefile
deleted file mode 100644
index adb33c5..0000000
--- a/verilog/rtl/syntacore_scr1/Makefile
+++ /dev/null
@@ -1,293 +0,0 @@
-#------------------------------------------------------------------------------
-# Makefile for SCR1
-#------------------------------------------------------------------------------
-
-# PARAMETERS
-
-# CFG = <MAX, BASE, MIN, CUSTOM>
-# BUS = <AHB, AXI>
-
-export CFG ?= MAX
-export BUS ?= AHB
-
-ifeq ($(CFG), MAX)
-# Predefined configuration SCR1_CFG_RV32IMC_MAX
- override ARCH := IMC
- override VECT_IRQ := 1
- override IPIC := 1
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32IMC_MAX
-else
- ifeq ($(CFG), BASE)
- # Predefined configuration SCR1_CFG_RV32IC_BASE
- override ARCH := IC
- override VECT_IRQ := 1
- override IPIC := 1
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32IC_BASE
- else
- ifeq ($(CFG), MIN)
- # Predefined configuration SCR1_CFG_RV32EC_MIN
- override ARCH := EC
- override VECT_IRQ := 0
- override IPIC := 0
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32EC_MIN
- else
- # CUSTOM configuration. Parameters can be overwritten
- # These options are for compiling tests only. Set the corresponding RTL parameters manually in the file scr1_arch_description.svh.
- # ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>
- # VECT_IRQ = <0, 1>
- # IPIC = <0, 1>
- # TCM = <0, 1>
- ARCH ?= IMC
- VECT_IRQ ?= 0
- IPIC ?= 0
- TCM ?= 0
- SIM_CFG_DEF = SCR1_CFG_$(CFG)
- endif
- endif
-endif
-
-# export all overrided variables
-export ARCH
-export VECT_IRQ
-export IPIC
-export TCM
-export SIM_CFG_DEF
-
-ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
-BUS_lowercase = $(shell echo $(BUS) | tr A-Z a-z)
-
-ifeq ($(ARCH_lowercase),)
- ARCH_tmp = imc
-else
- ifneq (,$(findstring e,$(ARCH_lowercase)))
- ARCH_tmp += e
- EXT_CFLAGS += -D__RVE_EXT
- else
- ARCH_tmp += i
- endif
- ifneq (,$(findstring m,$(ARCH_lowercase)))
- ARCH_tmp := $(ARCH_tmp)m
- endif
- ifneq (,$(findstring c,$(ARCH_lowercase)))
- ARCH_tmp := $(ARCH_tmp)c
- EXT_CFLAGS += -D__RVC_EXT
- endif
-endif
-
-override ARCH=$(ARCH_tmp)
-
-# Use this parameter to enable tracelog
-TRACE ?= 0
-
-ifeq ($(TRACE), 1)
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_EN
-else
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_DIS
-endif
-
-
-# Use this parameter to pass additional options for simulation build command
-SIM_BUILD_OPTS ?=
-
-# Use this parameter to set the list of tests to run
-# TARGETS = <riscv_isa, riscv_compliance, coremark, dhrystone21, hello, isr_sample>
-export TARGETS :=
-
-
-export ABI ?= ilp32
-# Testbench memory delay patterns\
- (FFFFFFFF - no delay, 00000000 - random delay, 00000001 - max delay)
-imem_pattern ?= FFFFFFFF
-dmem_pattern ?= FFFFFFFF
-
-VCS_OPTS ?=
-MODELSIM_OPTS ?=
-NCSIM_OPTS ?=
-VERILATOR_OPTS ?=
-
-current_goal := $(MAKECMDGOALS:run_%=%)
-ifeq ($(current_goal),)
- current_goal := verilator
-endif
-
-# Paths
-export root_dir := $(shell pwd)
-export tst_dir := $(root_dir)/sim/tests
-export inc_dir := $(tst_dir)/common
-export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE)
-
-test_results := $(bld_dir)/test_results.txt
-test_info := $(bld_dir)/test_info
-sim_results := $(bld_dir)/sim_results.txt
-
-todo_list := $(bld_dir)/todo.txt
-# Environment
-export CROSS_PREFIX ?= riscv64-unknown-elf-
-export RISCV_GCC ?= $(CROSS_PREFIX)gcc
-export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
-export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
-export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
-#--
-ifneq (,$(findstring axi,$(BUS_lowercase)))
-export rtl_top_files := axi_top.files
-export rtl_tb_files := axi_tb.files
-export top_module := scr1_top_tb_axi
-else
-export rtl_top_files := ahb_top.files
-export rtl_tb_files := ahb_tb.files
-export top_module := scr1_top_tb_ahb
-endif
-
-ifneq (,$(findstring e,$(ARCH_lowercase)))
-# Tests can be compiled for RVE only if gcc version 8.0.0 or higher
- GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
- ifeq "$(GCCVERSIONGT7)" "1"
- ABI := ilp32e
- endif
-endif
-
-#--
-ifeq (,$(findstring e,$(ARCH_lowercase)))
-# These tests cannot be compiled for RVE
-
- # Comment this target if you don't want to run the riscv_isa
- TARGETS += riscv_isa
-
- # Comment this target if you don't want to run the riscv_compliance
- TARGETS += riscv_compliance
-endif
-
-# Comment this target if you don't want to run the isr_sample
-TARGETS += isr_sample
-
-# Comment this target if you don't want to run the coremark
-TARGETS += coremark
-
-# Comment this target if you don't want to run the dhrystone
-TARGETS += dhrystone21
-
-# Comment this target if you don't want to run the hello test
-TARGETS += hello
-
-# Targets
-.PHONY: tests run_modelsim run_vcs run_ncsim run_verilator run_verilator_wf
-
-default: clean_test_list run_verilator
-
-clean_test_list:
- rm -f $(test_info)
-
-echo_out: tests
- @echo " Test | build | simulation " ;
- @echo "$$(cat $(test_results))"
-
-tests: $(TARGETS)
-
-$(test_info): clean_hex tests
- cd $(bld_dir)
-
-isr_sample: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/isr_sample ARCH=$(ARCH) IPIC=$(IPIC) VECT_IRQ=$(VECT_IRQ)
-
-dhrystone21: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-coremark: | $(bld_dir)
- -$(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-riscv_isa: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/riscv_isa ARCH=$(ARCH)
-
-riscv_compliance: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/riscv_compliance ARCH=$(ARCH)
-
-hello: | $(bld_dir)
- -$(MAKE) -C $(tst_dir)/hello EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-clean_hex: | $(bld_dir)
- $(RM) $(bld_dir)/*.hex
-
-$(bld_dir):
- mkdir -p $(bld_dir)
-
-run_vcs: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_vcs SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- $(bld_dir)/simv -V \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VCS_OPTS) | tee $(sim_results) ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-run_modelsim: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_modelsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
- printf "" > $(test_results); \
- cd $(bld_dir); \
- vsim -c -do "run -all" +nowarn3691 \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- work.$(top_module) \
- $(MODELSIM_OPTS) | tee $(sim_results) ;\
- printf "Simulation performed on $$(vsim -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_ncsim: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_ncsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- irun \
- -R \
- -64bit \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(NCSIM_OPTS) | tee $(sim_results) ;\
- printf "Simulation performed on $$(irun -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_verilator: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_verilator SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- echo $(top_module) | tee $(sim_results); \
- $(bld_dir)/verilator/V$(top_module) \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VERILATOR_OPTS) | tee -a $(sim_results) ;\
- printf "Simulation performed on $$(verilator -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_verilator_wf: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_verilator_wf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- echo $(top_module) | tee $(sim_results); \
- $(bld_dir)/verilator/V$(top_module) \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VERILATOR_OPTS) | tee -a $(sim_results) ;\
- printf "Simulation performed on $$(verilator -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-clean:
- $(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 clean
- $(MAKE) -C $(tst_dir)/riscv_isa clean
- $(MAKE) -C $(tst_dir)/riscv_compliance clean
- $(RM) -R $(root_dir)/build/*
- $(RM) $(test_info)
\ No newline at end of file
diff --git a/verilog/rtl/syntacore_scr1/README.md b/verilog/rtl/syntacore_scr1/README.md
deleted file mode 100644
index 0fb6648..0000000
--- a/verilog/rtl/syntacore_scr1/README.md
+++ /dev/null
@@ -1,197 +0,0 @@
-# SCR1 RISC-V Core
-
-SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore. It is industry-grade and silicon-proven (including full-wafer production), works out of the box in all major EDA flows and Verilator, and comes with extensive collateral and documentation.
-
-
-
-## Key features
-
-* Open sourced under SHL-license (see LICENSE file) - unrestricted commercial use allowed
-* RV32I or RV32E ISA base + optional RVM and RVC standard extensions
-* Machine privilege mode only
-* 2 to 4 stage pipeline
-* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
-* Optional RISC-V Debug subsystem with JTAG interface
-* Optional on-chip Tightly-Coupled Memory
-* 32-bit AXI4/AHB-Lite external interface
-* Written in SystemVerilog
-* Optimized for area and power
-* 3 predefined recommended configurations
-* A number of fine-tuning options for custom configuration
-* Verification suite provided
-* Extensive documentation
-
-For more information on core architecture, see [SCR1 External Architecture Specification](https://github.com/syntacore/scr1/blob/master/docs/scr1_eas.pdf).
-
-For more information on project usage, see [SCR1 User Manual](https://github.com/syntacore/scr1/blob/master/docs/scr1_um.pdf).
-
-## Repository contents
-
-|Folder | Description
-|------ | -----------
-|**dependencies** | **Dependent submodules**
-|├─ riscv-tests | Common source files for RISC-V ISA tests
-|├─ riscv-compliance | Common source files for RISC-V Compliance tests
-|└─ coremark | Common source files for EEMBC's CoreMark® benchmark
-|**docs** | **SCR1 documentation**
-|├─ scr1_eas.pdf | SCR1 External Architecture Specification
-|└─ scr1_um.pdf | SCR1 User Manual
-|**sim** | **Tests and scripts for simulation**
-|├─ tests/common | Common source files for tests
-|├─ tests/riscv_isa | RISC-V ISA tests platform specific source files
-|├─ tests/riscv_compliance | RISC-V Compliance platform specific source files
-|├─ tests/benchmarks/dhrystone21 | Dhrystone 2.1 benchmark source files
-|├─ tests/benchmarks/coremark | EEMBC's CoreMark® benchmark platform specific source files
-|├─ tests/isr_sample | Sample program "Interrupt Service Routine"
-|├─ tests/hello | Sample program "Hello"
-|└─ verilator_wrap | Wrappers for Verilator simulation
-|**src** | **SCR1 RTL source and testbench files**
-|├─ includes | Header files
-|├─ core | Core top source files
-|├─ top | Cluster source files
-|└─ tb | Testbench files
-
-## SCR1 source file lists
-
-SCR1 source file lists of SCR1 can be found in [./src](https://github.com/syntacore/scr1/tree/master/src):
-
-* **core.files** - all synthesized file sources of the SCR1 core
-* **ahb_top.files** - synthesized file sources of AHB cluster
-* **axi_top.files** - synthesized file sources of AXI cluster
-* **ahb_tb.files** - testbench file sources for AHB cluster (for simulation only)
-* **axi_tb.files** - testbench file sources for AXI cluster (for simulation only)
-
-Library with header files to include is [./src/includes/](https://github.com/syntacore/scr1/tree/master/src/includes)
-
-## Simulation quick start guide
-
-The project contains testbenches, test sources and scripts to quickly start the SCR1 simulation. Before starting the simulation, make sure you have:
-
-* installed RISC-V GCC toolchain,
-* installed one of the supported simulators,
-* initialized submodules with test sources.
-
-### Requirements
-
-#### Operating system
-
-GCC toolchain and make-scripts are supported by most popular Linux-like operating systems.
-
-To run from Windows you can use an additional compatibility layer, such as WSL or Cygwin.
-
-#### RISC-V GCC toolchain
-
-RISC-V GCC toolchain is required to compile the software. You can use pre-built binaries or build the toolchain from scratch.
-
-##### Using pre-built binary tools
-
-Pre-built RISC-V GCC toolchain with support for all SCR1 architectural configurations is available for download from http://syntacore.com/page/products/sw-tools.
-
-1. Download the archive for your platform.
-2. Extract the archive to preferred directory `<GCC_INSTALL_PATH>`.
-3. Add the `<GCC_INSTALL_PATH>/bin` folder to the $PATH environment variable:
-```
- export PATH=<GCC_INSTALL_PATH>/bin:$PATH
-```
-
-##### Building tools from source
-
-You can build the RISC-V GCC toolchain from sources, stored in official repo https://github.com/riscv/riscv-gnu-toolchain
-
-Instructions on how to prepare and build the toolchain can be found on https://github.com/riscv/riscv-gnu-toolchain/blob/master/README.md
-
-We recommend using the multilib compiler. Please note that RV32IC, RV32E, RV32EM, RV32EMC, RV32EC architectural configurations are not included in the compiler by default. If you plan to use them, you will need to include the appropriate libraries by yourself before building.
-
-After the building, be sure to add the `<GCC_INSTALL_PATH>/bin` folder to the $PATH environment variable
-
-
-#### HDL simulators
-
-Currently supported simulators:
-
-* Verilator (last verified version: v4.102)
-* Intel ModelSim (last verified version: INTEL FPGA STARTER EDITION vsim 2020.1_3)
-* Mentor Graphics ModelSim (last verified version: Modelsim PE Student Edition 10.4a)
-* Synopsys VCS (last verified version: vcs-mx_vL-2016.06)
-* Cadence NCSim
-
-Please note that RTL simulator executables should be in your $PATH variable.
-
-#### Tests preparation
-
-The simulation package includes the following tests:
-
-* **hello** - "Hello" sample program
-* **isr_sample** - "Interrupt Service Routine" sample program
-* **riscv_isa** - RISC-V ISA tests (submodule)
-* **riscv_compliance** - RISC-V Compliance tests (submodule)
-* **dhrystone21** - Dhrystone 2.1 benchmark
-* **coremark** - EEMBC's CoreMark® benchmark (submodule)
-
-After the main SCR1 repository has been cloned execute the following command:
-```
- git submodule update --init --recursive
-```
-
-This command will initialized submodules with test sources.
-
-### Running simulation
-
-To build RTL, compile and run tests from the repo root folder you have to call Makefile.
-By default, you may simply call Makefile without any parameters:
-``` sh
- make
-```
-
-In this case simulation will run on Verilator with following parameters: `CFG=MAX BUS=AHB TRACE=0 TARGETS="hello isr_sample riscv_isa riscv_compliance dhrystone21 coremark"`.
-
-Makefile supports:
-
-* choice of simulator - `run_<SIMULATOR> = <run_vcs, run_modelsim, run_ncsim, run_verilator, run_verilator_wf>`
-* selection of external interface - `BUS = <AHB, AXI>`,
-* configuration setup - `CFG = <MAX, BASE, MIN, CUSTOM>`,
-* parameters for CUSTOM configuration - `ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>, VECT_IRQ = <0, 1>, IPIC = <0, 1>, TCM = <0, 1>`
-* tests subset to run - `TARGETS = <hello, isr_sample, riscv_isa, riscv_compliance, dhrystone21, coremark>`
-* enabling tracelog - `TRACE = <0, 1>`
-* and any additional options to pass to the simulator - `SIM_BUILD_OPTS`.
-
-Examples:
-``` sh
- make run_verilator_wf CFG=MAX BUS=AXI TARGETS="riscv_isa riscv_compliance" TRACE=1
- make run_vcs CFG=BASE BUS=AHB TARGETS="dhrystone21 coremark" SIM_BUILD_OPTS="-gui"
- make run_modelsim CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=1 IPIC=1 TCM=0 TARGETS=isr_sample
-```
-
-Build and run parameters can be configured in the `./Makefile`.
-
-After all the tests have finished, the results can be found in `build/<SIM_CFG>/test_results.txt`.
-
-**IMPORTANT:** To ensure correct rebuild, please clean build directory between simulation runs:
-``` sh
- make clean
-```
-
-Please refer to the *"Simulation environment"* chapter of the [SCR1 User Manual](https://github.com/syntacore/scr1/blob/master/docs/scr1_um.pdf) for more information on setting up a simulation run.
-
-## SCR1 SDKs
-
-FPGA-based SDKs are available at the <https://github.com/syntacore/scr1-sdk>.
-
-Repo contains:
-
-* Pre-build images and open designs for several standard FPGAs boards:
- * Digilent Arty (Xilinx)
- * Digilent Nexys 4 DDR (Xilinx)
- * Arria V GX Starter (Intel)
- * Terasic DE10-Lite (Intel)
-* Software package:
- * Bootloader
- * Zephyr RTOS
- * Tests\SW samples
-* User Guides for SDKs and tools
-
-## Contacts
-
-Report an issue: <https://github.com/syntacore/scr1/issues>
-
-Ask a question: scr1@syntacore.com
diff --git a/verilog/rtl/syntacore_scr1/docs/img/scr1_cluster.svg b/verilog/rtl/syntacore_scr1/docs/img/scr1_cluster.svg
deleted file mode 100644
index 15af238..0000000
--- a/verilog/rtl/syntacore_scr1/docs/img/scr1_cluster.svg
+++ /dev/null
@@ -1,619 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
-<!-- Создано Microsoft Visio, экспорт SVG scr1_cluster.svg scr1_cluster -->
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ev="http://www.w3.org/2001/xml-events"
- xmlns:v="http://schemas.microsoft.com/visio/2003/SVGExtensions/" width="5.73958in" height="5.11458in"
- viewBox="0 0 413.25 368.25" xml:space="preserve" color-interpolation-filters="sRGB" class="st12">
- <v:documentProperties v:langID="2057" v:viewMarkup="false"/>
-
- <style type="text/css">
- <![CDATA[
- .st1 {fill:#dcedfa;stroke:#243740;stroke-linecap:butt;stroke-width:0.75}
- .st2 {fill:#b1ddf0;stroke:#243740;stroke-linecap:butt;stroke-width:0.75}
- .st3 {fill:#b0e3e6;stroke:#243740;stroke-linecap:butt;stroke-width:0.75}
- .st4 {fill:none}
- .st5 {stroke:#243740;stroke-linecap:butt;stroke-width:1.5}
- .st6 {fill:#243740;stroke:#243740;stroke-linecap:butt;stroke-width:1.5}
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