syntacore timing fix
diff --git a/docs/source/_static/user_project_wrapper.gds.png b/docs/source/_static/user_project_wrapper.gds.png
index b856180..46f95f1 100644
--- a/docs/source/_static/user_project_wrapper.gds.png
+++ b/docs/source/_static/user_project_wrapper.gds.png
Binary files differ
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index a65ed4e..840e8c3 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -32,7 +32,7 @@
set ::env(PAD_SDRAM_CLOCK_PORT) "u_skew_sd_ci*clk_in"
set ::env(PAD_SDRAM_CLOCK_NAME) "sdram_pad_clk"
-set ::env(CPU_CLOCK_PERIOD) "50"
+set ::env(CPU_CLOCK_PERIOD) "20"
set ::env(CPU_CLOCK_PORT) "u_wb_host*cpu_clk"
set ::env(CPU_CLOCK_NAME) "cpu_clk"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 02f4516..738387c 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -187,6 +187,7 @@
-mag_path $::env(magic_result_file_tag).mag \
-maglef_path $::env(magic_result_file_tag).lef.mag \
-spice_path $::env(magic_result_file_tag).spice \
+ -spef_path $::env(tritonRoute_result_file_tag).spef \
-verilog_path $::env(CURRENT_NETLIST) \
-save_path $arg_values(-save_path) \
-tag $::env(RUN_TAG)
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 152ff0b..fa9e31a 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h47m31s,0h4m45s,3.3079078455790785,10.2784,1.6539539227895392,0,552.5,17,0,0,0,0,0,0,0,0,1,-1,-1,1189752,3991,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.27,4.33,0.76,1.88,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m53s,0h4m37s,3.3079078455790785,10.2784,1.6539539227895392,0,551.71,17,0,0,0,0,0,0,0,0,1,-1,-1,1189766,3917,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.26,4.3,0.77,1.93,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv
new file mode 100755
index 0000000..a911d41
--- /dev/null
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv
@@ -0,0 +1,215 @@
+/////////////////////////////////////////////////////////////////////////////
+//// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+////
+//// Licensed under the Apache License, Version 2.0 (the "License");
+//// you may not use this file except in compliance with the License.
+//// You may obtain a copy of the License at
+////
+//// http://www.apache.org/licenses/LICENSE-2.0
+////
+//// Unless required by applicable law or agreed to in writing, software
+//// distributed under the License is distributed on an "AS IS" BASIS,
+//// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//// See the License for the specific language governing permissions and
+//// limitations under the License.
+//// SPDX-License-Identifier: Apache-2.0
+//// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+/////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////////////
+//// ////
+//// 32 / 32 Divider with 16 stage pipe line , Support Signed Division ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// 32 Div By 32 with 16 stage pipe line for timing reason ////
+//// Note: 2 Bit are computed at a time ////
+//// bit[32] =1 indicate negative number ////
+//// ////
+//// Example: 4'b1011 Div 4'b0011 ////
+//// ////
+//// ////
+//// """"""""| ////
+//// 1011 | <- qr reg ////
+//// -0011000 | <- Shuft Divider by 3 ////
+//// """"""""| <- 0011000 > 1011 , ignore sub, Quo: 0 ////
+//// 1011 | ////
+//// -001100 | <- Shift Divider by 2 ////
+//// """"""""| <- 001100 > 1011 , ignore sub, Quo:00 ////
+//// 1011 | ////
+//// -00110 | <- Shift Divider by 1 ////
+//// """"""""| <- 00110 < 1011, Rem: 0101 and Quo:001 ////
+//// 0101 | ////
+//// -0011 | <- Shift Divider by 0 ////
+//// """"""""| <- 0011 < 0101 , Rem: 10 and Quo: 0011 ////
+//// 10 | ////
+//// ////
+//// Quotient, 3 (0011); remainder 2 (10). ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// ////
+/////////////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+/////////////////////////////////////////////////////////////////////////////
+
+module scr1_pipe_div(
+ input logic clk,
+ input logic rstn,
+ input logic data_valid, // input valid
+ input logic [32:0] Din1, // dividend
+ input logic [32:0] Din2, // divider
+ output logic [31:0] quotient, // quotient
+ output logic [31:0] remainder, // remainder
+ output logic div_rdy_o, // Div result ready
+ input logic data_done // Result processing complete indication
+ );
+
+parameter WAIT_CMD = 2'b00; // Accept command and Do Signed to unsigned
+parameter WAIT_COMP = 2'b01; // Wait for COMPUTATION
+parameter WAIT_DONE = 2'b10; // Do Signed to Unsigned conversion
+parameter WAIT_EXIT = 2'b11; // Wait for Data Completion
+
+logic [31:0] src1, src2;
+
+// wires
+logic div0, div1;
+logic [31:0] rem0, rem1, rem2;
+logic [32:0] sub0, sub1;
+logic [63:0] cmp0, cmp1;
+logic [31:0] div_out, rem_out;
+logic [1:0] state, next_state;
+logic div_rdy_i;
+logic [31:0] quotient_next; // quotient
+logic [31:0] remainder_next; // remainder
+
+// real registers
+logic [3:0] cycle,next_cycle;
+
+// The main logic
+assign cmp1 = src2 << ({4'b1111 - cycle, 1'b0} + 'h1);
+assign cmp0 = src2 << ({4'b1111 - cycle, 1'b0} + 'h0);
+
+assign rem2 = cycle != 0 ? remainder : src1;
+
+assign sub1 = {1'b0, rem2} - {1'b0, cmp1[31:0]};
+assign div1 = |cmp1[63:32] ? 1'b0 : !sub1[32];
+assign rem1 = div1 ? sub1[31:0] : rem2[31:0];
+
+assign sub0 = {1'b0, rem1} - {1'b0, cmp0[31:0]};
+assign div0 = |cmp0[63:32] ? 1'b0 : !sub0[32];
+assign rem0 = div0 ? sub0[31:0] : rem1[31:0];
+
+//
+// in clock cycle 0 we first calculate two MSB bits, ...
+// till finally in clock cycle 3 we calculate two LSB bits
+assign div_out = {quotient[29:0], div1, div0};
+assign rem_out = rem0;
+
+//
+// divider works in four clock cycles -- 0, 1, 2 and 3
+always_ff @(posedge clk or negedge rstn)
+begin
+ if (!rstn) begin
+ state <= WAIT_CMD;
+ cycle <= 4'b0;
+ div_rdy_o <= 1'b0;
+ quotient <= 32'h0;
+ remainder <= 32'h0;
+ src1 <= 32'h0;
+ src2 <= 32'h0;
+ end else begin
+ cycle <= next_cycle;
+ state <= next_state;
+ div_rdy_o <= div_rdy_i;
+ if(data_valid && state== WAIT_CMD ) begin
+ src1 <= (Din1[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din1[31:0])+1 : Din1[31:0];
+ src2 <= (Din2[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din2[31:0])+1 : Din2[31:0];
+ end
+ quotient <= quotient_next;
+ remainder <= remainder_next;
+ end
+end
+
+
+always_comb
+begin
+ div_rdy_i = 0;
+ next_cycle = cycle;
+ next_state = state;
+ quotient_next = quotient;
+ remainder_next = remainder;
+ case(state)
+ WAIT_CMD: if(data_valid) begin
+ next_cycle = 0;
+ if(Din2[31:0] == 0) begin // Div by 0 case
+ next_state = WAIT_DONE;
+ end else begin
+ next_state = WAIT_COMP;
+ end
+ end
+ // WAIT for Computation
+ WAIT_COMP:
+ begin
+ quotient_next = div_out;
+ remainder_next = rem_out;
+ next_cycle = cycle +1;
+ if(cycle == 15) begin
+ next_state = WAIT_DONE;
+ end else begin
+ next_cycle = cycle +1;
+ end
+ end
+ WAIT_DONE:
+ begin
+ if(Din2[31:0] == 0) begin // Handling div by 0 case
+ quotient_next = 32'hFFFF_FFFF;
+ remainder_next = Din1[31:0];
+ end else begin
+ if(Din1[32] ^ Din2[32]) begin
+ quotient_next = (32'hFFFF_FFFF ^ quotient[31:0]) + 1;
+ end
+ if(Din1[32]) begin
+ remainder_next = (32'hFFFF_FFFF ^ remainder[31:0]) + 1;
+ end
+ end
+ div_rdy_i = 1'b1;
+ next_state = WAIT_EXIT;
+ end
+ WAIT_EXIT: begin
+ if(data_done) // Wait for data completion command
+ next_state = WAIT_CMD;
+ end
+ endcase
+end
+endmodule
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv
new file mode 100755
index 0000000..524e52d
--- /dev/null
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv
@@ -0,0 +1,176 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// 32x32 Multiplier with 8 stage pipe line ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// 32x32 Multiplier with 8 stage pipe line for timing reason ////
+//// Support signed multiplication, bit[32] indicate sign ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th July 2021 ////
+//// Breaking two's completement into two stage for ////
+//// timing reason, When all lower 32 bit zero and ////
+//// it's complement will be '1', this will cause ////
+//// increment in higer bits ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module scr1_pipe_mul (
+ input logic clk,
+ input logic rstn,
+ input logic data_valid, // input valid
+ input logic [32:0] Din1, // first operand
+ input logic [32:0] Din2, // second operand
+ output logic [31:0] des_hig, // first result
+ output logic [31:0] des_low, // second result
+ output logic mul_rdy_o, // Multiply result ready
+ input logic data_done // Result processing complete indication
+ );
+
+parameter WAIT_CMD = 2'b00; // Accept command and Do Signed to unsigned
+parameter WAIT_COMP = 2'b01; // Wait for COMPUTATION
+parameter WAIT_DONE = 2'b10; // Do Signed to Unsigned conversion
+parameter WAIT_EXIT = 2'b11; // Wait for Data Completion
+
+// wires
+logic [35:0] tmp_mul1;
+logic [64:0] tmp_mul, shifted;
+logic [31:0] src1,src2; // Unsigned number
+
+// real registers
+logic [2:0] cycle,next_cycle;
+logic [63:0] mul_result,mul_next;
+logic [1:0] state, next_state;
+logic mul_rdy_i;
+logic mul_32b_zero_b;
+
+assign tmp_mul1 = src1 * src2[31:28];
+//assign shifted = (cycle == 3'h0 ? 64'h0 : {mul_result[59:0], 4'b0000});
+assign tmp_mul = tmp_mul1 + shifted;
+assign des_hig = mul_result[63:32];
+assign des_low = mul_result[31:0];
+
+always_ff @(posedge clk or negedge rstn)
+begin
+ if (!rstn) begin
+ state <= WAIT_CMD;
+ cycle <= 3'b0;
+ mul_result <= 65'b0;
+ mul_rdy_o <= 1'b0;
+ src1 <= 32'h0;
+ src2 <= 32'h0;
+ shifted <= 'h0;
+ mul_32b_zero_b <= '0;
+ end else begin
+ cycle <= next_cycle;
+ state <= next_state;
+ shifted <= {mul_next[59:0], 4'b0000};
+
+ mul_rdy_o <= mul_rdy_i;
+ if(data_valid && state== WAIT_CMD ) begin
+ src1 <= (Din1[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din1[31:0])+1 : Din1[31:0];
+ src2 <= (Din2[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din2[31:0])+1 : Din2[31:0];
+ end else begin
+ src2 <= src2 << 4;
+ end
+ if(state== WAIT_DONE ) begin
+ // If Number is negative, then do 2's complement
+ // Breaking 2's complement to timing reason
+ if(Din1[32] ^ Din2[32]) begin
+ mul_result[31:0] <= (32'hFFFF_FFFF ^ mul_result[31:0]) + 1;
+ mul_result[63:32] <= (mul_32b_zero_b == 1'b0) ? (32'hFFFF_FFFF ^ mul_result[63:32]) + 1 : (32'hFFFF_FFFF ^ mul_result[63:32]) ;
+ end
+ end else begin
+ mul_result <= mul_next;
+ mul_32b_zero_b <= |mul_next[31:0]; // check all bit are zero
+ end
+ end
+end
+
+always_comb
+begin
+ mul_rdy_i = 0;
+ next_cycle = cycle;
+ next_state = state;
+ mul_next = mul_result;
+ case(state)
+ WAIT_CMD: if(data_valid) begin // Start only on active High Edge
+ mul_next = 0;
+ next_cycle = 0;
+ next_state = WAIT_COMP;
+ end
+ // WAIT for Computation
+ WAIT_COMP:
+ begin
+ mul_next = tmp_mul;
+ next_cycle = cycle +1;
+ if(cycle == 7) begin
+ next_state = WAIT_DONE;
+ end else begin
+ next_cycle = cycle +1;
+ end
+ end
+ WAIT_DONE: begin
+ mul_rdy_i = 1'b1;
+ next_state = WAIT_EXIT;
+ end
+ WAIT_EXIT: begin
+ if(data_done) // Wait for data completion command
+ next_state = WAIT_CMD;
+ end
+ endcase
+end
+
+endmodule
+
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
new file mode 100644
index 0000000..bb51ee9
--- /dev/null
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
@@ -0,0 +1,488 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// syntacore interface block ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// Holds interface block and timer & reset sync logic ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`include "scr1_arch_description.svh"
+`include "scr1_memif.svh"
+`include "scr1_wb.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_TCM_EN
+ `define SCR1_IMEM_ROUTER_EN
+`endif // SCR1_TCM_EN
+
+module scr1_intf (
+ // Control
+ input logic pwrup_rst_n, // Power-Up Reset
+ input logic rst_n, // Regular Reset signal
+ input logic cpu_rst_n, // CPU Reset (Core Reset)
+ input logic core_clk, // Core clock
+ input logic rtc_clk, // Real-time clock
+ output logic [63:0] riscv_debug,
+
+`ifdef SCR1_DBG_EN
+ // -- JTAG I/F
+ input logic trst_n,
+`endif // SCR1_DBG_EN
+
+ input logic wb_rst_n, // Wish bone reset
+ input logic wb_clk, // wish bone clock
+ // Instruction Memory Interface
+ output logic wbd_imem_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
+ output logic wbd_imem_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
+ output logic [3:0] wbd_imem_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
+ input logic wbd_imem_ack_i, // acknowlegement
+ input logic wbd_imem_err_i, // error
+
+ // Data Memory Interface
+ output logic wbd_dmem_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
+ output logic wbd_dmem_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
+ output logic [3:0] wbd_dmem_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
+ input logic wbd_dmem_ack_i, // acknowlegement
+ input logic wbd_dmem_err_i, // error
+
+ // Common
+ output logic pwrup_rst_n_sync, // Power-Up reset
+ output logic rst_n_sync, // Regular reset
+ output logic cpu_rst_n_sync, // CPU reset
+ output logic test_mode, // DFT Test Mode
+ output logic test_rst_n, // DFT Test Reset
+ input logic core_rst_n_local, // Core reset
+ input logic [48:0] core_debug ,
+`ifdef SCR1_DBG_EN
+ // Debug Interface
+ output logic tapc_trst_n, // Test Reset (TRSTn)
+`endif
+ // Memory-mapped external timer
+ output logic [63:0] timer_val, // Machine timer value
+ // Instruction Memory Interface
+ output logic core_imem_req_ack, // IMEM request acknowledge
+ input logic core_imem_req, // IMEM request
+ input logic core_imem_cmd, // IMEM command
+ input logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr, // IMEM address
+ output logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata, // IMEM read data
+ output logic [1:0] core_imem_resp, // IMEM response
+
+ // Data Memory Interface
+ output logic core_dmem_req_ack, // DMEM request acknowledge
+ input logic core_dmem_req, // DMEM request
+ input logic core_dmem_cmd, // DMEM command
+ input logic[1:0] core_dmem_width, // DMEM data width
+ input logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr, // DMEM address
+ input logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata, // DMEM write data
+ output logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata, // DMEM read data
+ output logic [1:0] core_dmem_resp // DMEM response
+
+);
+//-------------------------------------------------------------------------------
+// Local parameters
+//-------------------------------------------------------------------------------
+localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+
+// Instruction memory interface from router to WB bridge
+logic wb_imem_req_ack;
+logic wb_imem_req;
+logic wb_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
+logic [1:0] wb_imem_resp;
+
+// Data memory interface from router to WB bridge
+logic wb_dmem_req_ack;
+logic wb_dmem_req;
+logic wb_dmem_cmd;
+logic [1:0] wb_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
+logic [1:0] wb_dmem_resp;
+
+`ifdef SCR1_TCM_EN
+// Instruction memory interface from router to TCM
+logic tcm_imem_req_ack;
+logic tcm_imem_req;
+logic tcm_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
+logic [1:0] tcm_imem_resp;
+
+// Data memory interface from router to TCM
+logic tcm_dmem_req_ack;
+logic tcm_dmem_req;
+logic tcm_dmem_cmd;
+logic [1:0] tcm_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
+logic [1:0] tcm_dmem_resp;
+`endif // SCR1_TCM_EN
+
+// Data memory interface from router to memory-mapped timer
+logic timer_dmem_req_ack;
+logic timer_dmem_req;
+logic timer_dmem_cmd;
+logic [1:0] timer_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
+logic [1:0] timer_dmem_resp;
+
+logic timer_irq;
+
+
+//---------------------------------------------------------------------------------
+// To avoid core level power hook up, we have brought this signal inside, to
+// avoid any cell at digital core level
+// --------------------------------------------------------------------------------
+assign test_mode = 1'b0;
+assign test_rst_n = 1'b0;
+
+assign riscv_debug = {core_imem_req_ack,core_imem_req,core_imem_cmd,core_imem_resp[1:0],
+ core_dmem_req_ack,core_dmem_req,core_dmem_cmd,core_dmem_resp[1:0],
+ wb_imem_req,wb_dmem_req,wb_imem_cmd,wb_imem_resp[1:0], core_debug };
+//-------------------------------------------------------------------------------
+// Reset logic
+//-------------------------------------------------------------------------------
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell #(
+ .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
+) i_pwrup_rstn_reset_sync (
+ .rst_n (pwrup_rst_n ),
+ .clk (core_clk ),
+ .test_rst_n (test_rst_n ),
+ .test_mode (test_mode ),
+ .rst_n_in (1'b1 ),
+ .rst_n_out (pwrup_rst_n_sync)
+);
+
+// Regular Reset synchronizer
+scr1_reset_sync_cell #(
+ .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
+) i_rstn_reset_sync (
+ .rst_n (pwrup_rst_n ),
+ .clk (core_clk ),
+ .test_rst_n (test_rst_n ),
+ .test_mode (test_mode ),
+ .rst_n_in (rst_n ),
+ .rst_n_out (rst_n_sync )
+);
+
+// CPU Reset synchronizer
+scr1_reset_sync_cell #(
+ .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
+) i_cpu_rstn_reset_sync (
+ .rst_n (pwrup_rst_n ),
+ .clk (core_clk ),
+ .test_rst_n (test_rst_n ),
+ .test_mode (test_mode ),
+ .rst_n_in (cpu_rst_n ),
+ .rst_n_out (cpu_rst_n_sync )
+);
+
+`ifdef SCR1_DBG_EN
+// TAPC Reset
+scr1_reset_and2_cell i_tapc_rstn_and2_cell (
+ .rst_n_in ({trst_n, pwrup_rst_n}),
+ .test_rst_n (test_rst_n ),
+ .test_mode (test_mode ),
+ .rst_n_out (tapc_trst_n )
+);
+`endif // SCR1_DBG_EN
+
+`ifdef SCR1_TCM_EN
+//-------------------------------------------------------------------------------
+// TCM instance
+//-------------------------------------------------------------------------------
+scr1_tcm #(
+ .SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
+) i_tcm (
+ .clk (core_clk ),
+ .rst_n (core_rst_n_local),
+
+ // Instruction interface to TCM
+ .imem_req_ack (tcm_imem_req_ack),
+ .imem_req (tcm_imem_req ),
+ .imem_addr (tcm_imem_addr ),
+ .imem_rdata (tcm_imem_rdata ),
+ .imem_resp (tcm_imem_resp ),
+
+ // Data interface to TCM
+ .dmem_req_ack (tcm_dmem_req_ack),
+ .dmem_req (tcm_dmem_req ),
+ .dmem_cmd (tcm_dmem_cmd ),
+ .dmem_width (tcm_dmem_width ),
+ .dmem_addr (tcm_dmem_addr ),
+ .dmem_wdata (tcm_dmem_wdata ),
+ .dmem_rdata (tcm_dmem_rdata ),
+ .dmem_resp (tcm_dmem_resp )
+);
+`endif // SCR1_TCM_EN
+
+
+//-------------------------------------------------------------------------------
+// Memory-mapped timer instance
+//-------------------------------------------------------------------------------
+scr1_timer i_timer (
+ // Common
+ .rst_n (core_rst_n_local ),
+ .clk (core_clk ),
+ .rtc_clk (rtc_clk ),
+
+ // Memory interface
+ .dmem_req (timer_dmem_req ),
+ .dmem_cmd (timer_dmem_cmd ),
+ .dmem_width (timer_dmem_width ),
+ .dmem_addr (timer_dmem_addr ),
+ .dmem_wdata (timer_dmem_wdata ),
+ .dmem_req_ack (timer_dmem_req_ack),
+ .dmem_rdata (timer_dmem_rdata ),
+ .dmem_resp (timer_dmem_resp ),
+
+ // Timer interface
+ .timer_val (timer_val ),
+ .timer_irq (timer_irq )
+);
+
+
+`ifdef SCR1_IMEM_ROUTER_EN
+//-------------------------------------------------------------------------------
+// Instruction memory router
+//-------------------------------------------------------------------------------
+scr1_imem_router #(
+ `ifdef SCR1_TCM_EN
+ .SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
+ .SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
+ `endif // SCR1_TCM_EN
+) i_imem_router (
+ .rst_n (core_rst_n_local ),
+ .clk (core_clk ),
+ // Interface to core
+ .imem_req_ack (core_imem_req_ack),
+ .imem_req (core_imem_req ),
+ .imem_cmd (core_imem_cmd ),
+ .imem_addr (core_imem_addr ),
+ .imem_rdata (core_imem_rdata ),
+ .imem_resp (core_imem_resp ),
+ // Interface to WB bridge
+ .port0_req_ack (wb_imem_req_ack ),
+ .port0_req (wb_imem_req ),
+ .port0_cmd (wb_imem_cmd ),
+ .port0_addr (wb_imem_addr ),
+ .port0_rdata (wb_imem_rdata ),
+ .port0_resp (wb_imem_resp ),
+ `ifdef SCR1_TCM_EN
+ // Interface to TCM
+ .port1_req_ack (tcm_imem_req_ack ),
+ .port1_req (tcm_imem_req ),
+ .port1_cmd (tcm_imem_cmd ),
+ .port1_addr (tcm_imem_addr ),
+ .port1_rdata (tcm_imem_rdata ),
+ .port1_resp (tcm_imem_resp )
+ `endif // SCR1_TCM_EN
+);
+
+`else // SCR1_IMEM_ROUTER_EN
+
+assign wb_imem_req = core_imem_req;
+assign wb_imem_cmd = core_imem_cmd;
+assign wb_imem_addr = core_imem_addr;
+assign core_imem_req_ack = wb_imem_req_ack;
+assign core_imem_resp = wb_imem_resp;
+assign core_imem_rdata = wb_imem_rdata;
+
+`endif // SCR1_IMEM_ROUTER_EN
+
+//-------------------------------------------------------------------------------
+// Data memory router
+//-------------------------------------------------------------------------------
+scr1_dmem_router #(
+
+`ifdef SCR1_TCM_EN
+ .SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
+ .SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
+`else // SCR1_TCM_EN
+ .SCR1_PORT1_ADDR_MASK (32'h00000000),
+ .SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
+`endif // SCR1_TCM_EN
+
+ .SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
+ .SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
+
+) i_dmem_router (
+ .rst_n (core_rst_n_local ),
+ .clk (core_clk ),
+ // Interface to core
+ .dmem_req_ack (core_dmem_req_ack ),
+ .dmem_req (core_dmem_req ),
+ .dmem_cmd (core_dmem_cmd ),
+ .dmem_width (core_dmem_width ),
+ .dmem_addr (core_dmem_addr ),
+ .dmem_wdata (core_dmem_wdata ),
+ .dmem_rdata (core_dmem_rdata ),
+ .dmem_resp (core_dmem_resp ),
+`ifdef SCR1_TCM_EN
+ // Interface to TCM
+ .port1_req_ack (tcm_dmem_req_ack ),
+ .port1_req (tcm_dmem_req ),
+ .port1_cmd (tcm_dmem_cmd ),
+ .port1_width (tcm_dmem_width ),
+ .port1_addr (tcm_dmem_addr ),
+ .port1_wdata (tcm_dmem_wdata ),
+ .port1_rdata (tcm_dmem_rdata ),
+ .port1_resp (tcm_dmem_resp ),
+`else // SCR1_TCM_EN
+ .port1_req_ack (1'b0),
+ .port1_req ( ),
+ .port1_cmd ( ),
+ .port1_width ( ),
+ .port1_addr ( ),
+ .port1_wdata ( ),
+ .port1_rdata (32'h0 ),
+ .port1_resp (SCR1_MEM_RESP_RDY_ER),
+`endif // SCR1_TCM_EN
+ // Interface to memory-mapped timer
+ .port2_req_ack (timer_dmem_req_ack ),
+ .port2_req (timer_dmem_req ),
+ .port2_cmd (timer_dmem_cmd ),
+ .port2_width (timer_dmem_width ),
+ .port2_addr (timer_dmem_addr ),
+ .port2_wdata (timer_dmem_wdata ),
+ .port2_rdata (timer_dmem_rdata ),
+ .port2_resp (timer_dmem_resp ),
+ // Interface to WB bridge
+ .port0_req_ack (wb_dmem_req_ack ),
+ .port0_req (wb_dmem_req ),
+ .port0_cmd (wb_dmem_cmd ),
+ .port0_width (wb_dmem_width ),
+ .port0_addr (wb_dmem_addr ),
+ .port0_wdata (wb_dmem_wdata ),
+ .port0_rdata (wb_dmem_rdata ),
+ .port0_resp (wb_dmem_resp )
+);
+
+
+//-------------------------------------------------------------------------------
+// Instruction memory WB bridge
+//-------------------------------------------------------------------------------
+scr1_imem_wb i_imem_wb (
+ .core_rst_n (core_rst_n_local ),
+ .core_clk (core_clk ),
+ // Interface to imem router
+ .imem_req_ack (wb_imem_req_ack ),
+ .imem_req (wb_imem_req ),
+ .imem_addr (wb_imem_addr ),
+ .imem_rdata (wb_imem_rdata ),
+ .imem_resp (wb_imem_resp ),
+ // WB interface
+ .wb_rst_n (wb_rst_n ),
+ .wb_clk (wb_clk ),
+ .wbd_stb_o (wbd_imem_stb_o ),
+ .wbd_adr_o (wbd_imem_adr_o ),
+ .wbd_we_o (wbd_imem_we_o ),
+ .wbd_dat_o (wbd_imem_dat_o ),
+ .wbd_sel_o (wbd_imem_sel_o ),
+ .wbd_dat_i (wbd_imem_dat_i ),
+ .wbd_ack_i (wbd_imem_ack_i ),
+ .wbd_err_i (wbd_imem_err_i )
+);
+
+
+//-------------------------------------------------------------------------------
+// Data memory WB bridge
+//-------------------------------------------------------------------------------
+scr1_dmem_wb i_dmem_wb (
+ .core_rst_n (core_rst_n_local ),
+ .core_clk (core_clk ),
+ // Interface to dmem router
+ .dmem_req_ack (wb_dmem_req_ack ),
+ .dmem_req (wb_dmem_req ),
+ .dmem_cmd (wb_dmem_cmd ),
+ .dmem_width (wb_dmem_width ),
+ .dmem_addr (wb_dmem_addr ),
+ .dmem_wdata (wb_dmem_wdata ),
+ .dmem_rdata (wb_dmem_rdata ),
+ .dmem_resp (wb_dmem_resp ),
+ // WB interface
+ .wb_rst_n (wb_rst_n ),
+ .wb_clk (wb_clk ),
+ .wbd_stb_o (wbd_dmem_stb_o ),
+ .wbd_adr_o (wbd_dmem_adr_o ),
+ .wbd_we_o (wbd_dmem_we_o ),
+ .wbd_dat_o (wbd_dmem_dat_o ),
+ .wbd_sel_o (wbd_dmem_sel_o ),
+ .wbd_dat_i (wbd_dmem_dat_i ),
+ .wbd_ack_i (wbd_dmem_ack_i ),
+ .wbd_err_i (wbd_dmem_err_i )
+);
+
+endmodule : scr1_intf
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
index ae26909..63d5d7c 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
@@ -19,7 +19,7 @@
/// @brief Memory-mapped Timer
/// Version 1.0 - 18 - July 2021 - Dinesh A Project: yifive
/// 1.To break the timing path, input and output path are registered
-/// 2.Spilt the 64 bit adder into two 32 bit added with taking care of
+/// 2.Spilt the 64 bit adder into two 32 bit adder with taking care of
/// overflow
////////////////////////////////////////////////////////////////////////////////
@@ -66,6 +66,7 @@
// Local signals declaration
//-------------------------------------------------------------------------------
logic [63:0] mtime_reg;
+logic mtime_32b_ovr; // Indicate 32b Ovr flow
logic [63:0] mtime_new;
logic [63:0] mtimecmp_reg;
logic [63:0] mtimecmp_new;
@@ -124,12 +125,10 @@
mtime_new = mtime_reg;
if (time_posedge) begin
mtime_new[31:0] = mtime_reg[31:0] + 1'b1;
- mtime_new[63:32] = (&mtime_reg[31:0]) ? (mtime_new[63:32] + 1'b1) : mtime_new[63:32];
- end
- if (mtimelo_up) begin
+ mtime_new[63:32] = mtime_32b_ovr ? (mtime_new[63:32] + 1'b1) : mtime_new[63:32];
+ end else if (mtimelo_up) begin
mtime_new[31:0] = dmem_wdata;
- end
- if (mtimehi_up) begin
+ end else if (mtimehi_up) begin
mtime_new[63:32] = dmem_wdata;
end
end
@@ -137,9 +136,11 @@
always_ff @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
mtime_reg <= '0;
+ mtime_32b_ovr <= '0;
end else begin
if (time_posedge | mtimelo_up | mtimehi_up) begin
mtime_reg <= mtime_new;
+ mtime_32b_ovr <= &mtime_new; // Indicate 32B Overflow in next increment by check all one
end
end
end
diff --git a/verilog/rtl/syntacore/scr1/synth/synth.tcl b/verilog/rtl/syntacore/scr1/synth/synth.tcl
index 3331be6..f71d243 100755
--- a/verilog/rtl/syntacore/scr1/synth/synth.tcl
+++ b/verilog/rtl/syntacore/scr1/synth/synth.tcl
@@ -54,6 +54,7 @@
../src/top/scr1_imem_router.sv \
../src/top/scr1_tcm.sv \
../src/top/scr1_timer.sv \
+ ../src/top/scr1_intf.sv \
../src/top/scr1_top_wb.sv \
../src/top/scr1_dmem_wb.sv \
../src/top/scr1_imem_wb.sv \
