caravel update
diff --git a/.gitmodules b/.gitmodules
index 9bc2fca..0fbcc7c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -9,5 +9,5 @@
path = verilog/rtl/syntacore/scr1/dependencies/coremark
url = https://github.com/eembc/coremark
[submodule "caravel-lite"]
- path = caravel-lite
+ path = caravel
url = https://github.com/efabless/caravel-lite.git
diff --git a/Makefile b/Makefile
index aac51a9..89a50bb 100644
--- a/Makefile
+++ b/Makefile
@@ -15,9 +15,8 @@
# SPDX-License-Identifier: Apache-2.0
CARAVEL_ROOT?=$(PWD)/caravel
-PRECHECK_ROOT?=${HOME}/open_mpw_precheck
-SIM?=RTL
-DUMP?=OFF
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+SIM ?= RTL
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
@@ -36,9 +35,9 @@
SUBMODULE?=1
# Include Caravel Makefile Targets
-.PHONY: %
+.PHONY: % : check-caravel
%:
- $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
# Verify Target for running simulations
.PHONY: verify
@@ -78,7 +77,7 @@
BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
.PHONY: $(BLOCKS)
$(BLOCKS): %:
- cd openlane && $(MAKE) $*
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
# Install caravel
.PHONY: install
@@ -147,20 +146,20 @@
# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
.PHONY: precheck
precheck:
- @git clone https://github.com/efabless/open_mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
- @docker pull efabless/open_mpw_precheck:latest
+ @git clone https://github.com/efabless/mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
.PHONY: run-precheck
run-precheck: check-precheck check-pdk check-caravel
- $(eval TARGET_PATH := $(shell pwd))
+ $(eval INPUT_DIRECTORY := $(shell pwd))
cd $(PRECHECK_ROOT) && \
- docker run -v $(PRECHECK_ROOT):/usr/local/bin -v $(TARGET_PATH):$(TARGET_PATH) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
- -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --pdk_root $(PDK_ROOT) --target_path $(TARGET_PATH) -rfc -c $(CARAVEL_ROOT) "
+ docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)"
# Install PDK using OL's Docker Image
.PHONY: pdk-nonnative
pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
- docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(pwd):/user_project -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
+ docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
# Clean
.PHONY: clean
diff --git a/README.md b/README.md
index aaa083d..b9a6374 100644
--- a/README.md
+++ b/README.md
@@ -48,10 +48,14 @@
```
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* industry-grade and silicon-proven Open-Source RISC-V core from syntacore
+ * 4KB SRAM for data memory
+ * Pin Compatbible to arudino uno
* Quad SPI Master
* UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
+ * 6 Channel ADC
+ * 6 PWM
* Wishbone compatible design
* Written in System Verilog
* Open-source tool set
@@ -104,37 +108,66 @@
<tr>
<td align="center"> 0x0000_0000 to 0x0FFF_FFFF </td>
<td align="center"> 0x0000_0000 to 0x0FFF_FFFF </td>
- <td align="center"> 0x4000_0000 to 0x4FFF_FFFF</td>
+ <td align="center"> 0x0000_0000 to 0x0FFF_FFFF</td>
<td align="center"> SPI FLASH MEMORY</td>
</tr>
<tr>
<td align="center"> 0x1000_0000 to 0x1000_00FF</td>
<td align="center"> 0x1000_0000 to 0x1000_00FF</td>
- <td align="center"> 0x5000_0000 to 0x5000_00FF</td>
+ <td align="center"> 0x1000_0000 to 0x1000_00FF</td>
<td align="center"> SPI Config Reg</td>
</tr>
-
<tr>
- <td align="center"> 0x3000_0000 to 0x3000_00FF</td>
- <td align="center"> 0x3000_0000 to 0x3000_00FF</td>
- <td align="center"> 0x3000_0000 to 0x3000_00FF</td>
- <td align="center"> Global Register</td>
+ <td align="center"> 0x1001_0000 to 0x1001_003F</td>
+ <td align="center"> 0x1001_0000 to 0x1001_003F</td>
+ <td align="center"> 0x1001_0000 to 0x1001_003F</td>
+ <td align="center"> UART</td>
+ </tr>
+ <tr>
+ <td align="center"> 0x1001_0040 to 0x1001_007F</td>
+ <td align="center"> 0x1001_0040 to 0x1001_007F</td>
+ <td align="center"> 0x1001_0040 to 0x1001_007F</td>
+ <td align="center"> I2C</td>
+ </tr>
+ <tr>
+ <td align="center"> 0x1001_0080 to 0x1001_00FF</td>
+ <td align="center"> 0x1001_0080 to 0x1001_00FF</td>
+ <td align="center"> 0x1001_0080 to 0x1001_00FF</td>
+ <td align="center"> USB</td>
+ </tr>
+ <tr>
+ <td align="center"> 0x1002_0080 to 0x1002_00FF</td>
+ <td align="center"> 0x1002_0080 to 0x1002_00FF</td>
+ <td align="center"> 0x1002_0080 to 0x1002_00FF</td>
+ <td align="center"> PINMUX</td>
+ </tr>
+ <tr>
+ <td align="center"> 0x1003_0080 to 0x1003_00FF</td>
+ <td align="center"> 0x1003_0080 to 0x1003_00FF</td>
+ <td align="center"> 0x1003_0080 to 0x1003_00FF</td>
+ <td align="center"> PINMUX</td>
+ </tr>
+ <tr>
+ <td align="center"> -</td>
+ <td align="center"> -</td>
+ <td align="center"> 0x3080_0000 to 0x3080_00FF</td>
+ <td align="center"> WB HOST</td>
</tr>
</table>
# SOC Size
-| Block | Total Cell | Seq | Combo |
-| ------ | --------- | -------- | ----- |
-| RISC | 26642 | 3158 | 23484 |
-| GLOBAL REG | 2753 | 575 | 2178 |
-| SDRAM | 7198 | 1207 | 5991 |
-| SPI | 7607 | 1279 | 6328 |
-| UART_I2C | 3561 | 605 | 2956 |
-| WB_HOST | 3073 | 515 | 2558 |
-| WB_INTC | 1291 | 110 | 1181 |
-| | | | |
-| TOTAL | 52125 | 7449 | 44676 |
+| Block | Total Cell | Seq | Combo |
+| ------ | --------- | -------- | ----- |
+| RISC | 26919 | 3164 | 23755 |
+| PINMUX | 5461 | 1022 | 4439 |
+| SPI | 7597 | 1279 | 6318 |
+| UART_I2C_USB | 12423 | 2230 | 10193 |
+| WB_HOST | 3072 | 515 | 2557 |
+| WB_INTC | 1356 | 108 | 1248 |
+| SAR_ADC | 128 | 18 | 110 |
+| | | | |
+| TOTAL | 56956 | 8336 | 44620 |
diff --git a/caravel-lite b/caravel
similarity index 100%
rename from caravel-lite
rename to caravel
diff --git a/openlane/sar_adc/pin_order.cfg b/openlane/sar_adc/pin_order.cfg
index 392a553..9f5fbf6 100644
--- a/openlane/sar_adc/pin_order.cfg
+++ b/openlane/sar_adc/pin_order.cfg
@@ -95,5 +95,10 @@
sar2dac\[2\]
sar2dac\[1\]
sar2dac\[0\]
-analog_din
+analog_din\[5\]
+analog_din\[4\]
+analog_din\[3\]
+analog_din\[2\]
+analog_din\[1\]
+analog_din\[0\]
analog_dac_out
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 5c861db..b89efe6 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,13 +16,14 @@
# Base Configurations. Don't Touch
# section begin
set script_dir [file dirname [file normalize [info script]]]
+set proj_dir [file dirname [file normalize [info script]]]
source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
set ::env(DESIGN_NAME) user_project_wrapper
-set verilog_root $script_dir/../../verilog/
-set lef_root $script_dir/../../lef/
-set gds_root $script_dir/../../gds/
+set verilog_root $proj_dir/../../verilog/
+set lef_root $proj_dir/../../lef/
+set gds_root $proj_dir/../../gds/
#section end
# User Configurations
@@ -33,8 +34,8 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+ $proj_dir/../../caravel/verilog/rtl/defines.v \
+ $proj_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
@@ -45,26 +46,26 @@
## Internal Macros
### Macro Placement
set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(PDN_CFG) $proj_dir/pdn.tcl
-#set ::env(SDC_FILE) "$script_dir/base.sdc"
-#set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+#set ::env(SDC_FILE) "$proj_dir/base.sdc"
+#set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $script_dir/../../verilog/gl/spi_master.v \
- $script_dir/../../verilog/gl/wb_interconnect.v \
- $script_dir/../../verilog/gl/pinmux.v \
- $script_dir/../../verilog/gl/sar_adc.v \
- $script_dir/../../verilog/gl/uart_i2cm_usb.v \
- $script_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \
- $script_dir/../../verilog/gl/wb_host.v \
- $script_dir/../../verilog/gl/syntacore.v \
- $script_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $proj_dir/../../verilog/gl/spi_master.v \
+ $proj_dir/../../verilog/gl/wb_interconnect.v \
+ $proj_dir/../../verilog/gl/pinmux.v \
+ $proj_dir/../../verilog/gl/sar_adc.v \
+ $proj_dir/../../verilog/gl/uart_i2cm_usb.v \
+ $proj_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \
+ $proj_dir/../../verilog/gl/wb_host.v \
+ $proj_dir/../../verilog/gl/syntacore.v \
+ $proj_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
set ::env(EXTRA_LEFS) "\
@@ -92,7 +93,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
set ::env(GLB_RT_MAXLAYER) 5
diff --git a/signoff/sar_adc/final_summary_report.csv b/signoff/sar_adc/final_summary_report.csv
index d3936a2..17383a9 100644
--- a/signoff/sar_adc/final_summary_report.csv
+++ b/signoff/sar_adc/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sar_adc,sar_adc,sar_adc,Flow_completed,0h1m58s,0h1m3s,1653.3333333333335,0.15,826.6666666666667,1,439.33,124,0,0,0,0,0,0,0,0,13,-1,0,14612,1009,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,12962297,0.0,3.76,1.93,0.31,0.0,-1,102,181,48,127,0,0,0,124,0,0,0,1,12,0,0,32,19,26,5,204,1768,0,1972,10.0,100.0,100,AREA 0,5,50,1,45,40,0.01,0.15,sky130_fd_sc_hd,4,4
+0,/project/openlane/sar_adc,sar_adc,sar_adc,Flow_completed,0h1m45s,0h0m56s,1653.3333333333335,0.15,826.6666666666667,1,440.52,124,0,0,0,0,0,0,0,0,13,-1,0,14549,1000,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,12946929,0.0,3.68,1.92,0.36,0.0,-1,102,186,48,132,0,0,0,124,0,0,0,1,12,0,0,32,19,26,5,204,1768,0,1972,10.0,100.0,100,AREA 0,5,50,1,45,40,0.01,0.15,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
index e5d7813..2c0683d 100644
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h27m15s,0h11m51s,59157.14285714286,0.42,29578.57142857143,45,750.5,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h25m24s,0h9m59s,59157.14285714286,0.42,29578.57142857143,45,758.68,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
