push latest ycr core
diff --git a/.gitmodules b/.gitmodules
index e422cb9..102aa0f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,6 @@
[submodule "verilog/rtl/qspim"]
path = verilog/rtl/qspim
url = https://github.com/dineshannayya/qspim.git
-[submodule "verilog/rtl/yifive/ycr1cr"]
+[submodule "verilog/rtl/yifive/ycr1c"]
path = verilog/rtl/yifive/ycr1c
url = https://github.com/dineshannayya/ycr1cr.git
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index efc462a..d7a1662 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit efc462acd10fe6ba8f7aeed4eb0d6b05635115b3
+Subproject commit d7a16620e3212cf1d2777a8040fc4f2cf4598764
