user project def,lef,gds added
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 9fd9ca2..0b59edd 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -21,7 +21,7 @@
set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
+set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_sel_i*]
set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 0a4f516..5a67c33 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -139,3 +139,8 @@
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
deleted file mode 100644
index 6249330..0000000
--- a/openlane/user_project_wrapper/interactive.tcl
+++ /dev/null
@@ -1,34 +0,0 @@
-package require openlane
-set script_dir [file dirname [file normalize [info script]]]
-
-prep -design $script_dir -tag 24June2021 -overwrite
-set save_path $script_dir/../..
-
-run_synthesis
-run_floorplan
-run_placement
-run_cts
-run_routing
-
-write_powered_verilog
-set_netlist $::env(lvs_result_file_tag).powered.v
-run_magic
-run_magic_drc
-puts $::env(CURRENT_NETLIST)
-run_magic_spice_export
-
-save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(tritonRoute_result_file_tag).def \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -verilog_path $::env(CURRENT_NETLIST)\
- -save_path $save_path \
- -tag $::env(RUN_TAG)
-
-run_lvs
-run_antenna_check
-calc_total_runtime
-generate_final_summary_report
-puts_success "Flow Completed Without Fatal Errors."
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 5246de2..7e4defc 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h34m28s,0h2m12s,37.943648816936495,10.2784,18.971824408468247,0,585.11,195,0,0,0,0,0,0,74835,13,226,-1,2,898598,4357,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,895585866,0.0,1.19,1.92,1.26,2.19,-1,684,1302,676,1294,0,0,0,195,0,0,0,0,0,0,0,0,2,2,1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m47s,0h4m57s,38.33281444582815,10.2784,19.166407222914074,0,578.02,197,0,0,0,0,0,0,98674,15,225,-1,13,661124,2948,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,655217497,0.0,1.25,5.09,0.4,2.03,-1,693,1311,684,1302,0,0,0,197,0,0,0,0,0,0,0,0,2,2,1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.45,sky130_fd_sc_hd,4,0
