drc clean project ver1.0
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index a98636c..93cc2de 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -61,7 +61,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 400"
+set ::env(DIE_AREA) "0 0 500 500"
# If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 3c03978..a701001 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -59,7 +59,10 @@
ssram_sck
ssram_ss
-ssram_oen
+ssram_oen\[3\]
+ssram_oen\[2\]
+ssram_oen\[1\]
+ssram_oen\[0\]
ssram_do\[3\]
ssram_do\[2\]
ssram_do\[1\]
@@ -169,72 +172,70 @@
reg_rdata\[0\]
reg_ack
-digital_io_in\[15\] 300 0
-digital_io_out\[15\]
-digital_io_oen\[15\]
-digital_io_in\[16\]
-digital_io_out\[16\]
-digital_io_oen\[16\]
-digital_io_in\[17\]
-digital_io_out\[17\]
-digital_io_oen\[17\]
-digital_io_in\[18\]
-digital_io_out\[18\]
-digital_io_oen\[18\]
-digital_io_in\[19\]
-digital_io_out\[19\]
-digital_io_oen\[19\]
-digital_io_in\[20\]
-digital_io_out\[20\]
-digital_io_oen\[20\]
-digital_io_in\[21\]
-digital_io_out\[21\]
-digital_io_oen\[21\]
-digital_io_in\[22\]
-digital_io_out\[22\]
-digital_io_oen\[22\]
-digital_io_in\[23\]
+digital_io_in\[23\] 300 0
digital_io_out\[23\]
digital_io_oen\[23\]
+digital_io_in\[22\]
+digital_io_out\[22\]
+digital_io_oen\[22\]
+digital_io_in\[21\]
+digital_io_out\[21\]
+digital_io_oen\[21\]
+digital_io_in\[20\]
+digital_io_out\[20\]
+digital_io_oen\[20\]
+digital_io_in\[19\]
+digital_io_out\[19\]
+digital_io_oen\[19\]
+digital_io_in\[18\]
+digital_io_out\[18\]
+digital_io_oen\[18\]
+digital_io_in\[17\]
+digital_io_out\[17\]
+digital_io_oen\[17\]
+digital_io_in\[16\]
+digital_io_out\[16\]
+digital_io_oen\[16\]
+digital_io_in\[15\]
+digital_io_out\[15\]
+digital_io_oen\[15\]
#S
-pinmux_debug\[31\] 0000 0
-pinmux_debug\[30\]
-pinmux_debug\[29\]
-pinmux_debug\[28\]
-pinmux_debug\[27\]
-pinmux_debug\[26\]
-pinmux_debug\[25\]
-pinmux_debug\[24\]
-pinmux_debug\[23\]
-pinmux_debug\[22\]
-pinmux_debug\[21\]
-pinmux_debug\[20\]
-pinmux_debug\[19\]
-pinmux_debug\[18\]
-pinmux_debug\[17\]
-pinmux_debug\[16\]
-pinmux_debug\[15\]
-pinmux_debug\[14\]
-pinmux_debug\[13\]
-pinmux_debug\[12\]
-pinmux_debug\[11\]
-pinmux_debug\[10\]
-pinmux_debug\[9\]
-pinmux_debug\[8\]
-pinmux_debug\[7\]
-pinmux_debug\[6\]
-pinmux_debug\[5\]
-pinmux_debug\[4\]
-pinmux_debug\[3\]
-pinmux_debug\[2\]
+pinmux_debug\[0\] 0000 0 4
pinmux_debug\[1\]
-pinmux_debug\[0\]
-
-
+pinmux_debug\[2\]
+pinmux_debug\[3\]
+pinmux_debug\[4\]
+pinmux_debug\[5\]
+pinmux_debug\[6\]
+pinmux_debug\[7\]
+pinmux_debug\[8\]
+pinmux_debug\[9\]
+pinmux_debug\[10\]
+pinmux_debug\[11\]
+pinmux_debug\[12\]
+pinmux_debug\[13\]
+pinmux_debug\[14\]
+pinmux_debug\[15\]
+pinmux_debug\[16\]
+pinmux_debug\[17\]
+pinmux_debug\[18\]
+pinmux_debug\[19\]
+pinmux_debug\[20\]
+pinmux_debug\[21\]
+pinmux_debug\[22\]
+pinmux_debug\[23\]
+pinmux_debug\[24\]
+pinmux_debug\[25\]
+pinmux_debug\[26\]
+pinmux_debug\[27\]
+pinmux_debug\[28\]
+pinmux_debug\[29\]
+pinmux_debug\[30\]
+pinmux_debug\[31\]
#E
-digital_io_in\[0\]
+digital_io_in\[0\] 0000 0 4
digital_io_out\[0\]
digital_io_oen\[0\]
digital_io_in\[1\]
@@ -335,5 +336,8 @@
sflash_do\[0\]
sflash_sck
sflash_ss
-sflash_oen
+sflash_oen\[3\]
+sflash_oen\[2\]
+sflash_oen\[1\]
+sflash_oen\[0\]
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index bfe29dc..5f537e0 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -49,7 +49,10 @@
spi_sdo\[0\]
spi_clk
spi_csn0
-spi_oen
+spi_oen\[3\]
+spi_oen\[2\]
+spi_oen\[1\]
+spi_oen\[0\]
#S
wbd_stb_i 0000 0
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 1ce4c23..e939e83 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -96,7 +96,7 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.45"
+set ::env(PL_TARGET_DENSITY) "0.40"
set ::env(GLOBAL_ROUTER) "fastroute"
set ::env(DETAILED_ROUTER) "tritonroute"
set ::env(CELL_PAD) "4"
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 8bfe160..90d5c0e 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -1,6 +1,5 @@
#BUS_SORT
-
#MANUAL_PLACE
#E
@@ -8,6 +7,179 @@
rtc_clk
cpu_rst_n
+irq_lines\[15\]
+irq_lines\[14\]
+irq_lines\[13\]
+irq_lines\[12\]
+irq_lines\[11\]
+irq_lines\[10\]
+irq_lines\[9\]
+irq_lines\[8\]
+irq_lines\[7\]
+irq_lines\[6\]
+irq_lines\[5\]
+irq_lines\[4\]
+irq_lines\[3\]
+irq_lines\[2\]
+irq_lines\[1\]
+irq_lines\[0\]
+soft_irq
+fuse_mhartid\[31\]
+fuse_mhartid\[30\]
+fuse_mhartid\[29\]
+fuse_mhartid\[28\]
+fuse_mhartid\[27\]
+fuse_mhartid\[26\]
+fuse_mhartid\[25\]
+fuse_mhartid\[24\]
+fuse_mhartid\[23\]
+fuse_mhartid\[22\]
+fuse_mhartid\[21\]
+fuse_mhartid\[20\]
+fuse_mhartid\[19\]
+fuse_mhartid\[18\]
+fuse_mhartid\[17\]
+fuse_mhartid\[16\]
+fuse_mhartid\[15\]
+fuse_mhartid\[14\]
+fuse_mhartid\[13\]
+fuse_mhartid\[12\]
+fuse_mhartid\[11\]
+fuse_mhartid\[10\]
+fuse_mhartid\[9\]
+fuse_mhartid\[8\]
+fuse_mhartid\[7\]
+fuse_mhartid\[6\]
+fuse_mhartid\[5\]
+fuse_mhartid\[4\]
+fuse_mhartid\[3\]
+fuse_mhartid\[2\]
+fuse_mhartid\[1\]
+fuse_mhartid\[0\]
+
+sram_csb0 600 0 4
+sram_web0
+sram_addr0\[8\]
+sram_addr0\[7\]
+sram_addr0\[6\]
+sram_addr0\[5\]
+sram_addr0\[4\]
+sram_addr0\[3\]
+sram_addr0\[2\]
+sram_addr0\[1\]
+sram_addr0\[0\]
+sram_wmask0\[3\]
+sram_wmask0\[2\]
+sram_wmask0\[1\]
+sram_wmask0\[0\]
+sram_din0\[31\]
+sram_din0\[30\]
+sram_din0\[29\]
+sram_din0\[28\]
+sram_din0\[27\]
+sram_din0\[26\]
+sram_din0\[25\]
+sram_din0\[24\]
+sram_din0\[23\]
+sram_din0\[22\]
+sram_din0\[21\]
+sram_din0\[20\]
+sram_din0\[19\]
+sram_din0\[18\]
+sram_din0\[17\]
+sram_din0\[16\]
+sram_din0\[15\]
+sram_din0\[14\]
+sram_din0\[13\]
+sram_din0\[12\]
+sram_din0\[11\]
+sram_din0\[10\]
+sram_din0\[9\]
+sram_din0\[8\]
+sram_din0\[7\]
+sram_din0\[6\]
+sram_din0\[5\]
+sram_din0\[4\]
+sram_din0\[3\]
+sram_din0\[2\]
+sram_din0\[1\]
+sram_din0\[0\]
+sram_dout0\[31\]
+sram_dout0\[30\]
+sram_dout0\[29\]
+sram_dout0\[28\]
+sram_dout0\[27\]
+sram_dout0\[26\]
+sram_dout0\[25\]
+sram_dout0\[24\]
+sram_dout0\[23\]
+sram_dout0\[22\]
+sram_dout0\[21\]
+sram_dout0\[20\]
+sram_dout0\[19\]
+sram_dout0\[18\]
+sram_dout0\[17\]
+sram_dout0\[16\]
+sram_dout0\[15\]
+sram_dout0\[14\]
+sram_dout0\[13\]
+sram_dout0\[12\]
+sram_dout0\[11\]
+sram_dout0\[10\]
+sram_dout0\[9\]
+sram_dout0\[8\]
+sram_dout0\[7\]
+sram_dout0\[6\]
+sram_dout0\[5\]
+sram_dout0\[4\]
+sram_dout0\[3\]
+sram_dout0\[2\]
+sram_dout0\[1\]
+sram_dout0\[0\]
+
+sram_csb1
+sram_addr1\[8\]
+sram_addr1\[7\]
+sram_addr1\[6\]
+sram_addr1\[5\]
+sram_addr1\[4\]
+sram_addr1\[3\]
+sram_addr1\[2\]
+sram_addr1\[1\]
+sram_addr1\[0\]
+sram_dout1\[31\]
+sram_dout1\[30\]
+sram_dout1\[29\]
+sram_dout1\[28\]
+sram_dout1\[27\]
+sram_dout1\[26\]
+sram_dout1\[25\]
+sram_dout1\[24\]
+sram_dout1\[23\]
+sram_dout1\[22\]
+sram_dout1\[21\]
+sram_dout1\[20\]
+sram_dout1\[19\]
+sram_dout1\[18\]
+sram_dout1\[17\]
+sram_dout1\[16\]
+sram_dout1\[15\]
+sram_dout1\[14\]
+sram_dout1\[13\]
+sram_dout1\[12\]
+sram_dout1\[11\]
+sram_dout1\[10\]
+sram_dout1\[9\]
+sram_dout1\[8\]
+sram_dout1\[7\]
+sram_dout1\[6\]
+sram_dout1\[5\]
+sram_dout1\[4\]
+sram_dout1\[3\]
+sram_dout1\[2\]
+sram_dout1\[1\]
+sram_dout1\[0\]
+
#W
wb_clk 0000 0
wb_rst_n
@@ -226,58 +398,8 @@
wbd_dmem_ack_i
wbd_dmem_err_i
-irq_lines\[15\] 1200 0 2
-irq_lines\[14\]
-irq_lines\[13\]
-irq_lines\[12\]
-irq_lines\[11\]
-irq_lines\[10\]
-irq_lines\[9\]
-irq_lines\[8\]
-irq_lines\[7\]
-irq_lines\[6\]
-irq_lines\[5\]
-irq_lines\[4\]
-irq_lines\[3\]
-irq_lines\[2\]
-irq_lines\[1\]
-irq_lines\[0\]
-soft_irq
-fuse_mhartid\[31\]
-fuse_mhartid\[30\]
-fuse_mhartid\[29\]
-fuse_mhartid\[28\]
-fuse_mhartid\[27\]
-fuse_mhartid\[26\]
-fuse_mhartid\[25\]
-fuse_mhartid\[24\]
-fuse_mhartid\[23\]
-fuse_mhartid\[22\]
-fuse_mhartid\[21\]
-fuse_mhartid\[20\]
-fuse_mhartid\[19\]
-fuse_mhartid\[18\]
-fuse_mhartid\[17\]
-fuse_mhartid\[16\]
-fuse_mhartid\[15\]
-fuse_mhartid\[14\]
-fuse_mhartid\[13\]
-fuse_mhartid\[12\]
-fuse_mhartid\[11\]
-fuse_mhartid\[10\]
-fuse_mhartid\[9\]
-fuse_mhartid\[8\]
-fuse_mhartid\[7\]
-fuse_mhartid\[6\]
-fuse_mhartid\[5\]
-fuse_mhartid\[4\]
-fuse_mhartid\[3\]
-fuse_mhartid\[2\]
-fuse_mhartid\[1\]
-fuse_mhartid\[0\]
#S
-
riscv_debug\[0\] 500 0 4
riscv_debug\[1\]
riscv_debug\[2\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 05749d4..5c861db 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -64,6 +64,7 @@
$script_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \
$script_dir/../../verilog/gl/wb_host.v \
$script_dir/../../verilog/gl/syntacore.v \
+ $script_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
set ::env(EXTRA_LEFS) "\
@@ -75,6 +76,7 @@
$lef_root/sar_adc.lef \
$lef_root/DAC_8BIT.lef \
$lef_root/syntacore.lef \
+ $lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -85,7 +87,7 @@
$gds_root/wb_host.gds \
$gds_root/sar_adc.gds \
$gds_root/DAC_8BIT.gds \
- $gds_root/syntacore.gds \
+ $gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 051c72b..79dcb94 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -3,6 +3,7 @@
u_adc 2000 2700 N
u_dac 2000 3100 N
u_riscv_top 500 800 N
-u_pinmux 2200 1000 N
+u_sram_2kb 2200 1200 N
+u_pinmux 2200 300 N
u_intercon 300 2300 N
u_wb_host 300 300 N
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
new file mode 100644
index 0000000..bab6e84
--- /dev/null
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane v0.21-9-g94fe743
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/pinmux/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
new file mode 100644
index 0000000..dd08286
--- /dev/null
+++ b/signoff/pinmux/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/pinmux,pinmux,pinmux,Flow_completed,0h16m58s,0h8m8s,43688.0,0.25,21844.0,38,639.73,5461,0,0,0,0,0,0,0,0,0,-1,0,401103,52059,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,325104227,0.0,40.27,35.86,2.11,-1,-1,5298,5578,1003,1283,0,0,0,5461,131,0,36,66,784,107,11,1148,1014,964,12,350,3009,0,3359,100.0,10.0,10,AREA 0,4,50,1,100,100,0.35,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/sar_adc/OPENLANE_VERSION b/signoff/sar_adc/OPENLANE_VERSION
new file mode 100644
index 0000000..bab6e84
--- /dev/null
+++ b/signoff/sar_adc/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane v0.21-9-g94fe743
diff --git a/signoff/sar_adc/PDK_SOURCES b/signoff/sar_adc/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/sar_adc/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/sar_adc/final_summary_report.csv b/signoff/sar_adc/final_summary_report.csv
new file mode 100644
index 0000000..d3936a2
--- /dev/null
+++ b/signoff/sar_adc/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/sar_adc,sar_adc,sar_adc,Flow_completed,0h1m58s,0h1m3s,1653.3333333333335,0.15,826.6666666666667,1,439.33,124,0,0,0,0,0,0,0,0,13,-1,0,14612,1009,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,12962297,0.0,3.76,1.93,0.31,0.0,-1,102,181,48,127,0,0,0,124,0,0,0,1,12,0,0,32,19,26,5,204,1768,0,1972,10.0,100.0,100,AREA 0,5,50,1,45,40,0.01,0.15,sky130_fd_sc_hd,4,4
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 1349a9e..8e28748 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h15m27s,0h6m28s,49784.61538461538,0.26,24892.30769230769,40,642.45,6472,0,0,0,0,0,0,0,0,2,-1,0,302442,55080,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,228497488,0.0,25.86,30.21,0.29,-1,-1,6415,6548,1120,1253,0,0,0,6472,243,0,125,93,756,212,32,1957,1213,1151,25,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h20m39s,0h10m39s,58438.46153846153,0.26,29219.230769230766,47,664.71,7597,0,0,0,0,0,0,0,0,3,-1,0,384228,67124,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,294776771,0.0,31.33,39.79,0.04,-1,-1,7537,7673,1268,1404,0,0,0,7597,245,0,169,100,1051,210,32,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/syntacore/OPENLANE_VERSION b/signoff/syntacore/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/syntacore/OPENLANE_VERSION
+++ b/signoff/syntacore/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 33bb518..da99116 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h28m26s,0h25m23s,27737.5,1.92,13868.75,21,1242.11,26628,0,0,0,0,0,0,0,0,3,-1,0,1635488,254093,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1302938503,0.0,22.86,15.12,5.14,0.39,-1,26451,26752,3329,3630,0,0,0,26628,699,68,654,587,2858,979,288,7955,3220,3184,64,866,24574,0,25440,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h31m39s,0h24m23s,28040.625,1.92,14020.3125,21,1253.29,26919,0,0,0,0,0,0,0,0,2,-1,0,1880737,263792,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1499814362,0.0,26.25,17.0,6.81,0.41,-1,26694,27107,3332,3745,0,0,0,26919,705,68,683,599,2928,1044,290,8055,3258,3238,73,866,24574,0,25440,100.0,10.0,10,AREA 0,4,50,1,100,100,0.4,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
index ea00f72..e5d7813 100644
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h27m5s,0h11m4s,59157.14285714286,0.42,29578.57142857143,45,751.94,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h27m15s,0h11m51s,59157.14285714286,0.42,29578.57142857143,45,750.5,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 5f67206..66c490c 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h14m53s,0h8m57s,61440.0,0.1,30720.0,49,566.65,3072,0,0,0,0,0,0,0,0,0,-1,0,171387,26278,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,136337953,0.0,47.59,23.94,17.04,-1,-1,2927,3182,554,809,0,0,0,3072,78,0,3,11,50,27,10,797,605,773,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h9m58s,0h5m3s,61440.0,0.1,30720.0,49,583.21,3072,0,0,0,0,0,0,0,0,0,-1,0,170202,26317,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,138126985,0.0,48.13,23.41,16.33,-1,-1,2927,3182,554,809,0,0,0,3072,77,0,3,11,49,27,10,797,605,773,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
