qspim bug fix, wbs clock gen update
diff --git a/Makefile b/Makefile
index 2067627..2b4cb64 100644
--- a/Makefile
+++ b/Makefile
@@ -187,6 +187,24 @@
cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \
fi
+zip:
+ gzip -f def/*
+ gzip -f lef/*
+ gzip -f gds/*
+ gzip -f mag/*
+ gzip -f maglef/*
+ gzip -f spef/*
+ gzip -f spi/lvs/*
+
+unzip:
+ gzip -d def/*
+ gzip -d lef/*
+ gzip -d gds/*
+ gzip -d mag/*
+ gzip -d maglef/*
+ gzip -d spef/*
+ gzip -d spi/lvs/*
+
.PHONY: help
help:
cd $(CARAVEL_ROOT) && $(MAKE) help
diff --git a/README.md b/README.md
index 7271967..602f95e 100644
--- a/README.md
+++ b/README.md
@@ -48,12 +48,14 @@
```
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* industry-grade and silicon-proven Open-Source RISC-V core from syntacore
- * 4KB SRAM for data memory
- * 8KB SRAM for program memory
+ * 2KB SRAM for TCM Memory
+ * 2KB SRAM for Instruction cache
+ * 2KB SRAM for Data cache
* Quad SPI Master
* UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
+ * UART Master
* Simple SPI Master
* MBIST controller for 8KB Program memory
* 6 Channel ADC (in Progress)
@@ -144,7 +146,9 @@
* 2 to 4 stage pipeline
* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
* Optional RISC-V Debug subsystem with JTAG interface
- * Optional on-chip Tightly-Coupled Memory
+ * 2KB on-chip Tightly-Coupled Memory (TCM Memory)
+ * 2KB on-chip instruction cache
+ * 2KB on-chip data cache
```
### RISC V core customization Riscduino SOC
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc
index 4166d36..b18259c 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim/base.sdc
@@ -64,13 +64,19 @@
set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}]
-set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}]
-set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 35e8e08..3bac00d 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h19m18s,-1,42496.969696969696,0.2475,21248.484848484848,25.12,683.6,5259,0,0,0,0,0,0,-1,1,0,-1,-1,386276,55331,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,284511398.0,1.83,41.67,29.27,8.61,0.36,-1,3370,8310,523,5463,0,0,0,3952,0,0,0,0,0,0,0,4,1188,1209,11,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h8m51s,-1,42496.969696969696,0.2475,21248.484848484848,25.12,693.05,5259,0,0,0,0,0,0,-1,1,0,-1,-1,388178,55535,0.0,0.0,-1,-0.21,-1,0.0,0.0,-1,-0.21,-1,284496978.0,1.93,41.73,29.37,8.68,0.49,-1,3370,8310,523,5463,0,0,0,3952,0,0,0,0,0,0,0,4,1188,1209,11,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index eafe299..f03da6c 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h18m13s,-1,69139.39393939394,0.2475,34569.69696969697,39.57,778.62,8556,0,0,0,0,0,0,-1,1,0,-1,-1,423083,80674,-0.2,-5.37,-1,0.0,-1,-6.1,-2269.63,-1,0.0,-1,266384048.0,0.0,40.72,38.22,6.38,1.41,-1,7371,11035,803,4466,0,0,0,8344,0,0,0,0,0,0,0,4,2003,2524,22,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h14m22s,-1,69204.04040404041,0.2475,34602.020202020205,39.6,779.71,8564,0,0,0,0,0,0,-1,1,0,-1,-1,417412,80389,-0.29,-5.32,-1,0.0,-1,-14.71,-2179.87,-1,0.0,-1,263659655.0,0.0,40.7,36.95,6.51,0.87,-1,7378,11042,803,4466,0,0,0,8352,0,0,0,0,0,0,0,4,2000,2523,24,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 5600253..6959204 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h31m29s0ms,0h5m4s0ms,-2.0,-1,-1,-1,542.86,12,0,0,0,0,0,0,0,0,2,-1,-1,1256382,6969,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.83,7.29,0.62,0.23,-1,225,2313,225,2313,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h33m21s0ms,0h4m6s0ms,-2.0,-1,-1,-1,540.64,12,0,0,0,0,0,0,0,0,2,-1,-1,1256374,6915,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.81,7.25,0.67,0.31,-1,225,2313,225,2313,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index d1c2680..24b958a 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m6s,-1,59385.714285714275,0.14,29692.857142857138,37.96,637.61,4157,0,0,0,0,0,0,0,5,0,0,-1,217151,39662,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,160154988.0,8.33,37.43,36.42,1.44,1.04,-1,3490,6163,1024,3553,0,0,0,3793,0,0,0,0,0,0,0,4,1233,1205,17,278,1833,0,2111,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.38,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h6m52s,-1,59300.0,0.14,29650.0,37.93,636.42,4151,0,0,0,0,0,0,0,2,0,0,-1,215349,39348,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,160042151.0,7.36,37.22,36.69,1.49,0.3,-1,3488,6161,1030,3559,0,0,0,3786,0,0,0,0,0,0,0,4,1232,1202,17,278,1833,0,2111,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.38,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index 1eb1445..b9f1c98 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -263,4 +263,41 @@
report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Di[*] >> mprj.dffram.max.rpt
report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/A[*] >> mprj.dffram.max.rpt
report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Do[*] >> mprj.dffram.max.rpt
-
+
+
+ #Set False path from managment gpio enable towards SPI
+ set_false_path -through gpio_control_in_2[10]/mgmt_ena
+ set_false_path -through gpio_control_in_2[10]/gpio_outenb
+
+ echo " ##### SPI Timing" > spi.rpt
+ # SPI Inputs
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[0] -from mprj_io[29] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[1] -from mprj_io[30] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[2] -from mprj_io[31] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[3] -from mprj_io[32] >> spi.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[29] -from mprj_io[29] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[30] -from mprj_io[30] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[31] -from mprj_io[31] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[32] -from mprj_io[32] >> spi.rpt
+
+ #SPI output
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[29] -to mprj_io[29] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[30] -to mprj_io[30] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[31] -to mprj_io[31] >> spi.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[32] -to mprj_io[32] >> spi.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
diff --git a/sta/scripts/yifive_timing.tcl b/sta/scripts/yifive_timing.tcl
new file mode 100644
index 0000000..02d4e58
--- /dev/null
+++ b/sta/scripts/yifive_timing.tcl
@@ -0,0 +1,123 @@
+
+ set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino"
+ #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+ #set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
+
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+
+ # User project netlist
+ read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
+
+
+ link_design ycr1_top_wb
+
+
+ ## User Project Spef
+ read_spef $::env(USER_ROOT)/spef/ycr1_top_wb.spef
+
+
+ read_sdc -echo ./sdc/yifive.sdc
+ check_setup -verbose > unconstraints.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_worst_slack -max
+ report_worst_slack -min
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10
+ report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt
+
+
+ #Min Delay check around DFFRAM
+ echo "DFFRAM Interface Min Timing.................." > dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_wmask0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_cs0 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_din0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_addr0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_dout0[*] >> dffram.min.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_wmask1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_cs1 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_din1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_addr1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through tcm_dffram_dout1[*] >> dffram.min.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_wmask0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_cs0 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_din0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_addr0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_dout0[*] >> dffram.min.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_wmask1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_cs1 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_din1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_addr1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through icache_dffram_dout1[*] >> dffram.min.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_wmask0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_cs0 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_din0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_addr0[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_dout0[*] >> dffram.min.rpt
+
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_wmask1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_cs1 >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_din1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_addr1[*] >> dffram.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dcache_dffram_dout1[*] >> dffram.min.rpt
+
+ #Max Delay check around DFFRAM
+ echo "DFFRAM Interface Max Timing.................." > dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_wmask0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_cs0 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_din0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_addr0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_dout0[*] >> dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_wmask1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_cs1 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_din1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_addr1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through tcm_dffram_dout1[*] >> dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_wmask0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_cs0 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_din0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_addr0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_dout0[*] >> dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_wmask1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_cs1 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_din1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_addr1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through icache_dffram_dout1[*] >> dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_wmask0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_cs0 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_din0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_addr0[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_dout0[*] >> dffram.max.rpt
+
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_wmask1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_cs1 >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_din1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_addr1[*] >> dffram.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dcache_dffram_dout1[*] >> dffram.max.rpt
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 48d5279..448e929 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -22,6 +22,7 @@
create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}]
create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+create_generated_clock -name spi_clk -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 2 -comment {Spi Clock} [get_ports mprj_io[24]]
## Case analysis
@@ -68,9 +69,9 @@
set_propagated_clock [all_clocks]
set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {clock wb_clk mem_clk0 mem_clk1 mem_clk2 mem_clk3}]\
+ -group [get_clocks {clock wb_clk}]\
-group [get_clocks {user_clk2}]\
- -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_clk_i spi_clk}]\
-group [get_clocks {cpu_clk}]\
-group [get_clocks {cpu_ref_clk}]\
-group [get_clocks {rtc_clk}]\
@@ -110,15 +111,15 @@
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
-set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
+#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
-set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
-set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
-set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
-set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
+#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
+#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
+#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
+#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
@@ -130,6 +131,24 @@
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
+###############################################################################
+# User SPI constraints
+# Reducing the Tight SPI spec
+# As spi cs# asserted atleast 2 cycle before transaction, we are not constrainting it
+# In Spi Interace Data lanuch by negedge and capture at Posedge, So effective Interface hold and setup should not be
+# any issue. Any timing issue, we need to reduce the SPI interface clock
+#################################################################################
+
+set user_spi_out [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]]
+set user_spi_in [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]]
+
+set_input_delay -clock spi_clk -clock_fall -min 0 -add_delay $user_spi_in
+set_input_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_in
+
+set_output_delay -clock spi_clk -clock_fall -min -0 -add_delay $user_spi_out
+set_output_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_out
+
+
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
@@ -144,7 +163,6 @@
## User Project static signals
set_false_path -through [get_pins mprj/u_pinmux/bist_en]
-# TODO set this as parameter
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
@@ -159,89 +177,6 @@
set_clock_uncertainty -hold $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
-#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
-#
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
-#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
-#
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
-#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
-#
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
-#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
-
-
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
diff --git a/sta/sdc/yifive.sdc b/sta/sdc/yifive.sdc
new file mode 100644
index 0000000..309abd8
--- /dev/null
+++ b/sta/sdc/yifive.sdc
@@ -0,0 +1,338 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
+create_clock -name core_clk_mclk -period 20.0000 [get_ports {core_clk_mclk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+create_generated_clock -name tcm_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock0} [get_ports tcm_dffram_clk0]
+create_generated_clock -name tcm_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock1} [get_ports tcm_dffram_clk1]
+
+create_generated_clock -name icache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock0} [get_ports icache_dffram_clk0]
+create_generated_clock -name icache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock1} [get_ports icache_dffram_clk1]
+
+create_generated_clock -name dcache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_dffram_clk0]
+create_generated_clock -name dcache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_dffram_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set_propagated_clock [all_clocks]
+
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk core_clk_mclk tcm_dffram_clk0 tcm_dffram_clk1 icache_dffram_clk0 icache_dffram_clk1 dcache_dffram_clk0 dcache_dffram_clk1} ]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[3]}]
+
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_riscv}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv
+
+#TCM Memory
+set_input_delay -max 6.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}]
+set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}]
+set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}]
+
+# mem1
+set_input_delay -max 6.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_dout1[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_dout1[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_cs1}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_addr1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_wmask1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_din1[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_cs1}]
+set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_addr1[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_wmask1[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_din1[*]}]
+
+#icache memory
+set_input_delay -max 6.0000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_dout0[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_dout0[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_cs0}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_addr0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_wmask0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_din0[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_cs0}]
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_addr0[*]}]
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_wmask0[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_din0[*]}]
+
+# mem1
+set_input_delay -max 6.0000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_dout1[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_dout1[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_cs1}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_addr1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_wmask1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_din1[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_cs1}]
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_addr1[*]}]
+set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_wmask1[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_din1[*]}]
+
+#dcache memory
+
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_dout0[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_dout0[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_cs0}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_addr0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_wmask0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_din0[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_cs0}]
+set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_addr0[*]}]
+set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_wmask0[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_din0[*]}]
+
+# mem1
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_dout1[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_dout1[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_cs1}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_addr1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_wmask1[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_din1[*]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_cs1}]
+set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_addr1[*]}]
+set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_wmask1[*]}]
+set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_din1[*]}]
+
+
+
+
+set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
+
+#Wishbone DMEM
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+
+#Wishbone icache
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+
+#Wishbone dcache
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+
+set_false_path\
+ -from [get_ports {soft_irq}]
+set_false_path\
+ -to [list [get_ports {riscv_debug[0]}]\
+ [get_ports {riscv_debug[10]}]\
+ [get_ports {riscv_debug[11]}]\
+ [get_ports {riscv_debug[12]}]\
+ [get_ports {riscv_debug[13]}]\
+ [get_ports {riscv_debug[14]}]\
+ [get_ports {riscv_debug[15]}]\
+ [get_ports {riscv_debug[16]}]\
+ [get_ports {riscv_debug[17]}]\
+ [get_ports {riscv_debug[18]}]\
+ [get_ports {riscv_debug[19]}]\
+ [get_ports {riscv_debug[1]}]\
+ [get_ports {riscv_debug[20]}]\
+ [get_ports {riscv_debug[21]}]\
+ [get_ports {riscv_debug[22]}]\
+ [get_ports {riscv_debug[23]}]\
+ [get_ports {riscv_debug[24]}]\
+ [get_ports {riscv_debug[25]}]\
+ [get_ports {riscv_debug[26]}]\
+ [get_ports {riscv_debug[27]}]\
+ [get_ports {riscv_debug[28]}]\
+ [get_ports {riscv_debug[29]}]\
+ [get_ports {riscv_debug[2]}]\
+ [get_ports {riscv_debug[30]}]\
+ [get_ports {riscv_debug[31]}]\
+ [get_ports {riscv_debug[32]}]\
+ [get_ports {riscv_debug[33]}]\
+ [get_ports {riscv_debug[34]}]\
+ [get_ports {riscv_debug[35]}]\
+ [get_ports {riscv_debug[36]}]\
+ [get_ports {riscv_debug[37]}]\
+ [get_ports {riscv_debug[38]}]\
+ [get_ports {riscv_debug[39]}]\
+ [get_ports {riscv_debug[3]}]\
+ [get_ports {riscv_debug[40]}]\
+ [get_ports {riscv_debug[41]}]\
+ [get_ports {riscv_debug[42]}]\
+ [get_ports {riscv_debug[43]}]\
+ [get_ports {riscv_debug[44]}]\
+ [get_ports {riscv_debug[45]}]\
+ [get_ports {riscv_debug[46]}]\
+ [get_ports {riscv_debug[47]}]\
+ [get_ports {riscv_debug[48]}]\
+ [get_ports {riscv_debug[49]}]\
+ [get_ports {riscv_debug[4]}]\
+ [get_ports {riscv_debug[50]}]\
+ [get_ports {riscv_debug[51]}]\
+ [get_ports {riscv_debug[52]}]\
+ [get_ports {riscv_debug[53]}]\
+ [get_ports {riscv_debug[54]}]\
+ [get_ports {riscv_debug[55]}]\
+ [get_ports {riscv_debug[56]}]\
+ [get_ports {riscv_debug[57]}]\
+ [get_ports {riscv_debug[58]}]\
+ [get_ports {riscv_debug[59]}]\
+ [get_ports {riscv_debug[5]}]\
+ [get_ports {riscv_debug[60]}]\
+ [get_ports {riscv_debug[61]}]\
+ [get_ports {riscv_debug[62]}]\
+ [get_ports {riscv_debug[63]}]\
+ [get_ports {riscv_debug[6]}]\
+ [get_ports {riscv_debug[7]}]\
+ [get_ports {riscv_debug[8]}]\
+ [get_ports {riscv_debug[9]}]]
+
+set_false_path -from [get_ports {fuse_mhartid[0]}]
+set_false_path -from [get_ports {fuse_mhartid[10]}]
+set_false_path -from [get_ports {fuse_mhartid[11]}]
+set_false_path -from [get_ports {fuse_mhartid[12]}]
+set_false_path -from [get_ports {fuse_mhartid[13]}]
+set_false_path -from [get_ports {fuse_mhartid[14]}]
+set_false_path -from [get_ports {fuse_mhartid[15]}]
+set_false_path -from [get_ports {fuse_mhartid[16]}]
+set_false_path -from [get_ports {fuse_mhartid[17]}]
+set_false_path -from [get_ports {fuse_mhartid[18]}]
+set_false_path -from [get_ports {fuse_mhartid[19]}]
+set_false_path -from [get_ports {fuse_mhartid[1]}]
+set_false_path -from [get_ports {fuse_mhartid[20]}]
+set_false_path -from [get_ports {fuse_mhartid[21]}]
+set_false_path -from [get_ports {fuse_mhartid[22]}]
+set_false_path -from [get_ports {fuse_mhartid[23]}]
+set_false_path -from [get_ports {fuse_mhartid[24]}]
+set_false_path -from [get_ports {fuse_mhartid[25]}]
+set_false_path -from [get_ports {fuse_mhartid[26]}]
+set_false_path -from [get_ports {fuse_mhartid[27]}]
+set_false_path -from [get_ports {fuse_mhartid[28]}]
+set_false_path -from [get_ports {fuse_mhartid[29]}]
+set_false_path -from [get_ports {fuse_mhartid[2]}]
+set_false_path -from [get_ports {fuse_mhartid[30]}]
+set_false_path -from [get_ports {fuse_mhartid[31]}]
+set_false_path -from [get_ports {fuse_mhartid[3]}]
+set_false_path -from [get_ports {fuse_mhartid[4]}]
+set_false_path -from [get_ports {fuse_mhartid[5]}]
+set_false_path -from [get_ports {fuse_mhartid[6]}]
+set_false_path -from [get_ports {fuse_mhartid[7]}]
+set_false_path -from [get_ports {fuse_mhartid[8]}]
+set_false_path -from [get_ports {fuse_mhartid[9]}]
+set_false_path -from [get_ports {irq_lines[0]}]
+set_false_path -from [get_ports {irq_lines[10]}]
+set_false_path -from [get_ports {irq_lines[11]}]
+set_false_path -from [get_ports {irq_lines[12]}]
+set_false_path -from [get_ports {irq_lines[13]}]
+set_false_path -from [get_ports {irq_lines[14]}]
+set_false_path -from [get_ports {irq_lines[15]}]
+set_false_path -from [get_ports {irq_lines[1]}]
+set_false_path -from [get_ports {irq_lines[2]}]
+set_false_path -from [get_ports {irq_lines[3]}]
+set_false_path -from [get_ports {irq_lines[4]}]
+set_false_path -from [get_ports {irq_lines[5]}]
+set_false_path -from [get_ports {irq_lines[6]}]
+set_false_path -from [get_ports {irq_lines[7]}]
+set_false_path -from [get_ports {irq_lines[8]}]
+set_false_path -from [get_ports {irq_lines[9]}]
+set_false_path -from [get_ports {pwrup_rst_n}]
+set_false_path -from [get_ports {rst_n}]
+set_false_path -from [get_ports {soft_irq}]
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 8f6d96f..3b15b3d 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -181,60 +181,60 @@
// cfg_cpu_clk_ctrl = reg_0[23:20];
// cfg_sdram_clk_ctrl = reg_0[27:24];
// cfg_usb_clk_ctrl = reg_0[31:28];
- $display("Step-1, CPU: CLOCK1, RTC: CLOCK2/2, USB: CLOCK2, WBS:CLOCK1");
+ $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1");
test_step = 1;
- wb_user_core_write('h3080_0000,{4'h0,4'h0,4'h0,8'h0,3'b000,2'b00,7'h00});
+ wb_user_core_write('h3080_0000,{4'h0,4'h0,4'h0,8'h0,4'h0,8'h00});
clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD);
- $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK1/2");
+ $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2");
test_step = 2;
- wb_user_core_write('h3080_0000,{4'h8,4'h0,4'h8,8'h1,3'b100,2'b00,7'h00});
- clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,2*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'h8,4'h0,4'h8,8'h1,4'h8,8'h00});
+ clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD);
- $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/(2+1)");
+ $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2");
test_step = 3;
- wb_user_core_write('h3080_0000,{4'h9,4'h0,4'h4,8'h2,3'b101,2'b00,7'h00});
- clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,3*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'h9,4'h0,4'h4,8'h2,4'h4,8'h00});
+ clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD);
- $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/(2+2)");
+ $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3");
test_step = 4;
- wb_user_core_write('h3080_0000,{4'hA,4'h0,4'h5,8'h3,3'b110,2'b00,7'h00});
- clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,4*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hA,4'h0,4'h5,8'h3,4'h5,8'h00});
+ clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD);
- $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/(2+3)");
+ $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4");
test_step = 5;
- wb_user_core_write('h3080_0000,{4'hB,4'h0,4'h6,8'h4,3'b111,2'b00,7'h00});
- clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hB,4'h0,4'h6,8'h4,4'h6,8'h00});
+ clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD);
$display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)");
test_step = 6;
- wb_user_core_write('h3080_0000,{4'hC,4'h0,4'h7,8'h5,3'b111,2'b00,7'h00});
+ wb_user_core_write('h3080_0000,{4'hC,4'h0,4'h7,8'h5,4'h7,8'h00});
clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD);
- $display("Step-7, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
+ $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)");
test_step = 7;
- wb_user_core_write('h3080_0000,{4'hD,4'h0,4'h7,8'h6,3'b111,2'b00,7'h00});
- clock_monitor(5*CLK1_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hD,4'h0,4'hC,8'h6,4'hC,8'h00});
+ clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD);
- $display("Step-8, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK1/(2+3)");
+ $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3");
test_step = 8;
- wb_user_core_write('h3080_0000,{4'hE,4'h0,4'h7,8'h7,3'b111,2'b00,7'h00});
- clock_monitor(5*CLK1_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hE,4'h0,4'hD,8'h7,4'hD,8'h00});
+ clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD);
- $display("Step-9, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4");
test_step = 9;
- wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h8,3'b111,2'b00,7'h00});
- clock_monitor(5*CLK1_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hE,8'h8,4'hE,8'h00});
+ clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD);
- $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
test_step = 10;
- wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h80,3'b111,2'b00,7'h00});
- clock_monitor(5*CLK1_PERIOD,130*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hF,8'h80,4'hF,8'h00});
+ clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK2_PERIOD);
- $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+7), WBS:CLOCK2/(2+3)");
test_step = 10;
- wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'hFF,3'b111,2'b00,7'h00});
- clock_monitor(5*CLK1_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hF,8'hFF,4'hF,8'h00});
+ clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK2_PERIOD);
$display("###################################################");
$display("Monitor: Checking the chip signature :");
@@ -242,8 +242,8 @@
wb_user_core_write('h3080_0000,'h1);
wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
- wb_user_core_read_check(32'h3002005C,read_data,32'h1602_2022);
- wb_user_core_read_check(32'h30020060,read_data,32'h0003_5000);
+ wb_user_core_read_check(32'h3002005C,read_data,32'h1902_2022);
+ wb_user_core_read_check(32'h30020060,read_data,32'h0003_6000);
end
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 6c7f255..dba2b77 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -186,12 +186,15 @@
// Remove all the reset
wb_user_core_write('h3080_0000,'h1F);
- repeat (20000) @(posedge clock); // wait for Processor Get Ready
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
tb_uart.uart_init;
wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});
-
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
+
+ repeat (30000) @(posedge clock); // wait for Processor Get Ready
+
for (i=0; i<40; i=i+1)
uart_write_data[i] = $random;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index b09e18c..31b3ea7 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -721,7 +721,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h1602_2022) u_reg_23 (
+gen_32b_reg #(32'h1902_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -734,9 +734,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 3.3 = 0003500
+// Software Reg-3: Poject Revison 3.6 = 0003600
// ----------------------------------------
-gen_32b_reg #(32'h0003_5000) u_reg_24 (
+gen_32b_reg #(32'h0003_6000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index 644fc5e..f83d4c0 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim
@@ -1 +1 @@
-Subproject commit 644fc5e86bf08279ed257519456199e85d9584f9
+Subproject commit f83d4c0182dfd50f867f7cb49ec1bebc833e0a58
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 525d578..bfda0c9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -177,6 +177,16 @@
//// C. mbist controller slave port in wb_intern removed ////
//// D. Pinmux mbist port are removed ////
//// E. mbist related buffering are removed at wb_inter ////
+//// 3.6 Feb 19, Dinesh A ////
+//// A. Changed Module: wb_host ////
+//// wishbone slave clock generation config increase from ////
+//// 3 to 4 bit support clock source selection ////
+//// B. Changed Module: qspim ////
+////// 1. Bug fix in spi rise and fall pulse relation w.r.t ////
+//// spi_clk. Note: Previous version work only with ////
+//// spi clock config = 0x2 ////
+//// 2. spi_oen generation fix for different spi mode ////
+//// 3. spi_csn de-assertion fix for different spi clk div ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 4cf0005..470a421 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -156,11 +156,11 @@
logic [7:0] cfg_bank_sel;
logic [31:0] reg_0; // Software_Reg_0
-logic [2:0] cfg_wb_clk_ctrl;
+logic [3:0] cfg_wb_clk_ctrl;
logic [3:0] cfg_cpu_clk_ctrl;
logic [7:0] cfg_rtc_clk_ctrl;
logic [3:0] cfg_usb_clk_ctrl;
-logic [8:0] cfg_glb_ctrl;
+logic [7:0] cfg_glb_ctrl;
// uart Master Port
logic wbm_uart_cyc_i ; // strobe/request
@@ -373,8 +373,8 @@
//-------------------------------------
// Global + Clock Control
// -------------------------------------
-assign cfg_glb_ctrl = reg_0[8:0];
-assign cfg_wb_clk_ctrl = reg_0[11:9];
+assign cfg_glb_ctrl = reg_0[7:0];
+assign cfg_wb_clk_ctrl = reg_0[11:8];
assign cfg_rtc_clk_ctrl = reg_0[19:12];
assign cfg_cpu_clk_ctrl = reg_0[23:20];
assign cfg_usb_clk_ctrl = reg_0[31:28];
@@ -477,22 +477,28 @@
// Generate Internal WishBone Clock
//----------------------------------
logic wb_clk_div;
+logic wbs_ref_clk;
+logic cfg_wb_clk_src_sel;
logic cfg_wb_clk_div;
logic [1:0] cfg_wb_clk_ratio;
-assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0];
-assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2];
+assign cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[3];
+assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2];
+assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0];
+//assign wbs_ref_clk = (cfg_wb_clk_src_sel) ? user_clock2 : user_clock1;
+ctech_mux2x1 u_wbs_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S (cfg_wb_clk_src_sel), .X (wbs_ref_clk));
+
//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
-ctech_mux2x1 u_wbs_clk_sel (.A0 (wbm_clk_i), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out));
+ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out));
clk_ctl #(1) u_wbclk (
// Outputs
.clk_o (wb_clk_div ),
// Inputs
- .mclk (wbm_clk_i ),
+ .mclk (wbs_ref_clk ),
.reset_n (wbm_rst_n ),
.clk_div_ratio (cfg_wb_clk_ratio )
);
