floor planning cleanup
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
new file mode 100644
index 0000000..d57972b
--- /dev/null
+++ b/openlane/glbl_cfg/base.sdc
@@ -0,0 +1,62 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "mclk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {reset_n}
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_cs*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wr*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_addr*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wdata*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_be*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
+
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port device_idcode*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_rdata*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_ack*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port fuse_mhartid*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port irq_lines*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port soft_irq*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port user_irq*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_width*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_colbits*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+## These are generated clock, only max delay added
+set_false_path -to [get_port sdram_clk]
+set_false_path -to [get_port cpu_clk]
+set_false_path -to [get_port rtc_clk]
+
+#set_max_delay 2.0 [get_port sdram_clk]
+#set_max_delay 2.0 [get_port cpu_clk]
+#set_max_delay 2.0 [get_port rtc_clk]
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index d55458c..d17529f 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -12,6 +12,7 @@
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "mclk"
+set ::env(SYNTH_MAX_FANOUT) 4
# Sources
# -------
@@ -23,9 +24,8 @@
$script_dir/../../verilog/rtl/digital_core/src/glbl_cfg.sv \
"
-
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
# Floorplanning
@@ -33,11 +33,29 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(CELL_PAD) 0
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 300"
+
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
set ::env(GLB_RT_MAXLAYER) 5
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 300 300"
-set ::env(PL_TARGET_DENSITY) 0.3
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/glbl_cfg/pdn.tcl b/openlane/glbl_cfg/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/glbl_cfg/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
index 824a990..784fe9b 100644
--- a/openlane/glbl_cfg/pin_order.cfg
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -1,16 +1,21 @@
#BUS_SORT
#E
-mclk
-reset_n
-events_o.*
+cpu_clk
+rtc_clk
cpu_rst_n
-spi_rst_n
-device_idcode.*
-fuse_mhartid.*
irq_lines.*
soft_irq
+fuse_mhartid.*
+#N
+mclk
+reset_n
+user_clock2
+spi_rst_n
+user_irq.*
+events_o.*
+device_idcode.*
#W
sdram_clk
@@ -31,7 +36,7 @@
cfg_sdr_rfmax.*
-#N
+#S
reg_cs
reg_wr
reg_addr.*
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
new file mode 100644
index 0000000..9fd9ca2
--- /dev/null
+++ b/openlane/sdram/base.sdc
@@ -0,0 +1,84 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "wb_clk_i"
+
+set ::env(SDRAM_CLOCK_PERIOD) "20"
+set ::env(SDRAM_CLOCK_PORT) "sdram_clk"
+
+set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
+set ::env(PAD_SDRAM_CLOCK_PORT) "sdram_pad_clk"
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+
+set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_sel_i*]
+set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfmax*]
+
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_o*]
+set_output_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
+
+######################################
+# SDRAM Clock domain input output
+######################################
+create_clock [get_ports $::env(SDRAM_CLOCK_PORT)] -name $::env(SDRAM_CLOCK_PORT) -period $::env(SDRAM_CLOCK_PERIOD)
+set sdram_input_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
+set sdram_output_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cke*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cs_n*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ras_n*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cas_n*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_we_n*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dqm*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ba*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_addr*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dout*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_den_n*]
+
+################################################
+# PAD SDRAM Clock domain input output
+# Note: PAD SDRAM clock is same as SDRAM clock
+# it's a feedback clock through pads
+################################################
+
+create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)] -name $::env(PAD_SDRAM_CLOCK_PORT) -period $::env(SDRAM_CLOCK_PERIOD)
+set_input_delay $sdram_input_delay_value -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port pad_sdr_din*]
+
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)]
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index e8c1c22..796a40c 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -5,20 +5,11 @@
# Name
set ::env(DESIGN_NAME) sdrc_top
-# This is macro
-set ::env(DESIGN_IS_CORE) 0
-# Diode insertion
- # Spray
-set ::env(DIODE_INSERTION_STRATEGY) 0
-
- # Smart-"ish"
-#set ::env(DIODE_INSERTION_STRATEGY) 3
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PORT) "wb_clk_i sdram_clk sdram_pad_clk"
# Sources
@@ -38,84 +29,38 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
# Floorplanning
# -------------
-# Fixed area and pin position
-set ::env(FP_SIZING) "absolute"
-#actual die area is 0 0 2920 3520, given 500 micron extra margin
-set ::env(DIE_AREA) [list 0.0 0.0 1000.0 300.0]
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-# Halo around the Macros
-set ::env(FP_HORIZONTAL_HALO) 25
-set ::env(FP_VERTICAL_HALO) 20
-
-#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) [list 0.0 0.0 900.0 300.0]
-# Placement
-# ---------
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
-#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
-
-# Routing
-# -------
-
-#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
-set ::env(ROUTING_CORES) 4
-
-#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-
-# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
-set ::env(GLB_RT_MINLAYER) 1
-
-# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
set ::env(GLB_RT_MAXLAYER) 5
-# Obstructions
- # li1 over the SRAM areas
- # met5 over the whole design
-#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
-
-#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
-set ::env(ROUTING_OPT_ITERS) "64"
-
-#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
-set ::env(GLOBAL_ROUTER) "fastroute"
-
-#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
-set ::env(DETAILED_ROUTER) "tritonroute"
-
-# DRC
-# ---
+set ::env(DIODE_INSERTION_STRATEGY) 4
-set ::env(MAGIC_DRC_USE_GDS) 1
-
-
-# Tape Out
-# --------
-
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-
-# Cell library specific config
-# ----------------------------
-
-set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
-if { [file exists $filename] == 1} {
- source $filename
-}
diff --git a/openlane/sdram/pdn.tcl b/openlane/sdram/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/sdram/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/sdram/pin_order.cfg b/openlane/sdram/pin_order.cfg
index b404027..52236e6 100644
--- a/openlane/sdram/pin_order.cfg
+++ b/openlane/sdram/pin_order.cfg
@@ -1,29 +1,30 @@
#BUS_SORT
-#E
-wb_clk_i,
-wb_rst_i,
+#W
+wb_clk_i
+wb_rst_i
-#S
-sdr_cas_n,
-sdr_cke,
-sdr_cs_n,
-sdr_dqm,
-sdr_ras_n,
-sdr_we_n,
+#N
+sdr_cas_n
+sdr_cke
+sdr_cs_n
+sdr_dqm
+sdr_ras_n
+sdr_we_n
sdr_addr.*
sdr_ba.*
pad_sdr_din.*
sdr_dout.*
-sdr_den_n,
-sdram_pad_clk,
+sdr_den_n
+sdram_pad_clk
#E
-sdram_clk,
-sdram_resetn
+sdram_clk
+sdram_resetn
+sdr_init_done
cfg_sdr_width.*
cfg_colbits.*
cfg_sdr_tras_d.*
@@ -39,13 +40,13 @@
cfg_sdr_rfmax.*
-#N
-wb_stb_i,
-wb_we_i,
+#S
+wb_stb_i
+wb_we_i
wb_addr_i.*
wb_sel_i.*
wb_dat_i.*
wb_dat_o.*
-wb_ack_o,
+wb_ack_o
wb_cyc_i,
wb_cti_i.*
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
new file mode 100644
index 0000000..af8edee
--- /dev/null
+++ b/openlane/spi_master/base.sdc
@@ -0,0 +1,50 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "mclk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {rst_n}
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_stb_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_adr_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_we_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi0*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi1*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi2*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi3*]
+
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port events_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_clk*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn0*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn1*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn3*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_mode*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo0*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo1*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo2*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo3*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_en_tx*]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index da709bb..584bda3 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -3,15 +3,14 @@
set script_dir [file dirname [file normalize [info script]]]
# Name
-set ::env(DESIGN_NAME) spim_top
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(DESIGN_NAME) spim_top
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "mclk"
+set ::env(SYNTH_MAX_FANOUT) 4
# Sources
# -------
@@ -25,13 +24,8 @@
$script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
$script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv "
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
-
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
# Floorplanning
@@ -39,14 +33,29 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(CELL_PAD) 0
-
-set ::env(GLB_RT_MAXLAYER) 5
-
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 600 500"
-set ::env(PL_TARGET_DENSITY) 0.4
-set ::env(BOTTOM_MARGIN_MULT) 2
-set ::env(TOP_MARGIN_MULT) 2
-set ::env(LEFT_MARGIN_MULT) 15
-set ::env(RIGHT_MARGIN_MULT) 15
+
+
+
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/spi_master/pdn.tcl b/openlane/spi_master/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/spi_master/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index afd59ee..23b1cf5 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -24,7 +24,7 @@
spi_sdo3
-#N
+#S
wbd_stb_i
wbd_we_i
wbd_adr_i.*
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
new file mode 100644
index 0000000..0bb30a6
--- /dev/null
+++ b/openlane/syntacore/base.sdc
@@ -0,0 +1,49 @@
+set_units -time ns
+#Wishbone Clock
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "wb_clk"
+
+#Risc Core Clock
+set ::env(CORE_CLOCK_PERIOD) "50"
+set ::env(CORE_CLOCK_PORT) "core_clk"
+
+######################################
+# CORE Clock domain input output
+######################################
+create_clock [get_ports $::env(CORE_CLOCK_PORT)] -name $::env(CORE_CLOCK_PORT) -period $::env(CORE_CLOCK_PERIOD)
+set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
+puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
+set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_PORT)]]
+set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
+set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
+set all_outputs_core [all_outputs]
+
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_inputs_wo_core_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_PORT)] {cpu_rst_n}
+set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_outputs_core
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_PORT)]]
+set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
+set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
+set all_outputs_wb [all_outputs]
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_inputs_wo_wb_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_outputs_wb
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 91e5913..994b399 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -8,9 +8,10 @@
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# Timing configuration
-set ::env(CLOCK_PERIOD) "50"
-set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk core_clk"
+set ::env(SYNTH_MAX_FANOUT) 4
# Sources
# -------
@@ -44,66 +45,45 @@
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \
- $script_dir/../../verilog/rtl/lib/sync_fifo.sv "
+ $script_dir/../../verilog/rtl/lib/async_fifo.sv "
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
+# --------
# Floorplanning
# -------------
-# Fixed area and pin position
-set ::env(FP_SIZING) "absolute"
-#actual die area is 0 0 2920 3520, given 500 micron extra margin
+set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
+#set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) [list 0.0 0.0 1500.0 1200.0]
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-# Placement
-# ---------
-
-set ::env(PL_TARGET_DENSITY) 0.40
-# Routing
-# -------
-#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
-set ::env(ROUTING_CORES) 4
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
-#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
-# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
-set ::env(GLB_RT_MINLAYER) 1
-
-# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
set ::env(GLB_RT_MAXLAYER) 5
-# Obstructions
- # li1 over the SRAM areas
- # met5 over the whole design
-#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
-
-#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
-set ::env(ROUTING_OPT_ITERS) "64"
-
-#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
-set ::env(GLOBAL_ROUTER) "fastroute"
-
-#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
-set ::env(DETAILED_ROUTER) "tritonroute"
-
-# DRC
-# ---
-
-
-set ::env(MAGIC_DRC_USE_GDS) 1
-
-
-# Tape Out
-# --------
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/syntacore/pdn.tcl b/openlane/syntacore/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/syntacore/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 398de52..a854d55 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -1,41 +1,34 @@
#BUS_SORT
#E
-clk
+core_clk
+rtc_clk
cpu_rst_n
irq_lines.*
-pwrup_rst_n
-rst_n
-rtc_clk
soft_irq
-sys_rdc_qlfy_o
-sys_rst_n_o
-fuse_idcode.*
fuse_mhartid.*
#W
-tck
-tdi
-tdo
-tdo_en
-test_mode
-test_rst_n
-tms
-trst_n
+wb_clk
+wb_rst_n
+pwrup_rst_n
+rst_n
+sys_rdc_qlfy_o
+sys_rst_n_o
-#S
+#N
wbd_imem_stb_o
wbd_imem_we_o
wbd_imem_adr_o.*
-wbd_imem_sel_o
+wbd_imem_sel_o.*
wbd_imem_dat_o.*
wbd_imem_dat_i.*
wbd_imem_ack_i
wbd_imem_err_i
wbd_dmem_stb_o
-wbd_dmem_adr_o.*
wbd_dmem_we_o
-wbd_dmem_sel_o
+wbd_dmem_adr_o.*
+wbd_dmem_sel_o.*
wbd_dmem_dat_o.*
wbd_dmem_dat_i.*
wbd_dmem_ack_i
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
new file mode 100644
index 0000000..97e8ab3
--- /dev/null
+++ b/openlane/user_project_wrapper/base.sdc
@@ -0,0 +1,56 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "wb_clk_i"
+
+set ::env(SDRAM_CLOCK_PERIOD) "20"
+set ::env(SDRAM_CLOCK_PORT) "digital_core.u_glbl_cfg.sdram_clk"
+
+set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
+set ::env(PAD_SDRAM_CLOCK_PORT) "digital_core.u_sdram_ctrl.sdram_pad_clk"
+
+set ::env(CPU_CLOCK_PERIOD) "50"
+set ::env(CPU_CLOCK_PORT) "digital_core.u_glbl_cfg.cpu_clk"
+
+set ::env(RTC_CLOCK_PERIOD) "50"
+set ::env(RTC_CLOCK_PORT) "digital_core.u_glbl_cfg.rtc_clk"
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_stb_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_cyc_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_we_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_sel_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_adr_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_o*]
+set_output_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_ack_o*]
+
+######################################
+# SDRAM Clock domain input output
+######################################
+create_clock [get_pins (SDRAM_CLOCK_PORT)] -name $::env(SDRAM_CLOCK_PORT) -period $::env(SDRAM_CLOCK_PERIOD)
+create_clock [get_pins (PAD_SDRAM_CLOCK_PORT)] -name $::env(PAD_SDRAM_CLOCK_PORT) -period $::env(PAD_SDRAM_CLOCK_PERIOD)
+create_clock [get_pins (CPU_CLOCK_PORT)] -name $::env(CPU_CLOCK_PORT) -period $::env(CPU_CLOCK_PERIOD)
+create_clock [get_pins (RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_PORT) -period $::env(RTC_CLOCK_PERIOD)
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)] -group [get_clocks $::env(CPU_CLOCK_PORT)] -group [get_clocks $::env(RTC_CLOCK_PORT)]
+
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index b2f933a..04ea174 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -44,6 +44,10 @@
set ::env(FP_SIZING) "absolute"
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../verilog/rtl/spi_master/src/spim_top.sv \
@@ -79,19 +83,22 @@
# The following is because there are no std cells in the example wrapper project.
#set ::env(SYNTH_TOP_LEVEL) 1
-#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FILL_INSERTION) 1
+set ::env(TAP_DECAP_INSERTION) 1
+#set ::env(CLOCK_TREE_SYNTH) 1
# Important for large macro placement
set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
set ::env(ROUTING_OPT_ITERS) "20"
+set ::env(GLB_RT_OBS) "met5 0.0 0.0 2920.0 3520.0"
+
+
diff --git a/openlane/user_project_wrapper/macro/bb/syntacore.v b/openlane/user_project_wrapper/macro/bb/syntacore.v
index 1eb131f..4e1c7db 100644
--- a/openlane/user_project_wrapper/macro/bb/syntacore.v
+++ b/openlane/user_project_wrapper/macro/bb/syntacore.v
@@ -1,4 +1,4 @@
-module scr1_top_wb (clk,
+module scr1_top_wb (core_clk,
cpu_rst_n,
pwrup_rst_n,
rst_n,
@@ -6,6 +6,8 @@
soft_irq,
test_mode,
test_rst_n,
+ wb_clk,
+ wb_rst_n,
wbd_dmem_ack_i,
wbd_dmem_err_i,
wbd_dmem_stb_o,
@@ -26,7 +28,7 @@
wbd_imem_dat_i,
wbd_imem_dat_o,
wbd_imem_sel_o);
- input clk;
+ input core_clk;
input cpu_rst_n;
input pwrup_rst_n;
input rst_n;
@@ -34,6 +36,8 @@
input soft_irq;
input test_mode;
input test_rst_n;
+ input wb_clk;
+ input wb_rst_n;
input wbd_dmem_ack_i;
input wbd_dmem_err_i;
output wbd_dmem_stb_o;
diff --git a/openlane/user_project_wrapper/macro_placement.cfg b/openlane/user_project_wrapper/macro_placement.cfg
index 61d036a..bc62704 100644
--- a/openlane/user_project_wrapper/macro_placement.cfg
+++ b/openlane/user_project_wrapper/macro_placement.cfg
@@ -1,5 +1,5 @@
-u_core.u_riscv_top 300 1800 N
-u_core.u_intercon 300 1200 N
-u_core.u_sdram_ctrl 1100 500 N
-u_core.u_glbl_cfg 2300 500 N
-u_core.u_spi_master 200 300 N
+u_core.u_riscv_top 300 300 N
+u_core.u_intercon 300 1800 N
+u_core.u_spi_master 300 2500 N
+u_core.u_sdram_ctrl 1000 2500 N
+u_core.u_glbl_cfg 2000 2500 N
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
new file mode 100644
index 0000000..1ef8a54
--- /dev/null
+++ b/openlane/wb_interconnect/base.sdc
@@ -0,0 +1,27 @@
+set_units -time ns
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk_i"
+
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+
+set input_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+set rst_indx [lsearch [all_inputs] [get_port rst_n]]
+set all_inputs_wo_clk_rst [lreplace [all_inputs] $clk_indx $rst_indx]
+
+
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+set_input_delay 2.0 -clock [get_clocks $::env(CLOCK_PORT)] {rst_n}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index d58ffe7..3cbb6cb 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -4,7 +4,6 @@
set script_dir [file dirname [file normalize [info script]]]
# Name
set ::env(DESIGN_NAME) wb_interconnect
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -12,50 +11,55 @@
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "clk_i"
+set ::env(SYNTH_MAX_FANOUT) 4
# Sources
# -------
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/lib/wb_stagging.sv \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
"
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
# Floorplanning
# -------------
+#set ::env(PL_BASIC_PLACEMENT) 1
+#set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(CELL_PAD) 0
-
-set ::env(FP_PDN_LOWER_LAYER) met2
-set ::env(FP_PDN_UPPER_LAYER) met3
-set ::env(FP_PDN_AUTO_ADJUST) 0
-set ::env(FP_PDN_VWIDTH) 0.3
-set ::env(FP_PDN_HWIDTH) 0.3
-set ::env(FP_PDN_CORE_RING_VSPACING) 0.4
-set ::env(FP_PDN_CORE_RING_HSPACING) 0.4
-set ::env(FP_PDN_VOFFSET) 10
-set ::env(FP_PDN_HOFFSET) 1
-set ::env(FP_PDN_VWIDTH) 0.3
-set ::env(FP_PDN_HWIDTH) 0.3
-set ::env(FP_PDN_VPITCH) 80
-set ::env(FP_PDN_HPITCH) 10.8
-
-set ::env(GLB_RT_MAXLAYER) 4
-
-set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2300 100"
-set ::env(PL_TARGET_DENSITY) 0.9
-set ::env(BOTTOM_MARGIN_MULT) 2
-set ::env(TOP_MARGIN_MULT) 2
-set ::env(LEFT_MARGIN_MULT) 15
-set ::env(RIGHT_MARGIN_MULT) 15
+set ::env(DIE_AREA) "0 0 2400 150"
+
+
+
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.32
+set ::env(PL_TARGET_DENSITY_CELLS) 0.2
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/wb_interconnect/pdn.tcl b/openlane/wb_interconnect/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/wb_interconnect/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 08ef088..ffc604a 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -5,7 +5,7 @@
rst_n
-#N
+#S
m0_wbd_stb_i
m0_wbd_we_i
m0_wbd_adr_i.*
@@ -36,7 +36,7 @@
m2_wbd_err_o
m2_wbd_cyc_i
-#S
+#N
s0_wbd_stb_o
s0_wbd_we_o
s0_wbd_adr_o.*
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 7ae0a6b..41fbf83 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -22,6 +22,24 @@
//// 0.1 - 16th Feb 2021, Dinesh A ////
//// Initial integration with Risc-V core + ////
//// Wishbone Cross Bar + SPI Master ////
+//// 0.2 - 17th June 2021, Dinesh A ////
+//// 1. In risc core, wishbone and core domain is ////
+//// created ////
+//// 2. cpu and rtc clock are generated in glbl reg block ////
+//// 3. in wishbone interconnect:- Stagging flop are added ////
+//// at interface to break wishbone timing path ////
+//// 4. buswidth warning are fixed inside spi_master ////
+//// modified rtl files are ////
+//// verilog/rtl/digital_core/src/digital_core.sv ////
+/// verilog/rtl/digital_core/src/glbl_cfg.sv ////
+/// verilog/rtl/lib/wb_stagging.sv ////
+/// verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv ////
+/// verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv ////
+/// verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv ////
+/// verilog/rtl/user_project_wrapper.v ////
+/// verilog/rtl/wb_interconnect/src/wb_interconnect.sv ////
+/// verilog/rtl/spi_master/src/spim_clkgen.sv ////
+/// verilog/rtl/spi_master/src/spim_ctrl.sv ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -161,7 +179,7 @@
// Global Register Wishbone Interface
//---------------------------------------------------------------------
logic wbd_glbl_stb_o; // strobe/request
-logic [WB_WIDTH-1:0] wbd_glbl_adr_o; // address
+logic [7:0] wbd_glbl_adr_o; // address
logic wbd_glbl_we_o; // write
logic [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
logic [3:0] wbd_glbl_sel_o; // byte enable
@@ -543,7 +561,7 @@
// Reg Bus Interface Signal
.reg_cs (wbd_glbl_stb_o ),
.reg_wr (wbd_glbl_we_o ),
- .reg_addr (wbd_glbl_adr_o[5:2] ),
+ .reg_addr (wbd_glbl_adr_o ),
.reg_wdata (wbd_glbl_dat_o ),
.reg_be (wbd_glbl_sel_o ),
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index 22e68c5..1754aec 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -55,7 +55,7 @@
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
- input logic [3:0] reg_addr,
+ input logic [7:0] reg_addr,
input logic [31:0] reg_wdata,
input logic [3:0] reg_be,
@@ -152,7 +152,7 @@
reg_cs_l <= '0;
reg_cs_2l <= '0;
end else begin
- sw_addr <= reg_addr [3:0];
+ sw_addr <= reg_addr [5:2];
sw_rd_en <= reg_cs & !reg_wr;
sw_wr_en <= reg_cs & reg_wr;
sw_reg_wdata <= reg_wdata;
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv
new file mode 100755
index 0000000..5ff3df6
--- /dev/null
+++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -0,0 +1,386 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// ////
+//// Description ////
+//// Async Fifo with threshold tracking/status ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+//-------------------------------------------
+// async_fifo:: async FIFO
+// Following two ports are newly added
+// 1. At write clock domain:
+// wr_total_free_space --> Indicate total free transfer available
+// 2. At read clock domain:
+// rd_total_aval --> Indicate total no of transfer available
+//-----------------------------------------------
+
+module async_fifo_th (
+ wr_clk,
+ wr_reset_n,
+ wr_en,
+ wr_data,
+ full, // sync'ed to wr_clk
+ afull, // sync'ed to wr_clk
+ wr_total_free_space,
+ rd_clk,
+ rd_reset_n,
+ rd_en,
+ empty, // sync'ed to rd_clk
+ aempty, // sync'ed to rd_clk
+ rd_total_aval,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
+ rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+ output [AW:0] wr_total_free_space; // Total Number of free space aval
+ // w.r.t write clk
+ // note: Without accounting byte enables
+ output [AW:0] rd_total_aval; // Total Number of words avaialble
+ // w.r.t rd clock,
+ // note: Without accounting byte enables
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
+ wire [AW:0] sync_rd_ptr;
+ reg [AW:0] wr_ptr, grey_wr_ptr;
+ reg [AW:0] grey_rd_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+ //--------------------------
+ // Shows total number of words
+ // of free space available w.r.t write clock
+ //---------------------------
+ assign wr_total_free_space = FULL_DP - wr_cnt;
+
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ wr_ptr <= 0;
+ grey_wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ grey_wr_ptr <= bin2grey(wr_ptr_inc);
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge wr_clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+ wire [AW:0] grey_rd_ptr_dly ;
+ assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+
+ // read pointer synchronizer
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ sync_rd_ptr_0 <= 0;
+ sync_rd_ptr_1 <= 0;
+ end
+ else begin
+ sync_rd_ptr_0 <= grey_rd_ptr_dly;
+ sync_rd_ptr_1 <= sync_rd_ptr_0;
+ end
+ end
+
+ assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
+
+ /************************ read side *****************************/
+ reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
+ wire [AW:0] sync_wr_ptr;
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+ //--------------------------
+ // Shows total number of words
+ // space available w.r.t write clock
+ //---------------------------
+ assign rd_total_aval = rd_cnt;
+
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ rd_ptr <= 0;
+ grey_rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ grey_rd_ptr <= bin2grey(rd_ptr_inc);
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ assign rd_data = mem[rd_ptr[AW-1:0]];
+
+ wire [AW:0] grey_wr_ptr_dly ;
+ assign #1 grey_wr_ptr_dly = grey_wr_ptr;
+
+ // write pointer synchronizer
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ sync_wr_ptr_0 <= 0;
+ sync_wr_ptr_1 <= 0;
+ end
+ else begin
+ sync_wr_ptr_0 <= grey_wr_ptr_dly;
+ sync_wr_ptr_1 <= sync_wr_ptr_0;
+ end
+ end
+ assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
+
+
+/************************ functions ******************************/
+function [AW:0] bin2grey;
+input [AW:0] bin;
+reg [8:0] bin_8;
+reg [8:0] grey_8;
+begin
+ bin_8 = bin;
+ grey_8[1:0] = do_grey(bin_8[2:0]);
+ grey_8[3:2] = do_grey(bin_8[4:2]);
+ grey_8[5:4] = do_grey(bin_8[6:4]);
+ grey_8[7:6] = do_grey(bin_8[8:6]);
+ grey_8[8] = bin_8[8];
+ bin2grey = grey_8;
+end
+endfunction
+
+function [AW:0] grey2bin;
+input [AW:0] grey;
+reg [8:0] grey_8;
+reg [8:0] bin_8;
+begin
+ grey_8 = grey;
+ bin_8[8] = grey_8[8];
+ bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
+ bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
+ bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
+ bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
+ grey2bin = bin_8;
+end
+endfunction
+
+
+function [1:0] do_grey;
+input [2:0] bin;
+begin
+ if (bin[2]) begin // do reverse grey
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b10;
+ 2'b01: do_grey = 2'b11;
+ 2'b10: do_grey = 2'b01;
+ 2'b11: do_grey = 2'b00;
+ endcase
+ end
+ else begin
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b00;
+ 2'b01: do_grey = 2'b01;
+ 2'b10: do_grey = 2'b11;
+ 2'b11: do_grey = 2'b10;
+ endcase
+ end
+end
+endfunction
+
+function [1:0] do_bin;
+input [2:0] grey;
+begin
+ if (grey[2]) begin // actually bin[2]
+ case (grey[1:0])
+ 2'b10: do_bin = 2'b00;
+ 2'b11: do_bin = 2'b01;
+ 2'b01: do_bin = 2'b10;
+ 2'b00: do_bin = 2'b11;
+ endcase
+ end
+ else begin
+ case (grey[1:0])
+ 2'b00: do_bin = 2'b00;
+ 2'b01: do_bin = 2'b01;
+ 2'b11: do_bin = 2'b10;
+ 2'b10: do_bin = 2'b11;
+ endcase
+ end
+end
+endfunction
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge wr_clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge rd_clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+
+// gray code monitor
+reg [AW:0] last_gwr_ptr;
+always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ last_gwr_ptr <= #1 0;
+ end
+ else if (last_gwr_ptr !== grey_wr_ptr) begin
+ check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
+ last_gwr_ptr <= #1 grey_wr_ptr;
+ end
+end
+
+reg [AW:0] last_grd_ptr;
+always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ last_grd_ptr <= #1 0;
+ end
+ else if (last_grd_ptr !== grey_rd_ptr) begin
+ check_ptr_chg(last_grd_ptr, grey_rd_ptr);
+ last_grd_ptr <= #1 grey_rd_ptr;
+ end
+end
+
+task check_ptr_chg;
+input [AW:0] last_ptr;
+input [AW:0] cur_ptr;
+integer i;
+integer ptr_diff;
+begin
+ ptr_diff = 0;
+ for (i=0; i<= AW; i=i+ 1'b1) begin
+ if (last_ptr[i] != cur_ptr[i]) begin
+ ptr_diff = ptr_diff + 1'b1;
+ end
+ end
+ if (ptr_diff !== 1) begin
+ $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
+ last_ptr, cur_ptr);
+ $stop;
+ end
+end
+endtask
+ // synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/double_sync_high.v b/verilog/rtl/lib/double_sync_high.v
new file mode 100755
index 0000000..8e39520
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_high.v
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// ////
+//// Description ////
+//// OMS 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 0
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_high (
+ in_data ,
+ out_clk ,
+ out_rst_n ,
+ out_data
+ );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0] in_data ; // Input from Different clock domain
+input out_clk ; // Output clock
+input out_rst_n ; // Active low Reset
+output[WIDTH-1:0] out_data ; // Output Data
+
+
+reg [WIDTH-1:0] in_data_s ; // One Cycle sync
+reg [WIDTH-1:0] in_data_2s ; // two Cycle sync
+reg [WIDTH-1:0] in_data_3s ; // three Cycle sync
+
+assign out_data = in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+ if(out_rst_n == 1'b0)
+ begin
+ in_data_s <= {WIDTH{1'b0}};
+ in_data_2s <= {WIDTH{1'b0}};
+ in_data_3s <= {WIDTH{1'b0}};
+ end
+ else
+ begin
+ in_data_s <= in_data;
+ in_data_2s <= in_data_s;
+ in_data_3s <= in_data_2s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/double_sync_low.v b/verilog/rtl/lib/double_sync_low.v
new file mode 100755
index 0000000..2709b91
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_low.v
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// ////
+//// Description ////
+//// OMS 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 1
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_low (
+ in_data ,
+ out_clk ,
+ out_rst_n ,
+ out_data
+ );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0] in_data ; // Input from Different clock domain
+input out_clk ; // Output clock
+input out_rst_n ; // Active low Reset
+output[WIDTH-1:0] out_data ; // Output Data
+
+
+reg [WIDTH-1:0] in_data_s ; // One Cycle sync
+reg [WIDTH-1:0] in_data_2s ; // two Cycle sync
+reg [WIDTH-1:0] in_data_3s ; // three Cycle sync
+
+assign out_data = in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+ if(out_rst_n == 1'b0)
+ begin
+ in_data_s <= {WIDTH{1'b1}};
+ in_data_2s <= {WIDTH{1'b1}};
+ in_data_3s <= {WIDTH{1'b1}};
+ end
+ else
+ begin
+ in_data_s <= in_data;
+ in_data_2s <= in_data_s;
+ in_data_3s <= in_data_2s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv
index 7c1330a..5fce5f1 100644
--- a/verilog/rtl/lib/wb_stagging.sv
+++ b/verilog/rtl/lib/wb_stagging.sv
@@ -66,6 +66,7 @@
input logic m_wbd_we_i,
input logic m_wbd_cyc_i,
input logic m_wbd_stb_i,
+ input logic [3:0] m_wbd_tid_i,
output logic [31:0] m_wbd_dat_o,
output logic m_wbd_ack_o,
output logic m_wbd_err_o,
@@ -79,7 +80,8 @@
output logic [3:0] s_wbd_sel_o,
output logic s_wbd_we_o,
output logic s_wbd_cyc_o,
- output logic s_wbd_stb_o
+ output logic s_wbd_stb_o,
+ output logic [3:0] s_wbd_tid_o
);
@@ -90,6 +92,7 @@
logic m_wbd_we_i_ff ; // Flopped vesion of m_wbd_we_i
logic m_wbd_cyc_i_ff ; // Flopped vesion of m_wbd_cyc_i
logic m_wbd_stb_i_ff ; // Flopped vesion of m_wbd_stb_i
+logic [3:0] m_wbd_tid_i_ff ; // Flopped vesion of m_wbd_tid_i
logic [31:0] s_wbd_dat_i_ff ; // Flopped vesion of s_wbd_dat_i
logic s_wbd_ack_i_ff ; // Flopped vesion of s_wbd_ack_i
logic s_wbd_err_i_ff ; // Flopped vesion of s_wbd_err_i
@@ -101,6 +104,7 @@
assign s_wbd_we_o = m_wbd_we_i_ff;
assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
assign s_wbd_stb_o = m_wbd_stb_i_ff;
+assign s_wbd_tid_o = m_wbd_tid_i_ff;
assign m_wbd_dat_o = s_wbd_dat_i_ff;
assign m_wbd_ack_o = s_wbd_ack_i_ff;
@@ -116,10 +120,11 @@
m_wbd_we_i_ff <= 'h0;
m_wbd_cyc_i_ff <= 'h0;
m_wbd_stb_i_ff <= 'h0;
+ m_wbd_tid_i_ff <= 'h0;
s_wbd_dat_i_ff <= 'h0;
s_wbd_ack_i_ff <= 'h0;
s_wbd_err_i_ff <= 'h0;
- end begin
+ end else begin
s_wbd_dat_i_ff <= s_wbd_dat_i;
s_wbd_ack_i_ff <= s_wbd_ack_i;
s_wbd_err_i_ff <= s_wbd_err_i;
@@ -131,6 +136,7 @@
m_wbd_we_i_ff <= m_wbd_we_i;
m_wbd_cyc_i_ff <= m_wbd_cyc_i;
m_wbd_stb_i_ff <= m_wbd_stb_i;
+ m_wbd_tid_i_ff <= m_wbd_tid_i;
end else if (holding_busy && s_wbd_ack_i) begin
holding_busy <= 1'b0;
m_wbd_dat_i_ff <= 'h0;
@@ -139,6 +145,7 @@
m_wbd_we_i_ff <= 'h0;
m_wbd_cyc_i_ff <= 'h0;
m_wbd_stb_i_ff <= 'h0;
+ m_wbd_tid_i_ff <= 'h0;
end
end
end
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 0128568..cfb8ead 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -227,6 +227,7 @@
end
end
+ wire [3:0] reg_addr = spim_wb_addr[5:2];
integer byte_index;
always_ff @(negedge rst_n or posedge mclk) begin
if ( rst_n == 1'b0 ) begin
@@ -328,7 +329,7 @@
endcase
end else if (spim_reg_req & spim_wb_we )
begin
- case(spim_wb_addr[7:4])
+ case(reg_addr)
REG_CTRL:
begin
if ( spim_wb_be[0] == 1 )
@@ -398,8 +399,6 @@
- wire [3:0] reg_addr = spim_wb_addr[7:4];
-
// implement slave model register read mux
always_comb
begin
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index b127d5c..a477c94 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -107,7 +107,7 @@
grant2:
// if this req is dropped or next is asserted, check for other req's
if(!req[2] ) begin
- if(req[0]) next_state = grant0;
+ if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
end
endcase
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index b2e1df2..3eb688e 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -115,7 +115,7 @@
input logic s2_wbd_ack_i,
input logic s2_wbd_err_i,
output logic [31:0] s2_wbd_dat_o,
- output logic [31:0] s2_wbd_adr_o,
+ output logic [7:0] s2_wbd_adr_o, // glbl reg need only 8 bits
output logic [3:0] s2_wbd_sel_o,
output logic s2_wbd_we_o,
output logic s2_wbd_cyc_o,
@@ -168,9 +168,11 @@
type_wb_rd_intf s2_wb_rd;
-type_wb_wr_intf i_bus_m; // Multiplexed Master I/F
-type_wb_rd_intf i_bus_s; // Multiplexed Slave I/F
+type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F
+type_wb_rd_intf m_bus_rd; // Multiplexed Slave I/F
+type_wb_wr_intf s_bus_wr; // Multiplexed Master I/F
+type_wb_rd_intf s_bus_rd; // Multiplexed Slave I/F
//------------------------------
// RISC Data Memory Map
// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
@@ -245,38 +247,38 @@
// Slave Mapping
// -------------------------------------
// Masked Now and added stagging FF now
-// assign s0_wbd_dat_o = s0_wb_wr.wbd_dat ;
-// assign s0_wbd_adr_o = s0_wb_wr.wbd_adr ;
-// assign s0_wbd_sel_o = s0_wb_wr.wbd_sel ;
-// assign s0_wbd_we_o = s0_wb_wr.wbd_we ;
-// assign s0_wbd_cyc_o = s0_wb_wr.wbd_cyc ;
-// assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
-//
-// assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
-// assign s1_wbd_adr_o = s1_wb_wr.wbd_adr ;
-// assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
-// assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
-// assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
-// assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
-//
-// assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
-// assign s2_wbd_adr_o = s2_wb_wr.wbd_adr ;
-// assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
-// assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
-// assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
-// assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ;
-//
-// assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
-// assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
-// assign s0_wb_rd.wbd_err = s0_wbd_err_i ;
-//
-// assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ;
-// assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ;
-// assign s1_wb_rd.wbd_err = s1_wbd_err_i ;
-//
-// assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ;
-// assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ;
-// assign s2_wb_rd.wbd_err = s2_wbd_err_i ;
+ assign s0_wbd_dat_o = s0_wb_wr.wbd_dat ;
+ assign s0_wbd_adr_o = s0_wb_wr.wbd_adr ;
+ assign s0_wbd_sel_o = s0_wb_wr.wbd_sel ;
+ assign s0_wbd_we_o = s0_wb_wr.wbd_we ;
+ assign s0_wbd_cyc_o = s0_wb_wr.wbd_cyc ;
+ assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
+
+ assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
+ assign s1_wbd_adr_o = s1_wb_wr.wbd_adr ;
+ assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
+ assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
+ assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
+ assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
+
+ assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
+ assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit
+ assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
+ assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
+ assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
+ assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ;
+
+ assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
+ assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
+ assign s0_wb_rd.wbd_err = s0_wbd_err_i ;
+
+ assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ;
+ assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ;
+ assign s1_wb_rd.wbd_err = s1_wbd_err_i ;
+
+ assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ;
+ assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ;
+ assign s2_wb_rd.wbd_err = s2_wbd_err_i ;
//
@@ -297,121 +299,67 @@
// Generate Multiplexed Master Interface based on grant
always_comb begin
case(gnt)
- 3'h0: i_bus_m = m0_wb_wr;
- 3'h1: i_bus_m = m1_wb_wr;
- 3'h2: i_bus_m = m2_wb_wr;
- default: i_bus_m = m0_wb_wr;
+ 3'h0: m_bus_wr = m0_wb_wr;
+ 3'h1: m_bus_wr = m1_wb_wr;
+ 3'h2: m_bus_wr = m2_wb_wr;
+ default: m_bus_wr = m0_wb_wr;
endcase
end
// Generate Multiplexed Slave Interface based on target Id
-wire [3:0] wbd_tid = i_bus_m.wbd_tid; // to fix iverilog warning
+wire [3:0] s_wbd_tid = s_bus_wr.wbd_tid; // to fix iverilog warning
always_comb begin
- case(wbd_tid)
- 3'h0: i_bus_s = s0_wb_rd;
- 3'h1: i_bus_s = s1_wb_rd;
- 3'h2: i_bus_s = s2_wb_rd;
- default: i_bus_s = s0_wb_rd;
+ case(s_wbd_tid)
+ 3'h0: s_bus_rd = s0_wb_rd;
+ 3'h1: s_bus_rd = s1_wb_rd;
+ 3'h2: s_bus_rd = s2_wb_rd;
+ default: s_bus_rd = s0_wb_rd;
endcase
end
// Connect Master => Slave
-assign s0_wb_wr = (i_bus_m.wbd_tid == 2'b00) ? i_bus_m : 'h0;
-assign s1_wb_wr = (i_bus_m.wbd_tid == 2'b01) ? i_bus_m : 'h0;
-assign s2_wb_wr = (i_bus_m.wbd_tid == 2'b10) ? i_bus_m : 'h0;
+assign s0_wb_wr = (s_wbd_tid == 2'b00) ? s_bus_wr : 'h0;
+assign s1_wb_wr = (s_wbd_tid == 2'b01) ? s_bus_wr : 'h0;
+assign s2_wb_wr = (s_wbd_tid == 2'b10) ? s_bus_wr : 'h0;
// Connect Slave to Master
-assign m0_wb_rd = (gnt == 2'b00) ? i_bus_s : 'h0;
-assign m1_wb_rd = (gnt == 2'b01) ? i_bus_s : 'h0;
-assign m2_wb_rd = (gnt == 2'b10) ? i_bus_s : 'h0;
+assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
+assign m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
+assign m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
-
-// Wishbone Stagging FF towards S0 to break timing path
-wb_stagging u_s0_wb_stage(
+// Stagging FF to break write and read timing path
+wb_stagging u_m_wb_stage(
.clk_i (clk_i ),
.rst_n (rst_n ),
// WishBone Input master I/P
- .m_wbd_dat_i (s0_wb_wr.wbd_dat ),
- .m_wbd_adr_i (s0_wb_wr.wbd_adr ),
- .m_wbd_sel_i (s0_wb_wr.wbd_sel ),
- .m_wbd_we_i (s0_wb_wr.wbd_we ),
- .m_wbd_cyc_i (s0_wb_wr.wbd_cyc ),
- .m_wbd_stb_i (s0_wb_wr.wbd_stb ),
- .m_wbd_dat_o (s0_wb_rd.wbd_dat ),
- .m_wbd_ack_o (s0_wb_rd.wbd_ack ),
- .m_wbd_err_o (s0_wb_rd.wbd_err ),
+ .m_wbd_dat_i (m_bus_wr.wbd_dat ),
+ .m_wbd_adr_i (m_bus_wr.wbd_adr ),
+ .m_wbd_sel_i (m_bus_wr.wbd_sel ),
+ .m_wbd_we_i (m_bus_wr.wbd_we ),
+ .m_wbd_cyc_i (m_bus_wr.wbd_cyc ),
+ .m_wbd_stb_i (m_bus_wr.wbd_stb ),
+ .m_wbd_tid_i (m_bus_wr.wbd_tid ),
+ .m_wbd_dat_o (m_bus_rd.wbd_dat ),
+ .m_wbd_ack_o (m_bus_rd.wbd_ack ),
+ .m_wbd_err_o (m_bus_rd.wbd_err ),
// Slave Interface
- .s_wbd_dat_i (s0_wbd_dat_i ),
- .s_wbd_ack_i (s0_wbd_ack_i ),
- .s_wbd_err_i (s0_wbd_err_i ),
- .s_wbd_dat_o (s0_wbd_dat_o ),
- .s_wbd_adr_o (s0_wbd_adr_o ),
- .s_wbd_sel_o (s0_wbd_sel_o ),
- .s_wbd_we_o (s0_wbd_we_o ),
- .s_wbd_cyc_o (s0_wbd_cyc_o ),
- .s_wbd_stb_o (s0_wbd_stb_o )
+ .s_wbd_dat_i (s_bus_rd.wbd_dat ),
+ .s_wbd_ack_i (s_bus_rd.wbd_ack ),
+ .s_wbd_err_i (s_bus_rd.wbd_err ),
+ .s_wbd_dat_o (s_bus_wr.wbd_dat ),
+ .s_wbd_adr_o (s_bus_wr.wbd_adr ),
+ .s_wbd_sel_o (s_bus_wr.wbd_sel ),
+ .s_wbd_we_o (s_bus_wr.wbd_we ),
+ .s_wbd_cyc_o (s_bus_wr.wbd_cyc ),
+ .s_wbd_stb_o (s_bus_wr.wbd_stb ),
+ .s_wbd_tid_o (s_bus_wr.wbd_tid )
);
-// Wishbone Stagging FF towards S1 to break timing path
-wb_stagging u_s1_wb_stage(
- .clk_i (clk_i ),
- .rst_n (rst_n ),
- // WishBone Input master I/P
- .m_wbd_dat_i (s1_wb_wr.wbd_dat ),
- .m_wbd_adr_i (s1_wb_wr.wbd_adr ),
- .m_wbd_sel_i (s1_wb_wr.wbd_sel ),
- .m_wbd_we_i (s1_wb_wr.wbd_we ),
- .m_wbd_cyc_i (s1_wb_wr.wbd_cyc ),
- .m_wbd_stb_i (s1_wb_wr.wbd_stb ),
- .m_wbd_dat_o (s1_wb_rd.wbd_dat ),
- .m_wbd_ack_o (s1_wb_rd.wbd_ack ),
- .m_wbd_err_o (s1_wb_rd.wbd_err ),
-
- // Slave Interface
- .s_wbd_dat_i (s1_wbd_dat_i ),
- .s_wbd_ack_i (s1_wbd_ack_i ),
- .s_wbd_err_i (s1_wbd_err_i ),
- .s_wbd_dat_o (s1_wbd_dat_o ),
- .s_wbd_adr_o (s1_wbd_adr_o ),
- .s_wbd_sel_o (s1_wbd_sel_o ),
- .s_wbd_we_o (s1_wbd_we_o ),
- .s_wbd_cyc_o (s1_wbd_cyc_o ),
- .s_wbd_stb_o (s1_wbd_stb_o )
-
-);
-
-// Wishbone Stagging FF towards S1 to break timing path
-wb_stagging u_s2_wb_stage(
- .clk_i (clk_i ),
- .rst_n (rst_n ),
- // WishBone Input master I/P
- .m_wbd_dat_i (s2_wb_wr.wbd_dat ),
- .m_wbd_adr_i (s2_wb_wr.wbd_adr ),
- .m_wbd_sel_i (s2_wb_wr.wbd_sel ),
- .m_wbd_we_i (s2_wb_wr.wbd_we ),
- .m_wbd_cyc_i (s2_wb_wr.wbd_cyc ),
- .m_wbd_stb_i (s2_wb_wr.wbd_stb ),
- .m_wbd_dat_o (s2_wb_rd.wbd_dat ),
- .m_wbd_ack_o (s2_wb_rd.wbd_ack ),
- .m_wbd_err_o (s2_wb_rd.wbd_err ),
-
- // Slave Interface
- .s_wbd_dat_i (s2_wbd_dat_i ),
- .s_wbd_ack_i (s2_wbd_ack_i ),
- .s_wbd_err_i (s2_wbd_err_i ),
- .s_wbd_dat_o (s2_wbd_dat_o ),
- .s_wbd_adr_o (s2_wbd_adr_o ),
- .s_wbd_sel_o (s2_wbd_sel_o ),
- .s_wbd_we_o (s2_wbd_we_o ),
- .s_wbd_cyc_o (s2_wbd_cyc_o ),
- .s_wbd_stb_o (s2_wbd_stb_o )
-
-);
endmodule
