clk_ctl bug fix in wb_host
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index bd6d303..f66691f 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -4,8 +4,7 @@
#W
-sdram_clk 0000 0 4
-sspim_rst_n
+sspim_rst_n 0000 0 4
cpu_rst_n
qspim_rst_n
cfg_clk_ctrl1\[15\]
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 0c5c3c7..6746c4c 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h17m45s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,514.47,8,0,0,0,0,0,0,-1,0,0,-1,-1,1262458,5462,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.83,5.13,0.91,0.89,-1,166,1800,166,1800,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h20m15s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,519.0,8,0,0,0,0,0,0,-1,0,0,-1,-1,1262331,5400,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.8,5.17,0.95,0.82,-1,164,1798,164,1798,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 1c22120..a4ef737 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m26s,-1,34600.0,0.15,17300.0,21.07,602.71,2595,0,0,0,0,0,0,-1,4,0,0,-1,182887,27544,-4.26,-4.87,-1,-4.46,-1,-133.15,-138.34,-1,-147.66,-1,122772438.0,0.0,28.22,26.16,5.59,1.46,-1,1331,2937,696,2300,0,0,0,1379,0,0,0,0,0,0,0,4,762,894,13,204,1924,0,2128,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h8m31s,-1,35720.0,0.15,17860.0,21.59,597.18,2679,0,0,0,0,0,0,-1,12,0,0,-1,210257,30729,-3.95,-4.15,-1,-3.95,-1,-133.05,-138.35,-1,-131.8,-1,126979804.0,0.0,32.71,28.63,7.17,3.5,-1,1370,2981,694,2303,0,0,0,1428,0,0,0,0,0,0,0,4,782,936,13,204,1924,0,2128,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 67b9acb..91e4e9b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
new file mode 100644
index 0000000..1760e90
--- /dev/null
+++ b/verilog/dv/user_basic/Makefile
@@ -0,0 +1,104 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_basic
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
+else
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex:
+ echo @"This is user boot test, noting to compile the mangment core code"
+
+%.bin: %.elf
+ ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
new file mode 100644
index 0000000..b9164ea
--- /dev/null
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -0,0 +1,599 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// 1. User Risc core is booted using compiled code of ////
+//// user_risc_boot.c ////
+//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
+//// 3. After successful boot, Risc core will check the UART ////
+//// RX Data, If it's available then it loop back the same ////
+//// data in uart tx ////
+//// 4. Test bench send random 40 character towards User uart ////
+//// and expect same data to return back ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns/10 ps
+
+`include "uprj_netlists.v"
+
+
+module user_basic_tb;
+parameter CLK1_PERIOD = 10;
+parameter CLK2_PERIOD = 2;
+
+reg clock ;
+reg clock2 ;
+reg wb_rst_i ;
+reg power1, power2;
+reg power3, power4;
+
+reg wbd_ext_cyc_i; // strobe/request
+reg wbd_ext_stb_i; // strobe/request
+reg [31:0] wbd_ext_adr_i; // address
+reg wbd_ext_we_i; // write
+reg [31:0] wbd_ext_dat_i; // data output
+reg [3:0] wbd_ext_sel_i; // byte enable
+
+wire [31:0] wbd_ext_dat_o; // data input
+wire wbd_ext_ack_o; // acknowlegement
+wire wbd_ext_err_o; // error
+
+// User I/O
+wire [37:0] io_oeb ;
+wire [37:0] io_out ;
+wire [37:0] io_in ;
+
+wire [37:0] mprj_io ;
+wire [7:0] mprj_io_0 ;
+reg test_fail ;
+reg [31:0] read_data ;
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0] uart_data_bit ;
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] uart_data ;
+reg [15:0] uart_divisor ; // divided by n * 16
+reg [15:0] uart_timeout ;// wait time limit
+
+reg [15:0] uart_rx_nu ;
+reg [15:0] uart_tx_nu ;
+reg [7:0] uart_write_data [0:39];
+reg uart_fifo_enable ; // fifo mode disable
+
+wire clock_mon;
+integer test_step;
+
+integer i,j;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #(CLK1_PERIOD/2) clock <= (clock === 1'b0);
+ always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
+
+ initial begin
+ test_step = 0;
+ clock = 0;
+ clock2 = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("risc_boot.vcd");
+ $dumpvars(2, user_basic_tb);
+ end
+ `endif
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+initial
+begin
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Basic Test Started");
+
+ repeat (2) @(posedge clock);
+
+ test_fail=0;
+ fork
+ begin
+ // Default Value Check
+ // cfg_glb_ctrl = reg_0[6:0];
+ // uart_i2c_usb_sel = reg_0[8:7];
+ // cfg_wb_clk_ctrl = reg_0[11:9];
+ // cfg_rtc_clk_ctrl = reg_0[19:12];
+ // cfg_cpu_clk_ctrl = reg_0[23:20];
+ // cfg_sdram_clk_ctrl = reg_0[27:24];
+ // cfg_usb_clk_ctrl = reg_0[31:28];
+ $display("Step-1, CPU: CLOCK1, RTC: CLOCK2/2, USB: CLOCK2, WBS:CLOCK1");
+ test_step = 1;
+ wb_user_core_write('h3080_0000,{4'h0,4'h0,4'h0,8'h0,3'b000,2'b00,7'h00});
+ clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD);
+
+ $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK1/2");
+ test_step = 2;
+ wb_user_core_write('h3080_0000,{4'h8,4'h0,4'h8,8'h1,3'b100,2'b00,7'h00});
+ clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,2*CLK1_PERIOD);
+
+ $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/(2+1)");
+ test_step = 3;
+ wb_user_core_write('h3080_0000,{4'h9,4'h0,4'h4,8'h2,3'b101,2'b00,7'h00});
+ clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,3*CLK1_PERIOD);
+
+ $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/(2+2)");
+ test_step = 4;
+ wb_user_core_write('h3080_0000,{4'hA,4'h0,4'h5,8'h3,3'b110,2'b00,7'h00});
+ clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,4*CLK1_PERIOD);
+
+ $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/(2+3)");
+ test_step = 5;
+ wb_user_core_write('h3080_0000,{4'hB,4'h0,4'h6,8'h4,3'b111,2'b00,7'h00});
+ clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)");
+ test_step = 6;
+ wb_user_core_write('h3080_0000,{4'hC,4'h0,4'h7,8'h5,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-7, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
+ test_step = 7;
+ wb_user_core_write('h3080_0000,{4'hD,4'h0,4'h7,8'h6,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-8, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK1/(2+3)");
+ test_step = 8;
+ wb_user_core_write('h3080_0000,{4'hE,4'h0,4'h7,8'h7,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-9, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ test_step = 9;
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h8,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ test_step = 10;
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h80,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,130*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+
+ $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)");
+ test_step = 10;
+ wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'hFF,3'b111,2'b00,7'h00});
+ clock_monitor(5*CLK1_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+ end
+
+ begin
+ repeat (20000) @(posedge clock);
+ // $display("+1000 cycles");
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone User UART Test (GL) Passed");
+ `else
+ $display("Monitor: Standalone User UART Test (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone User UART Test (GL) Failed");
+ `else
+ $display("Monitor: Standalone User UART Test (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+end
+
+
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (clock2), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('0) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+ force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+ force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+ force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+ force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+ force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
+ force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
+
+ force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+ force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+ force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+ force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+ force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
+ force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
+
+ force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+ force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+ force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+ force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+ force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
+ force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
+
+ force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+ force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+ force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+ force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+ force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
+ force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
+ force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
+
+ force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+ force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
+ force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+ force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
+
+
+
+ force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
+
+ force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
+ force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
+
+ force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
+ force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
+
+ force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
+ force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
+
+ force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
+ force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
+ end
+`endif
+
+
+task clock_monitor;
+input [15:0] exp_cpu_period;
+input [15:0] exp_rtc_period;
+input [15:0] exp_usb_period;
+input [15:0] exp_wbs_period;
+begin
+ force clock_mon = u_top.u_wb_host.cpu_clk;
+ check_clock_period("CPU CLock",exp_cpu_period);
+ release clock_mon;
+
+ force clock_mon = u_top.u_wb_host.rtc_clk;
+ check_clock_period("RTC Clock",exp_rtc_period);
+ release clock_mon;
+
+ force clock_mon = u_top.u_wb_host.usb_clk;
+ check_clock_period("USB Clock",exp_usb_period);
+ release clock_mon;
+
+ force clock_mon = u_top.u_wb_host.wbs_clk_out;
+ check_clock_period("WBS Clock",exp_wbs_period);
+ release clock_mon;
+end
+endtask
+
+//----------------------------------
+// Check the clock period
+//----------------------------------
+task check_clock_period;
+input [127:0] clk_name;
+input [15:0] clk_period; // in NS
+time prev_t, next_t, periodd;
+begin
+ $timeformat(-12,3,"ns",10);
+ repeat(1) @(posedge clock_mon);
+ repeat(1) @(posedge clock_mon);
+ prev_t = $realtime;
+ repeat(100) @(posedge clock_mon);
+ next_t = $realtime;
+ periodd = (next_t-prev_t)/100;
+ //periodd = (periodd)/1e9;
+ if(clk_period != periodd) begin
+ $display("STATUS: FAIL => %s Exp Period: %d Rxd: %d",clk_name,clk_period,periodd);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: PASS => %s Period: %d ",clk_name,clk_period);
+ end
+end
+endtask
+
+
+
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+
+wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/lib/clk_ctl.v b/verilog/rtl/lib/clk_ctl.v
index 34f5989..7e4478b 100644
--- a/verilog/rtl/lib/clk_ctl.v
+++ b/verilog/rtl/lib/clk_ctl.v
@@ -31,7 +31,11 @@
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
-//// Revision : Mar 2, 2011 ////
+//// Revision : ////
+//// 1.0 Mar 2, 2011,Dinesh.A ////
+//// Initial Version ////
+//// 1.1 Nov 15,2021,Dinesh A ////
+//// Bug fix in High and Low count width ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -102,8 +106,8 @@
//------------------------------------
// Clock Divide func is done here
//------------------------------------
-reg [WD-1:0] high_count ; // high level counter
-reg [WD-1:0] low_count ; // low level counter
+reg [WD:0] high_count ; // high level counter
+reg [WD:0] low_count ; // low level counter
reg mclk_div ; // divided clock
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9bd8900..460af98 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -116,10 +116,13 @@
//// Basic verification and Synthesis cleanup ////
//// 1.5 - 6th Nov 2021, Dinesh A ////
//// Clock Skew block moved inside respective block due ////
-// to top-level power hook-up challenges for small IP ////
+//// to top-level power hook-up challenges for small IP ////
//// 1.6 Nov 14, 2021, Dinesh A ////
//// Major bug, clock divider inside the wb_host reset ////
//// connectivity open is fixed ////
+//// 1.7 Nov 15, 2021, Dinesh A ////
+//// Bug fix in clk_ctrl High/Low counter width ////
+//// Removed sram_clock ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -299,7 +302,6 @@
wire i2c_rst_n ;// i2c reset
wire usb_rst_n ;// i2c reset
wire [1:0] uart_i2c_usb_sel ;// 0 - uart, 1 - I2C, 2- USb
-wire sdram_clk ;
wire cpu_clk ;
wire rtc_clk ;
wire usb_clk ;
@@ -331,7 +333,6 @@
wire wbd_clk_riscv ; // clock for riscv
wire wbd_clk_uart ; // clock for uart
wire wbd_clk_spi ; // clock for spi
-wire wbd_clk_sdram ; // clock for sdram
wire wbd_clk_glbl ; // clock for global reg
wire wbd_clk_wh ; // clock for global reg
@@ -439,7 +440,6 @@
.user_clock1 (wb_clk_i ),
.user_clock2 (user_clock2 ),
- .sdram_clk (sdram_clk ),
.cpu_clk (cpu_clk ),
.rtc_clk (rtc_clk ),
.usb_clk (usb_clk ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index f5f2d4f..1cd32d6 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -75,7 +75,6 @@
input logic user_clock1 ,
input logic user_clock2 ,
- output logic sdram_clk ,
output logic cpu_clk ,
output logic rtc_clk ,
output logic usb_clk ,
@@ -156,7 +155,6 @@
logic [31:0] reg_0; // Software_Reg_0
logic [2:0] cfg_wb_clk_ctrl;
-logic [3:0] cfg_sdram_clk_ctrl;
logic [3:0] cfg_cpu_clk_ctrl;
logic [7:0] cfg_rtc_clk_ctrl;
logic [3:0] cfg_usb_clk_ctrl;
@@ -255,7 +253,6 @@
assign cfg_wb_clk_ctrl = reg_0[11:9];
assign cfg_rtc_clk_ctrl = reg_0[19:12];
assign cfg_cpu_clk_ctrl = reg_0[23:20];
-assign cfg_sdram_clk_ctrl = reg_0[27:24];
assign cfg_usb_clk_ctrl = reg_0[31:28];
@@ -384,9 +381,9 @@
wire cpu_ref_clk;
wire cpu_clk_int;
-wire cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[0];
-wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[1];
-wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[3:2];
+wire cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[3];
+wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[2];
+wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[1:0];
//assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1;
//assign cpu_clk_int = (cfg_cpu_clk_div) ? cpu_clk_div : cpu_ref_clk;
@@ -431,8 +428,8 @@
wire usb_ref_clk;
wire usb_clk_int;
-wire cfg_usb_clk_div = cfg_usb_clk_ctrl[0];
-wire [2:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[3:1];
+wire cfg_usb_clk_div = cfg_usb_clk_ctrl[3];
+wire [2:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[2:0];
assign usb_ref_clk = user_clock2 ;
//assign usb_clk_int = (cfg_usb_clk_div) ? usb_clk_div : usb_ref_clk;
