syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz

commit: a999a4e4c59662ad04dfa2997b8033ff63eb7ce5 [log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com> Sat Jul 24 19:56:01 2021 +0530
committer: dineshannayya <dinesh.annayya@gmail.com> Sat Jul 24 19:56:01 2021 +0530
tree: 7d3f1371dbf8b469a136d2cc5dd601f2bde7afcb
parent: d454c617a6466def28fd346aa5fba73ef3c48ac8 [diff]
diff --git a/checks/erase_box_user_project_wrapper.gds.log b/checks/erase_box_user_project_wrapper.gds.log
index e833e84..2464ece 100644
--- a/checks/erase_box_user_project_wrapper.gds.log
+++ b/checks/erase_box_user_project_wrapper.gds.log

@@ -16,47 +16,48 @@
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 3.0
 Library name: user_project_wrapper
-Reading "sky130_fd_sc_hd__decap_3".
-Reading "sky130_fd_sc_hd__decap_8".
-Reading "sky130_fd_sc_hd__decap_6".
-Reading "sky130_fd_sc_hd__decap_12".
-Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__fill_1".
-Reading "sky130_fd_sc_hd__o22a_4".
-Reading "sky130_fd_sc_hd__decap_4".
-Reading "sky130_fd_sc_hd__and2_4".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__dfxtp_4".
-Reading "sky130_fd_sc_hd__or2_4".
-Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__o21a_4".
-Reading "sky130_fd_sc_hd__buf_2".
-Reading "sky130_fd_sc_hd__and3_4".
-Reading "sky130_fd_sc_hd__a2bb2o_4".
-Reading "sky130_fd_sc_hd__conb_1".
-Reading "sky130_fd_sc_hd__inv_2".
-Reading "sky130_fd_sc_hd__a32o_4".
-Reading "sky130_fd_sc_hd__diode_2".
-Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__buf_4".
 Reading "sky130_fd_sc_hd__a21o_4".
-Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__or3_4".
 Reading "sky130_fd_sc_hd__a21boi_4".
 Reading "sky130_fd_sc_hd__or4_4".
-Reading "sky130_fd_sc_hd__a21oi_4".
-Reading "sky130_fd_sc_hd__or3_4".
-Reading "sky130_fd_sc_hd__nor2_4".
-Reading "sky130_fd_sc_hd__and4_4".
-Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__buf_8".
 Reading "sky130_fd_sc_hd__a22oi_4".
-Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__and3_4".
 Reading "sky130_fd_sc_hd__o21ai_4".
-Reading "sky130_fd_sc_hd__buf_4".
-Reading "sky130_fd_sc_hd__a2111o_4".
 Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__a2111o_4".
 Reading "sky130_fd_sc_hd__a21bo_4".
-Reading "scr1_top_wb".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "scr1_core_top".
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 Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
 Reading "sky130_fd_sc_hd__mux2_1".
 Reading "sky130_fd_sc_hd__mux2_4".
@@ -1960,7 +1411,7 @@
     11900 uses
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-Reading "sdrc_top".
+Reading "scr1_intf".
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@@ -2213,105 +1664,6 @@
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 Reading "uart_core".
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+Reading "sdrc_top".
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+    17900 uses
+    18000 uses
+    18100 uses
+    18200 uses
+    18300 uses
+    18400 uses
+    18500 uses
+    18600 uses
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+    18900 uses
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+    20000 uses
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+    22000 uses
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+    22400 uses
+    22500 uses
+    22600 uses
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+    22800 uses
+    22900 uses
+    23000 uses
+    23100 uses
+    23200 uses
+    23300 uses
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+    23500 uses
+    23600 uses
+    23700 uses
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+    23900 uses
+    24000 uses
+    24100 uses
+    24200 uses
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+    24400 uses
+    24500 uses
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+    24900 uses
+    25000 uses
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+    25200 uses
+    25300 uses
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+    25700 uses
+    25800 uses
+    25900 uses
+    26000 uses
+    26100 uses
+    26200 uses
+    26300 uses
+    26400 uses
+    26500 uses
+    26600 uses
+    26700 uses
+    26800 uses
+    26900 uses
+    27000 uses
+    27100 uses
+    27200 uses
+    27300 uses
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+    27500 uses
+    27600 uses
+    27700 uses
+    27800 uses
+    27900 uses
+    28000 uses
+    28100 uses
+    28200 uses
+    28300 uses
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+    28500 uses
+    28600 uses
+    28700 uses
+    28800 uses
+    28900 uses
+    29000 uses
+    29100 uses
+    29200 uses
+    29300 uses
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+    29600 uses
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+    30000 uses
+    30100 uses
+    30200 uses
+    30300 uses
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+    30500 uses
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+    30900 uses
+    31000 uses
+    31100 uses
+    31200 uses
+    31300 uses
+    31400 uses
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+    34600 uses
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+    34800 uses
+    34900 uses
+    35000 uses
+    35100 uses
 Reading "glbl_cfg".
     100 uses
     200 uses
@@ -2860,7 +2564,6 @@
     14000 uses
     14100 uses
 Reading "sky130_fd_sc_hd__dlygate4sd3_1".
-Reading "sky130_fd_sc_hd__o41a_4".
 Reading "spim_top".
     100 uses
     200 uses
@@ -3109,6 +2812,32 @@
     24500 uses
     24600 uses
     24700 uses
+    24800 uses
+    24900 uses
+    25000 uses
+    25100 uses
+    25200 uses
+    25300 uses
+    25400 uses
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+    26100 uses
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+    26500 uses
+    26600 uses
+    26700 uses
+    26800 uses
+    26900 uses
+    27000 uses
+    27100 uses
+    27200 uses
+    27300 uses
 Reading "user_project_wrapper".
 Root cell box:
            width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)

diff --git a/checks/full_log.log b/checks/full_log.log
index 6d28b11..6b9756a 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log

@@ -3,8 +3,8 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 8: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 971 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/user_project_wrapper.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_host.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/sdrc_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_interconnect.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/scr1_top_wb.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/glbl_cfg.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/test.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/uart_core.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_skew_adjust.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_buf.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/spim_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot']
+ SPDX COMPLIANCE Found 1110 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/user_project_wrapper.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_host.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/sdrc_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_interconnect.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/scr1_top_wb.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/glbl_cfg.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/test.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/uart_core.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_skew_adjust.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_buf.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/spim_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/aa', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/scr_core/runs/scr_core/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib']
  Executing Step 2 of 8: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.
@@ -21,7 +21,7 @@
 instance caravel found
 instance user_project_wrapper found
 Design is complex and contains: 47 modules
-Design is complex and contains: 18 modules
+Design is complex and contains: 20 modules
 verilog Consistency Checks Passed.
  Basic Hierarchy Checks Passed.
 {PROGRESS} Running Pins and Power Checks...
@@ -37,3 +37,7 @@
 TEST FAILED AT STEP 5
  Executing Step 6 of 8: DRC Violations Checks
  Running Magic DRC Checks...
+Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 1 Times.
+ DRC Checks on GDS Failed, Reason: Total # of DRC violations is 1
+TEST FAILED AT STEP 6
+ SOME Checks FAILED !!!

diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index c1fe571..b91926b 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log

@@ -13,47 +13,48 @@
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 3.0
 Library name: user_project_wrapper
-Reading "sky130_fd_sc_hd__decap_3".
-Reading "sky130_fd_sc_hd__decap_8".
-Reading "sky130_fd_sc_hd__decap_6".
-Reading "sky130_fd_sc_hd__decap_12".
-Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__fill_1".
-Reading "sky130_fd_sc_hd__o22a_4".
-Reading "sky130_fd_sc_hd__decap_4".
-Reading "sky130_fd_sc_hd__and2_4".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__dfxtp_4".
-Reading "sky130_fd_sc_hd__or2_4".
-Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__o21a_4".
-Reading "sky130_fd_sc_hd__buf_2".
-Reading "sky130_fd_sc_hd__and3_4".
-Reading "sky130_fd_sc_hd__a2bb2o_4".
-Reading "sky130_fd_sc_hd__conb_1".
-Reading "sky130_fd_sc_hd__inv_2".
-Reading "sky130_fd_sc_hd__a32o_4".
-Reading "sky130_fd_sc_hd__diode_2".
-Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__buf_4".
 Reading "sky130_fd_sc_hd__a21o_4".
-Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__or3_4".
 Reading "sky130_fd_sc_hd__a21boi_4".
 Reading "sky130_fd_sc_hd__or4_4".
-Reading "sky130_fd_sc_hd__a21oi_4".
-Reading "sky130_fd_sc_hd__or3_4".
-Reading "sky130_fd_sc_hd__nor2_4".
-Reading "sky130_fd_sc_hd__and4_4".
-Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__buf_8".
 Reading "sky130_fd_sc_hd__a22oi_4".
-Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__and3_4".
 Reading "sky130_fd_sc_hd__o21ai_4".
-Reading "sky130_fd_sc_hd__buf_4".
-Reading "sky130_fd_sc_hd__a2111o_4".
 Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__a2111o_4".
 Reading "sky130_fd_sc_hd__a21bo_4".
-Reading "scr1_top_wb".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "scr1_core_top".
     100 uses
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@@ -1272,553 +1273,1575 @@
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-    160600 uses
-    160700 uses
-    160800 uses
-    160900 uses
-    161000 uses
-    161100 uses
-    161200 uses
-    161300 uses
-    161400 uses
-    161500 uses
-    161600 uses
-    161700 uses
-    161800 uses
-    161900 uses
-    162000 uses
-    162100 uses
-    162200 uses
-    162300 uses
-    162400 uses
-    162500 uses
-    162600 uses
-    162700 uses
-    162800 uses
-    162900 uses
-    163000 uses
-    163100 uses
-    163200 uses
-    163300 uses
-    163400 uses
-    163500 uses
-    163600 uses
-    163700 uses
-    163800 uses
-    163900 uses
-    164000 uses
-    164100 uses
-    164200 uses
-    164300 uses
-    164400 uses
-    164500 uses
-    164600 uses
-    164700 uses
-    164800 uses
-    164900 uses
-    165000 uses
-    165100 uses
-    165200 uses
-    165300 uses
-    165400 uses
-    165500 uses
-    165600 uses
-    165700 uses
-    165800 uses
-    165900 uses
-    166000 uses
-    166100 uses
-    166200 uses
-    166300 uses
-    166400 uses
-    166500 uses
-    166600 uses
-    166700 uses
-    166800 uses
-    166900 uses
-    167000 uses
-    167100 uses
-    167200 uses
-    167300 uses
-    167400 uses
-    167500 uses
-    167600 uses
-    167700 uses
-    167800 uses
-    167900 uses
-    168000 uses
-    168100 uses
-    168200 uses
-    168300 uses
-    168400 uses
-    168500 uses
-    168600 uses
-    168700 uses
-    168800 uses
-    168900 uses
-    169000 uses
-    169100 uses
-    169200 uses
-    169300 uses
-    169400 uses
-    169500 uses
-    169600 uses
-    169700 uses
-    169800 uses
-    169900 uses
-    170000 uses
-    170100 uses
-    170200 uses
-    170300 uses
-    170400 uses
-    170500 uses
-    170600 uses
-    170700 uses
-    170800 uses
-    170900 uses
-    171000 uses
-    171100 uses
-    171200 uses
-    171300 uses
-    171400 uses
-    171500 uses
-    171600 uses
-    171700 uses
-    171800 uses
-    171900 uses
-    172000 uses
-    172100 uses
-    172200 uses
-    172300 uses
-    172400 uses
-    172500 uses
-    172600 uses
-    172700 uses
-    172800 uses
-    172900 uses
-    173000 uses
-    173100 uses
-    173200 uses
-    173300 uses
-    173400 uses
-    173500 uses
-    173600 uses
-    173700 uses
-    173800 uses
-    173900 uses
-    174000 uses
-    174100 uses
-    174200 uses
-    174300 uses
-    174400 uses
-    174500 uses
-    174600 uses
-    174700 uses
-    174800 uses
-    174900 uses
-    175000 uses
-    175100 uses
-    175200 uses
-    175300 uses
-    175400 uses
-    175500 uses
-    175600 uses
-    175700 uses
-    175800 uses
-    175900 uses
-    176000 uses
-    176100 uses
-    176200 uses
-    176300 uses
-    176400 uses
-    176500 uses
-    176600 uses
-    176700 uses
-    176800 uses
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "clk_skew_adjust".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+Reading "sky130_ef_sc_hd__fakediode_2".
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Reading "wb_host".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+    9500 uses
+    9600 uses
+    9700 uses
+    9800 uses
+    9900 uses
+    10000 uses
+    10100 uses
+    10200 uses
+    10300 uses
+    10400 uses
+    10500 uses
+    10600 uses
+    10700 uses
+    10800 uses
+    10900 uses
+    11000 uses
+    11100 uses
+    11200 uses
+    11300 uses
+    11400 uses
+    11500 uses
+    11600 uses
+    11700 uses
+    11800 uses
+    11900 uses
+    12000 uses
+    12100 uses
+Reading "scr1_intf".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+    9500 uses
+    9600 uses
+    9700 uses
+    9800 uses
+    9900 uses
+    10000 uses
+    10100 uses
+    10200 uses
+    10300 uses
+    10400 uses
+    10500 uses
+    10600 uses
+    10700 uses
+    10800 uses
+    10900 uses
+    11000 uses
+    11100 uses
+    11200 uses
+    11300 uses
+    11400 uses
+    11500 uses
+    11600 uses
+    11700 uses
+    11800 uses
+    11900 uses
+    12000 uses
+    12100 uses
+    12200 uses
+    12300 uses
+    12400 uses
+    12500 uses
+    12600 uses
+    12700 uses
+    12800 uses
+    12900 uses
+    13000 uses
+    13100 uses
+    13200 uses
+    13300 uses
+    13400 uses
+    13500 uses
+    13600 uses
+    13700 uses
+    13800 uses
+    13900 uses
+    14000 uses
+    14100 uses
+    14200 uses
+    14300 uses
+    14400 uses
+    14500 uses
+    14600 uses
+    14700 uses
+    14800 uses
+    14900 uses
+    15000 uses
+    15100 uses
+    15200 uses
+    15300 uses
+    15400 uses
+    15500 uses
+    15600 uses
+    15700 uses
+    15800 uses
+    15900 uses
+    16000 uses
+    16100 uses
+    16200 uses
+    16300 uses
+    16400 uses
+    16500 uses
+    16600 uses
+    16700 uses
+    16800 uses
+    16900 uses
+    17000 uses
+    17100 uses
+    17200 uses
+    17300 uses
+    17400 uses
+    17500 uses
+    17600 uses
+    17700 uses
+    17800 uses
+    17900 uses
+    18000 uses
+    18100 uses
+    18200 uses
+    18300 uses
+    18400 uses
+    18500 uses
+    18600 uses
+    18700 uses
+    18800 uses
+    18900 uses
+    19000 uses
+    19100 uses
+    19200 uses
+    19300 uses
+    19400 uses
+    19500 uses
+    19600 uses
+    19700 uses
+    19800 uses
+    19900 uses
+    20000 uses
+    20100 uses
+    20200 uses
+    20300 uses
+    20400 uses
+    20500 uses
+    20600 uses
+    20700 uses
+    20800 uses
+    20900 uses
+    21000 uses
+    21100 uses
+    21200 uses
+    21300 uses
+    21400 uses
+    21500 uses
+    21600 uses
+    21700 uses
+    21800 uses
+    21900 uses
+    22000 uses
+    22100 uses
+    22200 uses
+    22300 uses
+    22400 uses
+    22500 uses
+    22600 uses
+    22700 uses
+    22800 uses
+    22900 uses
+    23000 uses
+    23100 uses
+    23200 uses
+    23300 uses
+    23400 uses
+    23500 uses
+    23600 uses
+    23700 uses
+    23800 uses
+    23900 uses
+    24000 uses
+    24100 uses
+    24200 uses
+    24300 uses
+    24400 uses
+    24500 uses
+    24600 uses
+    24700 uses
+    24800 uses
+    24900 uses
+    25000 uses
+    25100 uses
+    25200 uses
+Reading "uart_core".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+    9500 uses
+    9600 uses
+    9700 uses
+    9800 uses
+    9900 uses
+    10000 uses
+    10100 uses
+    10200 uses
+    10300 uses
+    10400 uses
+    10500 uses
+    10600 uses
+    10700 uses
+    10800 uses
+    10900 uses
+    11000 uses
+    11100 uses
+    11200 uses
+    11300 uses
+    11400 uses
+    11500 uses
+    11600 uses
+    11700 uses
+    11800 uses
+    11900 uses
+    12000 uses
+    12100 uses
+    12200 uses
+    12300 uses
+    12400 uses
+    12500 uses
+    12600 uses
+    12700 uses
+    12800 uses
+    12900 uses
+    13000 uses
+    13100 uses
+    13200 uses
+    13300 uses
+    13400 uses
+    13500 uses
+    13600 uses
+    13700 uses
+Reading "wb_interconnect".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+    9500 uses
+    9600 uses
+    9700 uses
+    9800 uses
+    9900 uses
+    10000 uses
+    10100 uses
+    10200 uses
+    10300 uses
+    10400 uses
+    10500 uses
+    10600 uses
+    10700 uses
+    10800 uses
+    10900 uses
+    11000 uses
+    11100 uses
+    11200 uses
+    11300 uses
+    11400 uses
+    11500 uses
+    11600 uses
+    11700 uses
+    11800 uses
+    11900 uses
+    12000 uses
+    12100 uses
+    12200 uses
+    12300 uses
+    12400 uses
+    12500 uses
+    12600 uses
+    12700 uses
+    12800 uses
+    12900 uses
+    13000 uses
+    13100 uses
+    13200 uses
+    13300 uses
+    13400 uses
+    13500 uses
+    13600 uses
+    13700 uses
+    13800 uses
+    13900 uses
+    14000 uses
+    14100 uses
+    14200 uses
+    14300 uses
+    14400 uses
+    14500 uses
+    14600 uses
+    14700 uses
+    14800 uses
+    14900 uses
+    15000 uses
+    15100 uses
+    15200 uses
+    15300 uses
+    15400 uses
+    15500 uses
+    15600 uses
+    15700 uses
+    15800 uses
+    15900 uses
+    16000 uses
+    16100 uses
+    16200 uses
+    16300 uses
+    16400 uses
+    16500 uses
+    16600 uses
+    16700 uses
+    16800 uses
+    16900 uses
+    17000 uses
+    17100 uses
+    17200 uses
+    17300 uses
+    17400 uses
+    17500 uses
+    17600 uses
+    17700 uses
+    17800 uses
+    17900 uses
+    18000 uses
+    18100 uses
+    18200 uses
+    18300 uses
+    18400 uses
+    18500 uses
+    18600 uses
+    18700 uses
+    18800 uses
+    18900 uses
+    19000 uses
+    19100 uses
+    19200 uses
+    19300 uses
+    19400 uses
+    19500 uses
+    19600 uses
+    19700 uses
+    19800 uses
+    19900 uses
+    20000 uses
+    20100 uses
+    20200 uses
+    20300 uses
+    20400 uses
+    20500 uses
+    20600 uses
+    20700 uses
+    20800 uses
+    20900 uses
+    21000 uses
+    21100 uses
+    21200 uses
+    21300 uses
+    21400 uses
+    21500 uses
+    21600 uses
+    21700 uses
+    21800 uses
+    21900 uses
+    22000 uses
+    22100 uses
+    22200 uses
+    22300 uses
+    22400 uses
+    22500 uses
+    22600 uses
+    22700 uses
+    22800 uses
+    22900 uses
+    23000 uses
+    23100 uses
+    23200 uses
+    23300 uses
+    23400 uses
+    23500 uses
+    23600 uses
+    23700 uses
+    23800 uses
+    23900 uses
+    24000 uses
+    24100 uses
+    24200 uses
+    24300 uses
+    24400 uses
+    24500 uses
+    24600 uses
+    24700 uses
+    24800 uses
+    24900 uses
+    25000 uses
+    25100 uses
+    25200 uses
+    25300 uses
+    25400 uses
+    25500 uses
+    25600 uses
+    25700 uses
+    25800 uses
+    25900 uses
+    26000 uses
+    26100 uses
+    26200 uses
+    26300 uses
+    26400 uses
+    26500 uses
+    26600 uses
+Reading "sdrc_top".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+    9500 uses
+    9600 uses
+    9700 uses
+    9800 uses
+    9900 uses
+    10000 uses
+    10100 uses
+    10200 uses
+    10300 uses
+    10400 uses
+    10500 uses
+    10600 uses
+    10700 uses
+    10800 uses
+    10900 uses
+    11000 uses
+    11100 uses
+    11200 uses
+    11300 uses
+    11400 uses
+    11500 uses
+    11600 uses
+    11700 uses
+    11800 uses
+    11900 uses
+    12000 uses
+    12100 uses
+    12200 uses
+    12300 uses
+    12400 uses
+    12500 uses
+    12600 uses
+    12700 uses
+    12800 uses
+    12900 uses
+    13000 uses
+    13100 uses
+    13200 uses
+    13300 uses
+    13400 uses
+    13500 uses
+    13600 uses
+    13700 uses
+    13800 uses
+    13900 uses
+    14000 uses
+    14100 uses
+    14200 uses
+    14300 uses
+    14400 uses
+    14500 uses
+    14600 uses
+    14700 uses
+    14800 uses
+    14900 uses
+    15000 uses
+    15100 uses
+    15200 uses
+    15300 uses
+    15400 uses
+    15500 uses
+    15600 uses
+    15700 uses
+    15800 uses
+    15900 uses
+    16000 uses
+    16100 uses
+    16200 uses
+    16300 uses
+    16400 uses
+    16500 uses
+    16600 uses
+    16700 uses
+    16800 uses
+    16900 uses
+    17000 uses
+    17100 uses
+    17200 uses
+    17300 uses
+    17400 uses
+    17500 uses
+    17600 uses
+    17700 uses
+    17800 uses
+    17900 uses
+    18000 uses
+    18100 uses
+    18200 uses
+    18300 uses
+    18400 uses
+    18500 uses
+    18600 uses
+    18700 uses
+    18800 uses
+    18900 uses
+    19000 uses
+    19100 uses
+    19200 uses
+    19300 uses
+    19400 uses
+    19500 uses
+    19600 uses
+    19700 uses
+    19800 uses
+    19900 uses
+    20000 uses
+    20100 uses
+    20200 uses
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+Reading "glbl_cfg".
+    100 uses
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+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+[INFO]: COUNT: 1
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc)
+[INFO]: Saving mag view with DRC errors(/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 44d9a3b..8cdfdef 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log

@@ -13,90 +13,146 @@
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-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/22-opensta_spef_tns.rpt
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 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-yosys_4.chk.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/22-opensta_spef.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/2-opensta.min_max.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-yosys_pre.stat
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/2-opensta_tns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-yosys_dff.stat
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/3-yosys_dff.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/22-opensta_spef.min_max.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/12-opensta_post_openphysyn.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/12-opensta_post_openphysyn.timing.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/2-opensta_wns.rpt
@@ -840,28 +970,19 @@
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/3-yosys_4.chk.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/2-opensta.timing.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/3-yosys_pre.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/22-opensta_spef_wns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/12-opensta_post_openphysyn_wns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/12-opensta_post_openphysyn.min_max.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/3-yosys_4.stat.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-yosys_4.stat.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/routing/39-antenna.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/floorplan/4-verilog2def.die_area.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/floorplan/4-verilog2def.core_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/klayout/32-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/klayout/34-klayout.xor.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/placement/10-openphysyn_wns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/placement/10-openphysyn_tns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/reports/placement/10-openphysyn_allchecks.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis_preroute.v
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis_optimized.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.spef
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def.ref
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/.magicrc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.lef.json
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.powered.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/results/klayout/user_project_wrapper.lyp
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/netlist/uart.v
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/netlist/sdram.v
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/netlist/wb_host.v
@@ -968,6 +1089,24 @@
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.lef.json
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/klayout/sdrc_top.lyp
 /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_spi/user_risc_boot.dump
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_spi/user_spi.vvp
 /home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/model/s25fl256s.sv
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/risc_boot/user_uart.dump
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/risc_boot/risc_boot.vvp
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/user_risc_boot.dump
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/user_risc_boot.vvp
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_uart/user_uart.dump
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_uart/golden.gtkw
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_uart/user_uart.vvp
 /home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/wb_port/run_verilog
 /home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/aa
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/unconstraints.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/tmp/trimmed.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/tmp/synthesis/hierarchy.dot
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/reports/yosys_4.chk.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/reports/yosys_dff.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/reports/yosys_pre.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/netlist/scr1_top_wb.gv

diff --git a/checks/user_project_wrapper.magic.drc b/checks/user_project_wrapper.magic.drc
index 46ca7f3..ef51034 100644
--- a/checks/user_project_wrapper.magic.drc
+++ b/checks/user_project_wrapper.magic.drc

@@ -1,5 +1,9 @@
 user_project_wrapper
 ----------------------------------------
-[INFO]: COUNT: 0
+All nwells must contain metal-connected N+ taps (nwell.4)
+----------------------------------------
+ 443.710 1740.610 445.470 1742.215
+----------------------------------------
+[INFO]: COUNT: 1
 [INFO]: Should be divided by 3 or 4
 

diff --git a/checks/xor.log b/checks/xor.log
index caf81f2..833cc24 100644
--- a/checks/xor.log
+++ b/checks/xor.log

@@ -6,14 +6,14 @@
 Reading /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds ..
 --- Running XOR for 69/20 ---
 "_input" in: xor.drc:38
-Elapsed: 0.000s
+Elapsed: 0.010s
 "_input" in: xor.drc:38
 Elapsed: 0.010s
 "^" in: xor.drc:38
-Elapsed: 0.010s
+Elapsed: 0.000s
 XOR differences: 0
 "_output" in: xor.drc:41
-Elapsed: 0.000s
+Elapsed: 0.010s
 --- Running XOR for 70/20 ---
 "_input" in: xor.drc:38
 Elapsed: 0.010s
@@ -30,15 +30,15 @@
 "_input" in: xor.drc:38
 Elapsed: 0.000s
 "^" in: xor.drc:38
-Elapsed: 0.000s
+Elapsed: 0.010s
 XOR differences: 358
 "_output" in: xor.drc:41
 Elapsed: 0.010s
 --- Running XOR for 71/44 ---
 "_input" in: xor.drc:38
-Elapsed: 0.010s
-"_input" in: xor.drc:38
 Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
 "^" in: xor.drc:38
 Elapsed: 0.010s
 XOR differences: 1144
@@ -56,13 +56,13 @@
 Elapsed: 0.010s
 --- Running XOR for 81/14 ---
 "_input" in: xor.drc:38
-Elapsed: 0.000s
-"_input" in: xor.drc:38
 Elapsed: 0.010s
-"^" in: xor.drc:38
+"_input" in: xor.drc:38
 Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.010s
 XOR differences: 2
 "_output" in: xor.drc:41
-Elapsed: 0.010s
+Elapsed: 0.000s
 Writing layout file: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.xor.gds ..
-Total run time: 0.170s
+Total run time: 0.160s

diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index c200e4b..53a9082 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc

@@ -22,7 +22,7 @@
 set ::env(WB_CLOCK_NAME)      "wb_clk"
 
 #Risc Core Clock
-set ::env(CORE_CLOCK_PERIOD) "40"
+set ::env(CORE_CLOCK_PERIOD) "20"
 set ::env(CORE_CLOCK_PORT)   "core_clk"
 set ::env(CORE_CLOCK_NAME)   "core_clk"
 
@@ -54,8 +54,8 @@
 # WB Clock domain input output
 ######################################
 create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.45]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.45]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_NAME)]]

diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 9e01803..3439877 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl

@@ -51,6 +51,8 @@
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv  \
+	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv  \
+	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv  \
@@ -62,6 +64,7 @@
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv   \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv   \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv   \
+	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv   \
 	$script_dir/../../verilog/rtl/lib/async_fifo.sv "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
@@ -83,7 +86,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 1500.0 1200.0]
+set ::env(DIE_AREA) [list 0.0 0.0 1600.0 1200.0]
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -92,7 +95,11 @@
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
 
-set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.45"
+set ::env(GLOBAL_ROUTER) "fastroute"
+set ::env(DETAILED_ROUTER) "tritonroute"
+set ::env(CELL_PAD) "4"
 
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
@@ -100,6 +107,8 @@
 
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
 
 #set ::env(LVS_CONNECT_BY_LABEL) 1
 

diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 1ecdcf1..8bfe160 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg

@@ -1,6 +1,8 @@
 #BUS_SORT
 
+
 #MANUAL_PLACE
+
 #E
 core_clk            0000 0
 rtc_clk             

diff --git a/openlane/syntacore/sta.tcl b/openlane/syntacore/sta.tcl
index 0a63ab5..e1bc690 100644
--- a/openlane/syntacore/sta.tcl
+++ b/openlane/syntacore/sta.tcl

@@ -19,7 +19,7 @@
 set ::env(CURRENT_NETLIST) ../user_project_wrapper/netlist/syntacore.v
 set ::env(DESIGN_NAME) "scr1_top_wb"
 set ::env(CURRENT_SPEF) ../../spef/scr1_top_wb.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/syntacore/base.sdc"
+set ::env(BASE_SDC_FILE) "base.sdc"
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 set ::env(SYNTH_CAP_LOAD) "17.65"

diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 96e390e..03d8be4 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h36m28s,0h16m19s,27778.888888888887,1.8,13889.444444444443,18,1131.94,25001,0,0,0,0,0,0,0,74,3,-1,0,1325964,199950,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1100394978,0.0,14.95,14.15,2.89,0.96,-1,24824,25125,2879,3180,0,0,0,25001,532,68,543,604,2798,755,155,7438,2872,2842,106,866,22836,0,23702,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h52m12s,0h27m25s,27759.375,1.92,13879.6875,19,1195.43,26649,0,0,0,0,0,0,0,105,1,-1,0,1672470,234282,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1304827840,0.0,18.7,16.26,3.38,0.29,-1,26472,26773,3391,3692,0,0,0,26649,876,68,661,601,2743,980,298,7804,3218,3182,68,866,24574,1,25441,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,3

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index d82e1f3..152ff0b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h36m12s,0h3m45s,3.3079078455790785,10.2784,1.6539539227895392,0,552.84,17,0,0,0,0,0,0,0,0,1,-1,-1,1189440,3984,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.27,4.31,0.7,1.74,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h47m31s,0h4m45s,3.3079078455790785,10.2784,1.6539539227895392,0,552.5,17,0,0,0,0,0,0,0,0,1,-1,-1,1189752,3991,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.27,4.33,0.76,1.88,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0

diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 29925ab..ea393bf 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v

@@ -95,6 +95,8 @@
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
@@ -113,6 +115,7 @@
      `include "syntacore/scr1/src/top/scr1_timer.sv"
      `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
      `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_intf.sv"
      `include "syntacore/scr1/src/top/scr1_top_wb.sv"
      `include "lib/sync_fifo.sv"
 

diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 5abdac9..e11cffd 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v

@@ -155,7 +155,7 @@
 
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (20) begin
+		repeat (30) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end

diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
index 29925ab..ea393bf 100644
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ b/verilog/dv/user_spi/uprj_netlists.v

@@ -95,6 +95,8 @@
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
@@ -113,6 +115,7 @@
      `include "syntacore/scr1/src/top/scr1_timer.sv"
      `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
      `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_intf.sv"
      `include "syntacore/scr1/src/top/scr1_top_wb.sv"
      `include "lib/sync_fifo.sv"
 

diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 89364ec..aedc4d8 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v

@@ -93,6 +93,8 @@
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
@@ -111,6 +113,7 @@
      `include "syntacore/scr1/src/top/scr1_timer.sv"
      `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
      `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_intf.sv"
      `include "syntacore/scr1/src/top/scr1_top_wb.sv"
      `include "lib/sync_fifo.sv"
 

diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
index 433ed93..27ae857 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv

@@ -743,7 +743,7 @@
                             | (exu_queue_vd & jb_taken);
 
 // Jump/branch signals
-assign branch_taken = exu_queue.branch_req & ialu_cmp;
+assign branch_taken = exu_queue.branch_req & ialu_cmp & ialu_rdy;
 assign jb_taken     = exu_queue.jump_req | branch_taken;
 assign jb_new_pc    = ialu_addr_res & SCR1_JUMP_MASK;
 

diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
index 922a518..eabaf49 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv

@@ -17,7 +17,10 @@
 // //////////////////////////////////////////////////////////////////////////
 /// @file       <scr1_pipe_ialu.sv>
 /// @brief      Integer Arithmetic Logic Unit (IALU)
-///
+////     Ver 0.1 - 18th July 2021, Dinesh A, project: yifive
+////           A. For Timing Reason, Input and Output are registered
+////              Added SCR1_GOLDEN define to preserve the Previous Logic
+////////////////////////////////////////////////////////////////////////////
 
 //-------------------------------------------------------------------------------
  //
@@ -70,16 +73,10 @@
 //-------------------------------------------------------------------------------
 
 `ifdef SCR1_RVM_EXT
- `ifdef SCR1_FAST_MUL
 localparam SCR1_MUL_WIDTH     = `SCR1_XLEN;
 localparam SCR1_MUL_RES_WIDTH = 2 * `SCR1_XLEN;
 localparam SCR1_MDU_SUM_WIDTH = `SCR1_XLEN + 1;
- `else
-localparam SCR1_MUL_STG_NUM   = 32;
-localparam SCR1_MUL_WIDTH     = 32 / SCR1_MUL_STG_NUM;
-localparam SCR1_MUL_CNT_INIT  = 32'b1 << (`SCR1_XLEN/SCR1_MUL_WIDTH - 2);
-localparam SCR1_MDU_SUM_WIDTH = `SCR1_XLEN + SCR1_MUL_WIDTH;
- `endif // ~SCR1_FAST_MUL
+
 localparam SCR1_DIV_WIDTH     = 1;
 localparam SCR1_DIV_CNT_INIT  = 32'b1 << (`SCR1_XLEN/SCR1_DIV_WIDTH - 2);
 `endif // SCR1_RVM_EXT
@@ -130,31 +127,13 @@
 
 // MUL/DIV signals
 `ifdef SCR1_RVM_EXT
-// MUL/DIV FSM control signals
-logic                                       mdu_cmd_is_iter;    // MDU Command is iterative
-logic                                       mdu_iter_req;       // Request iterative stage
-logic                                       mdu_iter_rdy;       // Iteration is ready
-logic                                       mdu_corr_req;       // DIV/REM(U) correction request
-logic                                       div_corr_req;       // Correction request for DIV operation
-logic                                       rem_corr_req;       // Correction request for REM(U) operations
-
-// MUL/DIV FSM signals
-logic [1:0]                                 mdu_fsm_ff;         // Current FSM state
-logic [1:0]                                 mdu_fsm_next;       // Next FSM state
-logic                                       mdu_fsm_idle;       // MDU FSM is in IDLE state
-`ifdef SCR1_TRGT_SIMULATION
-logic                                       mdu_fsm_iter;       // MDU FSM is in ITER state
-`endif // SCR1_TRGT_SIMULATION
-logic                                       mdu_fsm_corr;       // MDU FSM is in CORR state
 
 // MDU command signals
-logic [1:0]                                 mdu_cmd;            // MDU command: 00 - NONE, 01 - MUL,  10 - DIV
 logic                                       mdu_cmd_mul;        // MDU command is MUL(HSU)
 logic                                       mdu_cmd_div;        // MDU command is DIV(U)/REM(U)
 logic        [1:0]                          mul_cmd;            // MUL command: 00 - MUL,  01 - MULH, 10 - MULHSU, 11 - MULHU
 logic                                       mul_cmd_hi;         // High part of MUL result is requested
 logic        [1:0]                          div_cmd;            // DIV command: 00 - DIV,  01 - DIVU, 10 - REM,    11 - REMU
-logic                                       div_cmd_div;        // DIV command is DIV
 logic                                       div_cmd_rem;        // DIV command is REM(U)
 
 // Multiplier signals
@@ -164,47 +143,96 @@
 logic                                       mul_op2_sgn;        // Second MUL operand is negative
 logic signed [`SCR1_XLEN:0]                 mul_op1;            // MUL operand 1
 logic signed [SCR1_MUL_WIDTH:0]             mul_op2;            // MUL operand 1
- `ifdef SCR1_FAST_MUL
 logic signed [SCR1_MUL_RES_WIDTH-1:0]       mul_res;            // MUL result
- `else // ~SCR1_FAST_MUL
-logic signed [SCR1_MDU_SUM_WIDTH:0]         mul_part_prod;
-logic        [`SCR1_XLEN-1:0]               mul_res_hi;
-logic        [`SCR1_XLEN-1:0]               mul_res_lo;
- `endif // ~SCR1_FAST_MUL
 
 // Divisor signals
+logic signed [`SCR1_XLEN:0]                 div_op1;            // DIV operand 1
+logic signed [SCR1_MUL_WIDTH:0]             div_op2;            // DIV operand 2
 logic                                       div_ops_are_sgn;
 logic                                       div_op1_is_neg;
 logic                                       div_op2_is_neg;
-logic                                       div_res_rem_c;
 logic        [`SCR1_XLEN-1:0]               div_res_rem;
 logic        [`SCR1_XLEN-1:0]               div_res_quo;
-logic                                       div_quo_bit;
-logic                                       div_dvdnd_lo_upd;
-logic        [`SCR1_XLEN-1:0]               div_dvdnd_lo_ff;
-logic        [`SCR1_XLEN-1:0]               div_dvdnd_lo_next;
 
-// MDU adder signals
-logic                                       mdu_sum_sub;        // MDU adder operation: 0 - add, 1 - sub
-logic signed [SCR1_MDU_SUM_WIDTH-1:0]       mdu_sum_op1;        // MDU adder operand 1
-logic signed [SCR1_MDU_SUM_WIDTH-1:0]       mdu_sum_op2;        // MDU adder operand 2
-logic signed [SCR1_MDU_SUM_WIDTH-1:0]       mdu_sum_res;        // MDU adder result
 
-// MDU iteration counter signals
-logic                                       mdu_iter_cnt_en;
-logic        [`SCR1_XLEN-1:0]               mdu_iter_cnt;
-logic        [`SCR1_XLEN-1:0]               mdu_iter_cnt_next;
-
-// Intermediate results registers
-logic                                       mdu_res_upd;
-logic                                       mdu_res_c_ff;
-logic                                       mdu_res_c_next;
-logic        [`SCR1_XLEN-1:0]               mdu_res_hi_ff;
-logic        [`SCR1_XLEN-1:0]               mdu_res_hi_next;
-logic        [`SCR1_XLEN-1:0]               mdu_res_lo_ff;
-logic        [`SCR1_XLEN-1:0]               mdu_res_lo_next;
 `endif // SCR1_RVM_EXT
 
+
+//-------------------------------------------------------
+// Adding Input Register to break Timing Path 
+// ------------------------------------------------------
+logic [`SCR1_XLEN-1:0]          exu2ialu_main_op1_ff;        // main ALU 1st operand
+logic [`SCR1_XLEN-1:0]          exu2ialu_main_op2_ff;        // main ALU 2nd operand
+type_scr1_ialu_cmd_sel_e        exu2ialu_cmd_ff;             // IALU command
+logic                           exu2ialu_rvm_cmd_vd_ff;      // MUL/DIV command valid
+logic [`SCR1_XLEN-1:0]          ialu2exu_main_res_i;        // main ALU result
+logic                           ialu2exu_cmp_res_i;         // IALU comparison result
+logic                           ialu2exu_rvm_res_rdy_i;     // MUL/DIV result ready
+logic                           ialu_rdy        ;           // ialu ready
+logic                           ialu_data_pdone ;           // ialu data process done
+
+
+`ifdef SCR1_GOLDEN
+assign	exu2ialu_main_op1_ff = exu2ialu_main_op1_i;
+assign  exu2ialu_main_op2_ff = exu2ialu_main_op2_i;
+assign  exu2ialu_cmd_ff      = exu2ialu_cmd_i;
+assign	exu2ialu_rvm_cmd_vd_ff = exu2ialu_rvm_cmd_vd_i;
+
+assign	ialu2exu_main_res_o     = ialu2exu_main_res_i;
+assign  ialu2exu_cmp_res_o      = ialu2exu_cmp_res_i;
+assign  ialu2exu_rvm_res_rdy_o  = ialu2exu_rvm_res_rdy_i;
+assign  ialu_rdy                = 1; 
+
+`else
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+	exu2ialu_main_op1_ff <= '0;
+        exu2ialu_main_op2_ff <= '0;
+        exu2ialu_cmd_ff      <= '0;
+	exu2ialu_rvm_cmd_vd_ff <= '0;
+    end else begin
+	exu2ialu_main_op1_ff <= exu2ialu_main_op1_i;
+        exu2ialu_main_op2_ff <= exu2ialu_main_op2_i;
+        exu2ialu_cmd_ff      <= exu2ialu_cmd_i;
+	exu2ialu_rvm_cmd_vd_ff <= exu2ialu_rvm_cmd_vd_i;
+    end
+end
+
+//-------------------------------------------------------
+// Adding Output Register to break Timing Path 
+// ------------------------------------------------------
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+	ialu2exu_main_res_o         <= '0;
+        ialu2exu_cmp_res_o          <= '0;
+        ialu2exu_rvm_res_rdy_o      <= '0;
+	ialu_data_pdone             <= '0;
+    end else begin
+	ialu_data_pdone             <= ialu2exu_rvm_res_rdy_o; // generate one cycle delayed process done
+	ialu2exu_main_res_o         <= ialu2exu_main_res_i;
+        ialu2exu_cmp_res_o          <= ialu2exu_cmp_res_i;
+        ialu2exu_rvm_res_rdy_o      <= ialu2exu_rvm_res_rdy_i;
+    end
+end
+
+//-------------------------------------------------------
+// Creating Two cycle Latency to break timing path
+// One Cycle for Register Input + One Cycle Registered Output
+// -----------------------------------------------------
+logic cmd_vd_d;
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+	cmd_vd_d <= '0;
+        ialu_rdy <= '0;
+    end else begin
+	cmd_vd_d <= exu2ialu_rvm_cmd_vd_i & (ialu_rdy ==0);
+        ialu_rdy <= cmd_vd_d & exu2ialu_rvm_cmd_vd_i & (ialu_rdy ==0) ;
+    end
+end
+
+`endif
+
 //-------------------------------------------------------------------------------
 // Main adder
 //-------------------------------------------------------------------------------
@@ -218,15 +246,15 @@
 // Carry out (MSB of main_sum_res) is evaluated correctly because the result
 // width equals to the maximum width of both the right-hand and left-hand side variables
 always_comb begin
-    main_sum_res = (exu2ialu_cmd_i != SCR1_IALU_CMD_ADD)
-                 ? (exu2ialu_main_op1_i - exu2ialu_main_op2_i)   // Subtraction and comparison
-                 : (exu2ialu_main_op1_i + exu2ialu_main_op2_i);  // Addition
+    main_sum_res = (exu2ialu_cmd_ff != SCR1_IALU_CMD_ADD)
+                 ? (exu2ialu_main_op1_ff - exu2ialu_main_op2_ff)   // Subtraction and comparison
+                 : (exu2ialu_main_op1_ff + exu2ialu_main_op2_ff);  // Addition
 
-    main_sum_pos_ovflw = ~exu2ialu_main_op1_i[`SCR1_XLEN-1]
-                       &  exu2ialu_main_op2_i[`SCR1_XLEN-1]
+    main_sum_pos_ovflw = ~exu2ialu_main_op1_ff[`SCR1_XLEN-1]
+                       &  exu2ialu_main_op2_ff[`SCR1_XLEN-1]
                        &  main_sum_res[`SCR1_XLEN-1];
-    main_sum_neg_ovflw =  exu2ialu_main_op1_i[`SCR1_XLEN-1]
-                       & ~exu2ialu_main_op2_i[`SCR1_XLEN-1]
+    main_sum_neg_ovflw =  exu2ialu_main_op1_ff[`SCR1_XLEN-1]
+                       & ~exu2ialu_main_op2_ff[`SCR1_XLEN-1]
                        & ~main_sum_res[`SCR1_XLEN-1];
 
     // FLAGS1 - flags for comparison (result of subtraction)
@@ -260,17 +288,17 @@
  // - Arithmetic right shift  (SRAI/SRA)
 //
 
-assign ialu_cmd_shft = (exu2ialu_cmd_i == SCR1_IALU_CMD_SLL)
-                     | (exu2ialu_cmd_i == SCR1_IALU_CMD_SRL)
-                     | (exu2ialu_cmd_i == SCR1_IALU_CMD_SRA);
+assign ialu_cmd_shft = (exu2ialu_cmd_ff == SCR1_IALU_CMD_SLL)
+                     | (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRL)
+                     | (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRA);
 assign shft_cmd      = ialu_cmd_shft
-                     ? {(exu2ialu_cmd_i != SCR1_IALU_CMD_SLL),
-                        (exu2ialu_cmd_i == SCR1_IALU_CMD_SRA)}
+                     ? {(exu2ialu_cmd_ff != SCR1_IALU_CMD_SLL),
+                        (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRA)}
                      : 2'b00;
 
 always_comb begin
-    shft_op1 = exu2ialu_main_op1_i;
-    shft_op2 = exu2ialu_main_op2_i[4:0];
+    shft_op1 = exu2ialu_main_op1_ff;
+    shft_op2 = exu2ialu_main_op2_ff[4:0];
     case (shft_cmd)
         2'b10   : shft_res = shft_op1  >> shft_op2;
         2'b11   : shft_res = shft_op1 >>> shft_op2;
@@ -297,273 +325,106 @@
 // MUL/DIV FSM Control logic
 //-------------------------------------------------------------------------------
 
-assign mdu_cmd_div = (exu2ialu_cmd_i == SCR1_IALU_CMD_DIV)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_DIVU)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_REM)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_REMU);
-assign mdu_cmd_mul = (exu2ialu_cmd_i == SCR1_IALU_CMD_MUL)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_MULH)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_MULHU)
-                   | (exu2ialu_cmd_i == SCR1_IALU_CMD_MULHSU);
+assign mdu_cmd_div = ((exu2ialu_cmd_ff == SCR1_IALU_CMD_DIV)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_DIVU)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REM)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU)) & exu2ialu_rvm_cmd_vd_ff;
+assign mdu_cmd_mul = ((exu2ialu_cmd_ff == SCR1_IALU_CMD_MUL)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULH)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU)
+                   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHSU)) & exu2ialu_rvm_cmd_vd_ff;
 
-assign mdu_cmd     = mdu_cmd_div ? SCR1_IALU_MDU_DIV
-                   : mdu_cmd_mul ? SCR1_IALU_MDU_MUL
-                                 : SCR1_IALU_MDU_NONE;
 
-assign main_ops_non_zero = |exu2ialu_main_op1_i & |exu2ialu_main_op2_i;
-assign main_ops_diff_sgn = exu2ialu_main_op1_i[`SCR1_XLEN-1]
-                         ^ exu2ialu_main_op2_i[`SCR1_XLEN-1];
+assign main_ops_non_zero = |exu2ialu_main_op1_ff & |exu2ialu_main_op2_ff;
+assign main_ops_diff_sgn = exu2ialu_main_op1_ff[`SCR1_XLEN-1]
+                         ^ exu2ialu_main_op2_ff[`SCR1_XLEN-1];
 
- `ifdef SCR1_FAST_MUL
-    assign mdu_cmd_is_iter = mdu_cmd_div;
- `else // ~SCR1_FAST_MUL
-    assign mdu_cmd_is_iter = mdu_cmd_mul | mdu_cmd_div;
- `endif // ~SCR1_FAST_MUL
 
-assign mdu_iter_req = mdu_cmd_is_iter ? (main_ops_non_zero & mdu_fsm_idle) : 1'b0;
-assign mdu_iter_rdy = mdu_iter_cnt[0];
 
-assign div_cmd_div = (div_cmd == 2'b00);
 assign div_cmd_rem = div_cmd[1];
 
-// Correction request signals
-assign div_corr_req = div_cmd_div & main_ops_diff_sgn;
-assign rem_corr_req = div_cmd_rem & |div_res_rem & (div_op1_is_neg ^ div_res_rem_c);
-assign mdu_corr_req = mdu_cmd_div & (div_corr_req | rem_corr_req);
 
-// MDU iteration counter
-//------------------------------------------------------------------------------
-
-assign mdu_iter_cnt_en = exu2ialu_rvm_cmd_vd_i & ~ialu2exu_rvm_res_rdy_o;
-
-always_ff @(posedge clk) begin
-    if (mdu_iter_cnt_en) begin
-        mdu_iter_cnt <= mdu_iter_cnt_next;
-    end
-end
-
-assign mdu_iter_cnt_next = ~mdu_fsm_idle ? mdu_iter_cnt >> 1
-                         : mdu_cmd_div   ? SCR1_DIV_CNT_INIT
- `ifndef SCR1_FAST_MUL
-                         : mdu_cmd_mul   ? SCR1_MUL_CNT_INIT
- `endif // ~SCR1_FAST_MUL
-                                         : mdu_iter_cnt;
-
-//-------------------------------------------------------------------------------
-// MUL/DIV FSM
-//-------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
-    if (~rst_n) begin
-        mdu_fsm_ff <= SCR1_IALU_MDU_FSM_IDLE;
-    end else begin
-        mdu_fsm_ff <= mdu_fsm_next;
-    end
-end
-
-always_comb begin
-    mdu_fsm_next = SCR1_IALU_MDU_FSM_IDLE;
-
-    if (exu2ialu_rvm_cmd_vd_i) begin
-        case (mdu_fsm_ff)
-            SCR1_IALU_MDU_FSM_IDLE : begin
-                mdu_fsm_next = mdu_iter_req  ? SCR1_IALU_MDU_FSM_ITER
-                                             : SCR1_IALU_MDU_FSM_IDLE;
-            end
-            SCR1_IALU_MDU_FSM_ITER : begin
-                mdu_fsm_next = ~mdu_iter_rdy ? SCR1_IALU_MDU_FSM_ITER
-                             : mdu_corr_req  ? SCR1_IALU_MDU_FSM_CORR
-                                             : SCR1_IALU_MDU_FSM_IDLE;
-            end
-            SCR1_IALU_MDU_FSM_CORR : begin
-                mdu_fsm_next = SCR1_IALU_MDU_FSM_IDLE;
-            end
-        endcase
-    end
-end
-
-assign mdu_fsm_idle = (mdu_fsm_ff == SCR1_IALU_MDU_FSM_IDLE);
-`ifdef SCR1_TRGT_SIMULATION
-assign mdu_fsm_iter = (mdu_fsm_ff == SCR1_IALU_MDU_FSM_ITER);
-`endif // SCR1_TRGT_SIMULATION
-assign mdu_fsm_corr = (mdu_fsm_ff == SCR1_IALU_MDU_FSM_CORR);
 
 //-------------------------------------------------------------------------------
 // Multiplier logic
 //-------------------------------------------------------------------------------
 //
- // Multiplication has 2 options: fast (1 cycle) and Radix-2 (32 cycles) multiplication.
+ // Multiplication has 2 options: fast (1 cycle) and Radix-2 (8 cycles) multiplication.
  //
  // 1. Fast multiplication uses the straightforward approach when 2 operands are
  // multiplied in one cycle
  //
- // 2. Radix-2 multiplication uses 2 registers (high and low part of multiplication)
+ // 2. Radix-2 multiplication does 4bit multication at time
  //
- // Radix-2 algorithm:
- // 1. Initialize registers
- // 2. Create a partial product by multiplying multiplicand by the LSB of multiplier
- // 3. Add the partial product to the previous (intermediate) value of multiplication
- //    result (stored into high and low parts of multiplication result register)
- // 4. Shift the low part of multiplication result register right
- // 4. Store the addition result into the high part of multiplication result register
- // 6. If iteration is not ready, go to step 2. Otherwise multiplication is done
  //
 //
 
-assign mul_cmd  = {((exu2ialu_cmd_i == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_i == SCR1_IALU_CMD_MULHSU)),
-                   ((exu2ialu_cmd_i == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_i == SCR1_IALU_CMD_MULH))};
+assign mul_cmd  = {((exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHSU)),
+                   ((exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULH))};
 
 assign mul_cmd_hi     = |mul_cmd;
 assign mul_op1_is_sgn = ~&mul_cmd;
 assign mul_op2_is_sgn = ~mul_cmd[1];
-assign mul_op1_sgn    = mul_op1_is_sgn & exu2ialu_main_op1_i[`SCR1_XLEN-1];
-assign mul_op2_sgn    = mul_op2_is_sgn & exu2ialu_main_op2_i[`SCR1_XLEN-1];
+assign mul_op1_sgn    = mul_op1_is_sgn & exu2ialu_main_op1_ff[`SCR1_XLEN-1];
+assign mul_op2_sgn    = mul_op2_is_sgn & exu2ialu_main_op2_ff[`SCR1_XLEN-1];
 
 `ifdef SCR1_FAST_MUL
-assign mul_op1 = mdu_cmd_mul ? $signed({mul_op1_sgn, exu2ialu_main_op1_i}) : '0;
-assign mul_op2 = mdu_cmd_mul ? $signed({mul_op2_sgn, exu2ialu_main_op2_i}) : '0;
+assign mul_op1 = mdu_cmd_mul ? $signed({mul_op1_sgn, exu2ialu_main_op1_ff}) : '0;
+assign mul_op2 = mdu_cmd_mul ? $signed({mul_op2_sgn, exu2ialu_main_op2_ff}) : '0;
 assign mul_res = mdu_cmd_mul ? mul_op1 * mul_op2                           : 'sb0;
 `else // ~SCR1_FAST_MUL
-assign mul_op1 = mdu_cmd_mul  ? $signed({mul_op1_sgn, exu2ialu_main_op1_i}) : '0;
-assign mul_op2 = ~mdu_cmd_mul ? '0
-               : mdu_fsm_idle ? $signed({1'b0, exu2ialu_main_op2_i[SCR1_MUL_WIDTH-1:0]})
-                              : $signed({(mdu_iter_cnt[0] & mul_op2_is_sgn & mdu_res_lo_ff[SCR1_MUL_WIDTH-1]),
-                                          mdu_res_lo_ff[SCR1_MUL_WIDTH-1:0]});
 
-assign mul_part_prod            = mdu_cmd_mul  ? mul_op1 * mul_op2 : 'sb0;
-assign {mul_res_hi, mul_res_lo} = ~mdu_cmd_mul ? '0
-                                : mdu_fsm_idle ? ({mdu_sum_res, exu2ialu_main_op2_i[`SCR1_XLEN-1:SCR1_MUL_WIDTH]})
-                                               : ({mdu_sum_res, mdu_res_lo_ff[`SCR1_XLEN-1:SCR1_MUL_WIDTH]});
+assign mul_op1 = mdu_cmd_mul ? $signed({mul_op1_sgn, exu2ialu_main_op1_ff}) : '0;
+assign mul_op2 = mdu_cmd_mul ? $signed({mul_op2_sgn, exu2ialu_main_op2_ff}) : '0;
+
+logic mul_rdy;
+
+scr1_pipe_mul u_mul(
+	.clk          (clk), 
+	.rstn         (rst_n), 
+	.data_valid   (mdu_cmd_mul),   // input valid
+	.Din1         (mul_op1),       // first operand
+	.Din2         (mul_op2),       // second operand
+	.des_hig      (mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]),    // first result
+	.des_low      (mul_res[`SCR1_XLEN-1:0]),    // second result
+	.mul_rdy_o    (mul_rdy),      // Multiply result ready
+	.data_done    (ialu_data_pdone)    // data_process_done
+    );
+
+
 `endif // ~SCR1_FAST_MUL
 
+
+
 //-------------------------------------------------------------------------------
 // Divider logic
 //-------------------------------------------------------------------------------
-//
- // Division uses a non-restoring algorithm. 3 registers are used:
- // - Remainder register
- // - Quotient register
- // - Dividend low part register (for corner case quotient bit calculation)
- //
- // Algorithm:
- // 1. Initialize registers
- // 2. Shift remainder and dividend low part registers left
- // 3. Compare remainder register with the divisor (taking previous quotient bit
- //    and operands signs into account) and calculate quotient bit based on the
- //    comparison results
- // 4. Shift quotient register left, append quotient bit to the quotient register
- // 5. If iteration is not ready, go to step 2. Otherwise go to step 6
- // 6. Do correction if necessary, otherwise division is done
- //
- // Quotient bit calculation has a corner case:
- // When dividend is negative result carry bit check takes into account only
- // the case of remainder register been greater than divisor. To handle
- // equality case we should check if both the comparison result and the
- // lower part of dividend are zero
-//
 
-assign div_cmd  = {((exu2ialu_cmd_i == SCR1_IALU_CMD_REM)   | (exu2ialu_cmd_i == SCR1_IALU_CMD_REMU)),
-                   ((exu2ialu_cmd_i == SCR1_IALU_CMD_REMU)  | (exu2ialu_cmd_i == SCR1_IALU_CMD_DIVU))};
+assign div_cmd  = {((exu2ialu_cmd_ff == SCR1_IALU_CMD_REM)   | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU)),
+                   ((exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU)  | (exu2ialu_cmd_ff == SCR1_IALU_CMD_DIVU))};
 
 assign div_ops_are_sgn = ~div_cmd[0];
-assign div_op1_is_neg  = div_ops_are_sgn & exu2ialu_main_op1_i[`SCR1_XLEN-1];
-assign div_op2_is_neg  = div_ops_are_sgn & exu2ialu_main_op2_i[`SCR1_XLEN-1];
+assign div_op1_is_neg  = div_ops_are_sgn & exu2ialu_main_op1_ff[`SCR1_XLEN-1];
+assign div_op2_is_neg  = div_ops_are_sgn & exu2ialu_main_op2_ff[`SCR1_XLEN-1];
 
-always_comb begin
-    div_res_rem_c = '0;
-    div_res_rem   = '0;
-    div_res_quo   = '0;
-    div_quo_bit   = 1'b0;
-    if (mdu_cmd_div & ~mdu_fsm_corr) begin
-        div_res_rem_c = mdu_sum_res[SCR1_MDU_SUM_WIDTH-1];
-        div_res_rem   = mdu_sum_res[SCR1_MDU_SUM_WIDTH-2:0];
-        div_quo_bit   = ~(div_op1_is_neg ^ div_res_rem_c)
-                      | (div_op1_is_neg & ({mdu_sum_res, div_dvdnd_lo_next} == '0));
-        div_res_quo   = mdu_fsm_idle
-                      ? {'0, div_quo_bit}
-                      : {mdu_res_lo_ff[`SCR1_XLEN-2:0], div_quo_bit};
-    end
-end
+assign div_op1 = mdu_cmd_div ? $signed({div_op1_is_neg, exu2ialu_main_op1_ff}) : '0;
+assign div_op2 = mdu_cmd_div ? $signed({div_op2_is_neg, exu2ialu_main_op2_ff}) : '0;
 
-// Dividend low part register
-//------------------------------------------------------------------------------
+logic div_rdy;
 
-assign div_dvdnd_lo_upd = exu2ialu_rvm_cmd_vd_i & ~ialu2exu_rvm_res_rdy_o;
+scr1_pipe_div u_div(
+	.clk          (clk), 
+	.rstn         (rst_n), 
+	.data_valid   (mdu_cmd_div),   // input valid
+	.Din1         (div_op1),       // first operand
+	.Din2         (div_op2),       // second operand
+	.quotient     (div_res_quo),   // Remainder
+	.remainder    (div_res_rem),   // Quotient
+	.div_rdy_o    (div_rdy),       // Divide result ready
+	.data_done    (ialu_data_pdone)     // data_process_done
+    );
 
-always_ff @(posedge clk) begin
-    if (div_dvdnd_lo_upd) begin
-        div_dvdnd_lo_ff <= div_dvdnd_lo_next;
-    end
-end
 
-assign div_dvdnd_lo_next = (~mdu_cmd_div | mdu_fsm_corr) ? '0
-                         : mdu_fsm_idle                  ? exu2ialu_main_op1_i << 1
-                                                         : div_dvdnd_lo_ff     << 1;
-
-//-------------------------------------------------------------------------------
-// MDU adder
-//-------------------------------------------------------------------------------
-logic           sgn;
-logic           inv;
-
-always_comb begin
-    mdu_sum_sub    = 1'b0;
-    mdu_sum_op1    = '0;
-    mdu_sum_op2    = '0;
-    sgn            = '0; // yosys - latch fix
-    inv            = '0; // yosys - latch fix
-    case (mdu_cmd)
-        SCR1_IALU_MDU_DIV : begin
-            sgn         = mdu_fsm_corr ? div_op1_is_neg ^ mdu_res_c_ff
-                        : mdu_fsm_idle ? 1'b0
-                                       : ~mdu_res_lo_ff[0];
-            inv         = div_ops_are_sgn & main_ops_diff_sgn;
-            mdu_sum_sub = ~inv ^ sgn;
-            mdu_sum_op1 = mdu_fsm_corr ? $signed({1'b0, mdu_res_hi_ff})
-                        : mdu_fsm_idle ? $signed({div_op1_is_neg, exu2ialu_main_op1_i[`SCR1_XLEN-1]})
-                                       : $signed({mdu_res_hi_ff, div_dvdnd_lo_ff[`SCR1_XLEN-1]});
-            mdu_sum_op2 = $signed({div_op2_is_neg, exu2ialu_main_op2_i});
-        end
-`ifndef SCR1_FAST_MUL
-        SCR1_IALU_MDU_MUL : begin
-            mdu_sum_op1 = mdu_fsm_idle
-                        ? '0
-                        : $signed({(mul_op1_is_sgn & mdu_res_hi_ff[`SCR1_XLEN-1]), mdu_res_hi_ff});
-            mdu_sum_op2 = mul_part_prod;
-        end
-`endif // SCR1_FAST_MUL
-        default : begin end
-    endcase
-    mdu_sum_res = mdu_sum_sub
-                ? (mdu_sum_op1 - mdu_sum_op2)
-                : (mdu_sum_op1 + mdu_sum_op2);
-end
-
-//-------------------------------------------------------------------------------
-// MUL/DIV intermediate results registers
-//-------------------------------------------------------------------------------
-
-assign mdu_res_upd = exu2ialu_rvm_cmd_vd_i & ~ialu2exu_rvm_res_rdy_o;
-
-always_ff @(posedge clk) begin
-    if (mdu_res_upd) begin
-        mdu_res_c_ff  <= mdu_res_c_next;
-        mdu_res_hi_ff <= mdu_res_hi_next;
-        mdu_res_lo_ff <= mdu_res_lo_next;
-    end
-end
-
-assign mdu_res_c_next  = mdu_cmd_div ? div_res_rem_c : mdu_res_c_ff;
-assign mdu_res_hi_next = mdu_cmd_div ? div_res_rem
- `ifndef SCR1_FAST_MUL
-                       : mdu_cmd_mul ? mul_res_hi
- `endif // SCR1_FAST_MUL
-                                     : mdu_res_hi_ff;
-assign mdu_res_lo_next = mdu_cmd_div ? div_res_quo
- `ifndef SCR1_FAST_MUL
-                       : mdu_cmd_mul ? mul_res_lo
- `endif // SCR1_FAST_MUL
-                                     : mdu_res_lo_ff;
 `endif // SCR1_RVM_EXT
 
 //-------------------------------------------------------------------------------
@@ -571,56 +432,66 @@
 //-------------------------------------------------------------------------------
 
 always_comb begin
-    ialu2exu_main_res_o    = '0;
-    ialu2exu_cmp_res_o     = 1'b0;
-`ifdef SCR1_RVM_EXT
-    ialu2exu_rvm_res_rdy_o = 1'b1;
-`endif // SCR1_RVM_EXT
+    ialu2exu_main_res_i    = '0;
+    ialu2exu_cmp_res_i     = 1'b0;
+    ialu2exu_rvm_res_rdy_i = 1'b0;
 
-    case (exu2ialu_cmd_i)
+    case (exu2ialu_cmd_ff)
         SCR1_IALU_CMD_AND : begin
-            ialu2exu_main_res_o = exu2ialu_main_op1_i & exu2ialu_main_op2_i;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = exu2ialu_main_op1_ff & exu2ialu_main_op2_ff;
         end
         SCR1_IALU_CMD_OR : begin
-            ialu2exu_main_res_o = exu2ialu_main_op1_i | exu2ialu_main_op2_i;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = exu2ialu_main_op1_ff | exu2ialu_main_op2_ff;
         end
         SCR1_IALU_CMD_XOR : begin
-            ialu2exu_main_res_o = exu2ialu_main_op1_i ^ exu2ialu_main_op2_i;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = exu2ialu_main_op1_ff ^ exu2ialu_main_op2_ff;
         end
         SCR1_IALU_CMD_ADD : begin
-            ialu2exu_main_res_o = main_sum_res[`SCR1_XLEN-1:0];
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = main_sum_res[`SCR1_XLEN-1:0];
         end
         SCR1_IALU_CMD_SUB : begin
-            ialu2exu_main_res_o = main_sum_res[`SCR1_XLEN-1:0];
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = main_sum_res[`SCR1_XLEN-1:0];
         end
         SCR1_IALU_CMD_SUB_LT : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(main_sum_flags.s ^ main_sum_flags.o);
-            ialu2exu_cmp_res_o  = main_sum_flags.s ^ main_sum_flags.o;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.s ^ main_sum_flags.o);
+            ialu2exu_cmp_res_i  = main_sum_flags.s ^ main_sum_flags.o;
         end
         SCR1_IALU_CMD_SUB_LTU : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(main_sum_flags.c);
-            ialu2exu_cmp_res_o  = main_sum_flags.c;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.c);
+            ialu2exu_cmp_res_i  = main_sum_flags.c;
         end
         SCR1_IALU_CMD_SUB_EQ : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(main_sum_flags.z);
-            ialu2exu_cmp_res_o  = main_sum_flags.z;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.z);
+            ialu2exu_cmp_res_i  = main_sum_flags.z;
         end
         SCR1_IALU_CMD_SUB_NE : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(~main_sum_flags.z);
-            ialu2exu_cmp_res_o  = ~main_sum_flags.z;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(~main_sum_flags.z);
+            ialu2exu_cmp_res_i  = ~main_sum_flags.z;
         end
         SCR1_IALU_CMD_SUB_GE : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(~(main_sum_flags.s ^ main_sum_flags.o));
-            ialu2exu_cmp_res_o  = ~(main_sum_flags.s ^ main_sum_flags.o);
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(~(main_sum_flags.s ^ main_sum_flags.o));
+            ialu2exu_cmp_res_i  = ~(main_sum_flags.s ^ main_sum_flags.o);
         end
         SCR1_IALU_CMD_SUB_GEU : begin
-            ialu2exu_main_res_o = `SCR1_XLEN'(~main_sum_flags.c);
-            ialu2exu_cmp_res_o  = ~main_sum_flags.c;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = `SCR1_XLEN'(~main_sum_flags.c);
+            ialu2exu_cmp_res_i  = ~main_sum_flags.c;
         end
         SCR1_IALU_CMD_SLL,
         SCR1_IALU_CMD_SRL,
         SCR1_IALU_CMD_SRA: begin
-            ialu2exu_main_res_o = shft_res;
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = shft_res;
         end
 `ifdef SCR1_RVM_EXT
         SCR1_IALU_CMD_MUL,
@@ -628,44 +499,23 @@
         SCR1_IALU_CMD_MULHSU,
         SCR1_IALU_CMD_MULH : begin
  `ifdef SCR1_FAST_MUL
-            ialu2exu_main_res_o = mul_cmd_hi
+            ialu2exu_rvm_res_rdy_i = ialu_rdy;
+            ialu2exu_main_res_i = mul_cmd_hi
                                 ? mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]
                                 : mul_res[`SCR1_XLEN-1:0];
  `else // ~SCR1_FAST_MUL
-            case (mdu_fsm_ff)
-                SCR1_IALU_MDU_FSM_IDLE : begin
-                    ialu2exu_main_res_o    = '0;
-                    ialu2exu_rvm_res_rdy_o = ~mdu_iter_req;
-                end
-                SCR1_IALU_MDU_FSM_ITER : begin
-                    ialu2exu_main_res_o    = mul_cmd_hi ? mul_res_hi : mul_res_lo;
-                    ialu2exu_rvm_res_rdy_o = mdu_iter_rdy;
-                end
-            endcase
+            ialu2exu_rvm_res_rdy_i = mul_rdy;
+            ialu2exu_main_res_i = mul_cmd_hi
+                                ? mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]
+                                : mul_res[`SCR1_XLEN-1:0];
  `endif // ~SCR1_FAST_MUL
         end
         SCR1_IALU_CMD_DIV,
         SCR1_IALU_CMD_DIVU,
         SCR1_IALU_CMD_REM,
         SCR1_IALU_CMD_REMU : begin
-            case (mdu_fsm_ff)
-                SCR1_IALU_MDU_FSM_IDLE : begin
-                    ialu2exu_main_res_o    = (|exu2ialu_main_op2_i | div_cmd_rem)
-                                           ? exu2ialu_main_op1_i
-                                           : '1;
-                    ialu2exu_rvm_res_rdy_o = ~mdu_iter_req;
-                end
-                SCR1_IALU_MDU_FSM_ITER : begin
-                    ialu2exu_main_res_o    = div_cmd_rem ? div_res_rem : div_res_quo;
-                    ialu2exu_rvm_res_rdy_o = mdu_iter_rdy & ~mdu_corr_req;
-                end
-                SCR1_IALU_MDU_FSM_CORR : begin
-                    ialu2exu_main_res_o    = div_cmd_rem
-                                           ? mdu_sum_res[`SCR1_XLEN-1:0]
-                                           : -mdu_res_lo_ff[`SCR1_XLEN-1:0];
-                    ialu2exu_rvm_res_rdy_o = 1'b1;
-                end
-            endcase
+            ialu2exu_main_res_i    = div_cmd_rem ? div_res_rem : div_res_quo;
+            ialu2exu_rvm_res_rdy_i = div_rdy;
         end
 `endif // SCR1_RVM_EXT
         default : begin end
@@ -682,55 +532,14 @@
 
 // X checks
 
-SCR1_SVA_IALU_XCHECK : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    !$isunknown({exu2ialu_rvm_cmd_vd_i, mdu_fsm_ff})
-    ) else $error("IALU Error: unknown values");
-
 SCR1_SVA_IALU_XCHECK_QUEUE : assert property (
     @(negedge clk) disable iff (~rst_n)
-    exu2ialu_rvm_cmd_vd_i |->
-    !$isunknown({exu2ialu_main_op1_i, exu2ialu_main_op2_i, exu2ialu_cmd_i})
+    exu2ialu_rvm_cmd_vd_ff |->
+    !$isunknown({exu2ialu_main_op1_ff, exu2ialu_main_op2_ff, exu2ialu_cmd_ff})
     ) else $error("IALU Error: unknown values in queue");
 
 // Behavior checks
 
-SCR1_SVA_IALU_ILL_STATE : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    $onehot0({~exu2ialu_rvm_cmd_vd_i, mdu_fsm_iter, mdu_fsm_corr})
-    ) else $error("IALU Error: illegal state");
-
-`ifndef VERILATOR    
-SCR1_SVA_IALU_JUMP_FROM_IDLE : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    (mdu_fsm_idle & (~exu2ialu_rvm_cmd_vd_i | ~mdu_iter_req)) |=> mdu_fsm_idle
-    ) else $error("EXU Error: illegal jump from IDLE state");
-
-SCR1_SVA_IALU_IDLE_TO_ITER : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    (mdu_fsm_idle & exu2ialu_rvm_cmd_vd_i & mdu_iter_req) |=> mdu_fsm_iter
-    ) else $error("EXU Error: illegal change state form IDLE to ITER");
-
-SCR1_SVA_IALU_JUMP_FROM_ITER : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    (mdu_fsm_iter & ~mdu_iter_rdy) |=> mdu_fsm_iter
-    ) else $error("EXU Error: illegal jump from ITER state");
-
-SCR1_SVA_IALU_ITER_TO_IDLE : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    (mdu_fsm_iter & mdu_iter_rdy & ~mdu_corr_req) |=> mdu_fsm_idle
-    ) else $error("EXU Error: illegal state change ITER to IDLE");
-
-SCR1_SVA_IALU_ITER_TO_CORR : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    (mdu_fsm_iter & mdu_iter_rdy & mdu_corr_req) |=> mdu_fsm_corr
-    ) else $error("EXU Error: illegal state change ITER to CORR");
-
-SCR1_SVA_IALU_CORR_TO_IDLE : assert property (
-    @(negedge clk) disable iff (~rst_n)
-    mdu_fsm_corr |=> mdu_fsm_idle
-    ) else $error("EXU Error: illegal state stay in CORR");
-`endif // VERILATOR
 
 `endif // SCR1_RVM_EXT
 

diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
index ee9164e..3b7f493 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv

@@ -19,7 +19,10 @@
 /// @file       <scr1_pipe_mprf.sv>
 /// @brief      Multi Port Register File (MPRF)
 ///
-
+///   Version 1.0 - Dinesh A - Project: yifive
+///                added additional stage FF to break timing path
+///                additional define SCRC1_MPRF_STAGE added
+//////////////////////////////////////////////////////////////////////////////
 `include "scr1_arch_description.svh"
 `include "scr1_arch_types.svh"
 

diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
index 634069e..467dd10 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv

@@ -618,7 +618,7 @@
  `ifdef SCR1_DBG_EN
     .rst_n                      (dbg_rst_n             ),
  `else
-    .rst_n                      (pipe_rst_n            ), // dinesh-a: Bugfix- reset correction when debug is not enabled
+    .rst_n                      (pipe_rst_n            ),
  `endif // SCR1_DBG_EN
     .clk                        (clk                   ),
     .clk_en                     (1'b1                  ),

diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
index a96c617..71b9928 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh

@@ -89,7 +89,7 @@
   `define SCR1_RVC_EXT
   parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26;
   `define SCR1_MTVEC_MODE_EN          // enable writable MTVEC.mode field to allow vectored irq mode, otherwise only direct mode is possible
-// `define SCR1_FAST_MUL               // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
+//  `define SCR1_FAST_MUL               // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
 //`define SCR1_MPRF_RST_EN - yosys fix, two dimensional array init not allowed
   `define SCR1_MCOUNTEN_EN            // enable custom MCOUNTEN CSR for counter control
 //`define SCR1_DBG_EN                 // enable Debug Subsystem (TAPC, DM, SCU, HDU)

diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
index 393a7af..f839edd 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv

@@ -377,17 +377,22 @@
         .rd_data    (resp_fifo_dout          )
       );
 
-
-
 assign resp_fifo_rd = !resp_fifo_empty;
-
-assign dmem_rdata = (resp_fifo_rd) ? scr1_conv_wb2mem_rdata(resp_fifo_dout.hwidth, resp_fifo_dout.haddr, resp_fifo_dout.hrdata) : 'h0;
-
-assign dmem_resp = (resp_fifo_rd)
-                    ? (resp_fifo_dout.hresp == 1'b1)
-                        ? SCR1_MEM_RESP_RDY_OK
-                        : SCR1_MEM_RESP_RDY_ER
-                    : SCR1_MEM_RESP_NOTRDY ;
+  
+// Added FF to improve timing
+always_ff @(posedge core_clk, negedge core_rst_n) begin
+   if(core_rst_n == 0) begin
+      dmem_rdata <= '0;
+      dmem_resp <= '0;
+   end else begin
+      dmem_rdata <= (resp_fifo_rd) ? scr1_conv_wb2mem_rdata(resp_fifo_dout.hwidth, resp_fifo_dout.haddr, resp_fifo_dout.hrdata) : 'h0;
+      dmem_resp  <= (resp_fifo_rd)
+                          ? (resp_fifo_dout.hresp == 1'b1)
+                              ? SCR1_MEM_RESP_RDY_OK
+                              : SCR1_MEM_RESP_RDY_ER
+                          : SCR1_MEM_RESP_NOTRDY ;
+   end
+end
 
 
 

diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
index 7750789..ae26909 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv

@@ -17,7 +17,11 @@
 // //////////////////////////////////////////////////////////////////////////
 /// @file       <scr1_timer.sv>
 /// @brief      Memory-mapped Timer
-///
+///    Version 1.0 - 18 - July 2021 - Dinesh A Project: yifive
+///           1.To break the timing path, input and output path are registered
+///           2.Spilt the 64 bit adder into two 32 bit added with taking care of
+///             overflow
+////////////////////////////////////////////////////////////////////////////////
 
 `include "scr1_arch_description.svh"
 `include "scr1_memif.svh"
@@ -119,7 +123,8 @@
 always_comb begin
     mtime_new   = mtime_reg;
     if (time_posedge) begin
-        mtime_new   = mtime_reg + 1'b1;
+        mtime_new[31:0]    = mtime_reg[31:0] + 1'b1;
+        mtime_new[63:32]   = (&mtime_reg[31:0]) ? (mtime_new[63:32] + 1'b1) : mtime_new[63:32];
     end
     if (mtimelo_up) begin
         mtime_new[31:0]     = dmem_wdata;
@@ -225,21 +230,32 @@
 //-------------------------------------------------------------------------------
 // Memory interface
 //-------------------------------------------------------------------------------
-assign dmem_req_valid   =   (dmem_width == SCR1_MEM_WIDTH_WORD) & (~|dmem_addr[1:0]) &
-                            (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:2] <= SCR1_TIMER_MTIMECMPHI[SCR1_TIMER_ADDR_WIDTH-1:2]);
-
-assign dmem_req_ack     = 1'b1;
+logic                           dmem_cmd_ff;
+logic [SCR1_TIMER_ADDR_WIDTH-1:0]   dmem_addr_ff;
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+       dmem_req_valid <= '0;
+       dmem_req_ack  <= '0;
+       dmem_cmd_ff  <= '0;
+       dmem_addr_ff <= '0;
+    end else begin
+       dmem_req_valid <=  (dmem_req) && (dmem_req_ack == 0) &&  (dmem_width == SCR1_MEM_WIDTH_WORD) & (~|dmem_addr[1:0]) &
+                          (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:2] <= SCR1_TIMER_MTIMECMPHI[SCR1_TIMER_ADDR_WIDTH-1:2]);
+       dmem_req_ack   <= dmem_req & (dmem_req_ack ==0);
+       dmem_cmd_ff    <= dmem_cmd;
+       dmem_addr_ff   <= dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0];
+    end
+end
 
 always_ff @(negedge rst_n, posedge clk) begin
     if (~rst_n) begin
         dmem_resp   <= SCR1_MEM_RESP_NOTRDY;
         dmem_rdata  <= '0;
     end else begin
-        if (dmem_req) begin
-            if (dmem_req_valid) begin
+        if (dmem_req_valid) begin
                 dmem_resp   <= SCR1_MEM_RESP_RDY_OK;
-                if (dmem_cmd == SCR1_MEM_CMD_RD) begin
-                    case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
+                if (dmem_cmd_ff == SCR1_MEM_CMD_RD) begin
+                    case (dmem_addr_ff)
                         SCR1_TIMER_CONTROL      : dmem_rdata    <= `SCR1_DMEM_DWIDTH'({timer_clksrc_rtc, timer_en});
                         SCR1_TIMER_DIVIDER      : dmem_rdata    <= `SCR1_DMEM_DWIDTH'(timer_div);
                         SCR1_TIMER_MTIMELO      : dmem_rdata    <= mtime_reg[31:0];
@@ -249,9 +265,6 @@
                         default                 : begin end
                     endcase
                 end
-            end else begin
-                dmem_resp   <= SCR1_MEM_RESP_RDY_ER;
-            end
         end else begin
             dmem_resp   <= SCR1_MEM_RESP_NOTRDY;
             dmem_rdata  <= '0;
@@ -266,8 +279,8 @@
     mtimehi_up      = 1'b0;
     mtimecmplo_up   = 1'b0;
     mtimecmphi_up   = 1'b0;
-    if (dmem_req & dmem_req_valid & (dmem_cmd == SCR1_MEM_CMD_WR)) begin
-        case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
+    if (dmem_req_valid & (dmem_cmd_ff == SCR1_MEM_CMD_WR)) begin
+        case (dmem_addr_ff)
             SCR1_TIMER_CONTROL      : control_up    = 1'b1;
             SCR1_TIMER_DIVIDER      : divider_up    = 1'b1;
             SCR1_TIMER_MTIMELO      : mtimelo_up    = 1'b1;

diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index bf6affc..8ddd341 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv

@@ -237,72 +237,87 @@
 
 logic                                               timer_irq;
 logic [63:0]                                        timer_val;
+logic [48:0]                                        core_debug;
 
-
-//---------------------------------------------------------------------------------
-// To avoid core level power hook up, we have brought this signal inside, to
-// avoid any cell at digital core level
-// --------------------------------------------------------------------------------
-assign test_mode = 1'b0;
-assign test_rst_n = 1'b0;
-
-logic [48:0] core_debug;
-assign riscv_debug = {core_imem_req,core_imem_req,core_imem_cmd,core_imem_resp[1:0],
-	              core_dmem_req_ack,core_dmem_req,core_dmem_cmd,core_dmem_resp[1:0],
-		      wb_imem_req,wb_imem_req,wb_imem_cmd,wb_imem_resp[1:0], core_debug };
 //-------------------------------------------------------------------------------
-// Reset logic
+// SCR1 Intf instance
 //-------------------------------------------------------------------------------
-// Power-Up Reset synchronizer
-scr1_reset_sync_cell #(
-    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_pwrup_rstn_reset_sync (
-    .rst_n          (pwrup_rst_n     ),
-    .clk            (core_clk        ),
-    .test_rst_n     (test_rst_n      ),
-    .test_mode      (test_mode       ),
-    .rst_n_in       (1'b1            ),
-    .rst_n_out      (pwrup_rst_n_sync)
-);
-
-// Regular Reset synchronizer
-scr1_reset_sync_cell #(
-    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_rstn_reset_sync (
-    .rst_n          (pwrup_rst_n     ),
-    .clk            (core_clk        ),
-    .test_rst_n     (test_rst_n      ),
-    .test_mode      (test_mode       ),
-    .rst_n_in       (rst_n           ),
-    .rst_n_out      (rst_n_sync      )
-);
-
-// CPU Reset synchronizer
-scr1_reset_sync_cell #(
-    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_cpu_rstn_reset_sync (
-    .rst_n          (pwrup_rst_n     ),
-    .clk            (core_clk        ),
-    .test_rst_n     (test_rst_n      ),
-    .test_mode      (test_mode       ),
-    .rst_n_in       (cpu_rst_n       ),
-    .rst_n_out      (cpu_rst_n_sync  )
-);
+scr1_intf u_intf (
+    // Control
+    .pwrup_rst_n                        (pwrup_rst_n),        // Power-Up Reset
+    .rst_n                              (rst_n),              // Regular Reset signal
+    .cpu_rst_n                          (cpu_rst_n),          // CPU Reset (Core Reset)
+    .core_clk                           (core_clk),           // Core clock
+    .rtc_clk                            (rtc_clk),            // Real-time clock
+    .riscv_debug                        (riscv_debug),
 
 `ifdef SCR1_DBG_EN
-// TAPC Reset
-scr1_reset_and2_cell i_tapc_rstn_and2_cell (
-    .rst_n_in       ({trst_n, pwrup_rst_n}),
-    .test_rst_n     (test_rst_n      ),
-    .test_mode      (test_mode       ),
-    .rst_n_out      (tapc_trst_n     )
-);
+    // -- JTAG I/F
+    .trst_n                             (trst_n),
 `endif // SCR1_DBG_EN
 
+    .wb_rst_n                           (wb_rst_n),           // Wish bone reset
+    .wb_clk                             (wb_clk),             // wish bone clock
+
+    // Instruction Memory Interface
+    .wbd_imem_stb_o                     (wbd_imem_stb_o),     // strobe/request
+    .wbd_imem_adr_o                     (wbd_imem_adr_o),     // address
+    .wbd_imem_we_o                      (wbd_imem_we_o),      // write
+    .wbd_imem_dat_o                     (wbd_imem_dat_o),     // data output
+    .wbd_imem_sel_o                     (wbd_imem_sel_o),     // byte enable
+    .wbd_imem_dat_i                     (wbd_imem_dat_i),     // data input
+    .wbd_imem_ack_i                     (wbd_imem_ack_i),     // acknowlegement
+    .wbd_imem_err_i                     (wbd_imem_err_i),     // error
+
+    // Data Memory Interface
+    .wbd_dmem_stb_o                     (wbd_dmem_stb_o),     // strobe/request
+    .wbd_dmem_adr_o                     (wbd_dmem_adr_o),     // address
+    .wbd_dmem_we_o                      (wbd_dmem_we_o),      // write
+    .wbd_dmem_dat_o                     (wbd_dmem_dat_o),     // data output
+    .wbd_dmem_sel_o                     (wbd_dmem_sel_o),     // byte enable
+    .wbd_dmem_dat_i                     (wbd_dmem_dat_i),     // data input
+    .wbd_dmem_ack_i                     (wbd_dmem_ack_i),     // acknowlegement
+    .wbd_dmem_err_i                     (wbd_dmem_err_i),     // error
+
+    // Common
+    .pwrup_rst_n_sync                   (pwrup_rst_n_sync),   // Power-Up reset
+    .rst_n_sync                         (rst_n_sync),         // Regular reset
+    .cpu_rst_n_sync                     (cpu_rst_n_sync),     // CPU reset
+    .test_mode                          (test_mode),          // DFT Test Mode
+    .test_rst_n                         (test_rst_n),         // DFT Test Reset
+    .core_rst_n_local                   (core_rst_n_local),   // Core reset
+    .core_debug                         (core_debug  ),
+`ifdef SCR1_DBG_EN
+    // Debug Interface
+    .tapc_trst_n                        (tapc_trst_n),        // Test Reset (TRSTn)
+`endif
+    // Memory-mapped external timer
+    .timer_val                          (timer_val),          // Machine timer value
+    // Instruction Memory Interface
+    .core_imem_req_ack                  (core_imem_req_ack),  // IMEM request acknowledge
+    .core_imem_req                      (core_imem_req),      // IMEM request
+    .core_imem_cmd                      (core_imem_cmd),      // IMEM command
+    .core_imem_addr                     (core_imem_addr),     // IMEM address
+    .core_imem_rdata                    (core_imem_rdata),    // IMEM read data
+    .core_imem_resp                     (core_imem_resp),     // IMEM response
+
+    // Data Memory Interface
+    .core_dmem_req_ack                  (core_dmem_req_ack),  // DMEM request acknowledge
+    .core_dmem_req                      (core_dmem_req),      // DMEM request
+    .core_dmem_cmd                      (core_dmem_cmd),      // DMEM command
+    .core_dmem_width                    (core_dmem_width),    // DMEM data width
+    .core_dmem_addr                     (core_dmem_addr),     // DMEM address
+    .core_dmem_wdata                    (core_dmem_wdata),    // DMEM write data
+    .core_dmem_rdata                    (core_dmem_rdata),    // DMEM read data
+    .core_dmem_resp                     (core_dmem_resp)      // DMEM response
+
+);
+
+
 //-------------------------------------------------------------------------------
 // SCR1 core instance
 //-------------------------------------------------------------------------------
-scr1_core_top i_core_top (
+scr1_core_top u_core_top (
     // Common
     .pwrup_rst_n                (pwrup_rst_n_sync ),
     .rst_n                      (rst_n_sync       ),
@@ -366,231 +381,6 @@
 );
 
 
-`ifdef SCR1_TCM_EN
-//-------------------------------------------------------------------------------
-// TCM instance
-//-------------------------------------------------------------------------------
-scr1_tcm #(
-    .SCR1_TCM_SIZE  (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
-) i_tcm (
-    .clk            (core_clk        ),
-    .rst_n          (core_rst_n_local),
-
-    // Instruction interface to TCM
-    .imem_req_ack   (tcm_imem_req_ack),
-    .imem_req       (tcm_imem_req    ),
-    .imem_addr      (tcm_imem_addr   ),
-    .imem_rdata     (tcm_imem_rdata  ),
-    .imem_resp      (tcm_imem_resp   ),
-
-    // Data interface to TCM
-    .dmem_req_ack   (tcm_dmem_req_ack),
-    .dmem_req       (tcm_dmem_req    ),
-    .dmem_cmd       (tcm_dmem_cmd    ),
-    .dmem_width     (tcm_dmem_width  ),
-    .dmem_addr      (tcm_dmem_addr   ),
-    .dmem_wdata     (tcm_dmem_wdata  ),
-    .dmem_rdata     (tcm_dmem_rdata  ),
-    .dmem_resp      (tcm_dmem_resp   )
-);
-`endif // SCR1_TCM_EN
-
-
-//-------------------------------------------------------------------------------
-// Memory-mapped timer instance
-//-------------------------------------------------------------------------------
-scr1_timer i_timer (
-    // Common
-    .rst_n          (core_rst_n_local  ),
-    .clk            (core_clk          ),
-    .rtc_clk        (rtc_clk           ),
-
-    // Memory interface
-    .dmem_req       (timer_dmem_req    ),
-    .dmem_cmd       (timer_dmem_cmd    ),
-    .dmem_width     (timer_dmem_width  ),
-    .dmem_addr      (timer_dmem_addr   ),
-    .dmem_wdata     (timer_dmem_wdata  ),
-    .dmem_req_ack   (timer_dmem_req_ack),
-    .dmem_rdata     (timer_dmem_rdata  ),
-    .dmem_resp      (timer_dmem_resp   ),
-
-    // Timer interface
-    .timer_val      (timer_val         ),
-    .timer_irq      (timer_irq         )
-);
-
-
-`ifdef SCR1_IMEM_ROUTER_EN
-//-------------------------------------------------------------------------------
-// Instruction memory router
-//-------------------------------------------------------------------------------
-scr1_imem_router #(
- `ifdef SCR1_TCM_EN
-    .SCR1_ADDR_MASK     (SCR1_TCM_ADDR_MASK),
-    .SCR1_ADDR_PATTERN  (SCR1_TCM_ADDR_PATTERN)
- `endif // SCR1_TCM_EN
-) i_imem_router (
-    .rst_n          (core_rst_n_local ),
-    .clk            (core_clk         ),
-    // Interface to core
-    .imem_req_ack   (core_imem_req_ack),
-    .imem_req       (core_imem_req    ),
-    .imem_cmd       (core_imem_cmd    ),
-    .imem_addr      (core_imem_addr   ),
-    .imem_rdata     (core_imem_rdata  ),
-    .imem_resp      (core_imem_resp   ),
-    // Interface to WB bridge
-    .port0_req_ack  (wb_imem_req_ack ),
-    .port0_req      (wb_imem_req     ),
-    .port0_cmd      (wb_imem_cmd     ),
-    .port0_addr     (wb_imem_addr    ),
-    .port0_rdata    (wb_imem_rdata   ),
-    .port0_resp     (wb_imem_resp    ),
- `ifdef SCR1_TCM_EN
-    // Interface to TCM
-    .port1_req_ack  (tcm_imem_req_ack ),
-    .port1_req      (tcm_imem_req     ),
-    .port1_cmd      (tcm_imem_cmd     ),
-    .port1_addr     (tcm_imem_addr    ),
-    .port1_rdata    (tcm_imem_rdata   ),
-    .port1_resp     (tcm_imem_resp    )
- `endif // SCR1_TCM_EN
-);
-
-`else // SCR1_IMEM_ROUTER_EN
-
-assign wb_imem_req         = core_imem_req;
-assign wb_imem_cmd         = core_imem_cmd;
-assign wb_imem_addr        = core_imem_addr;
-assign core_imem_req_ack    = wb_imem_req_ack;
-assign core_imem_resp       = wb_imem_resp;
-assign core_imem_rdata      = wb_imem_rdata;
-
-`endif // SCR1_IMEM_ROUTER_EN
-
-//-------------------------------------------------------------------------------
-// Data memory router
-//-------------------------------------------------------------------------------
-scr1_dmem_router #(
-
-`ifdef SCR1_TCM_EN
-    .SCR1_PORT1_ADDR_MASK       (SCR1_TCM_ADDR_MASK),
-    .SCR1_PORT1_ADDR_PATTERN    (SCR1_TCM_ADDR_PATTERN),
-`else // SCR1_TCM_EN
-    .SCR1_PORT1_ADDR_MASK       (32'h00000000),
-    .SCR1_PORT1_ADDR_PATTERN    (32'hFFFFFFFF),
-`endif // SCR1_TCM_EN
-
-    .SCR1_PORT2_ADDR_MASK       (SCR1_TIMER_ADDR_MASK),
-    .SCR1_PORT2_ADDR_PATTERN    (SCR1_TIMER_ADDR_PATTERN)
-
-) i_dmem_router (
-    .rst_n          (core_rst_n_local    ),
-    .clk            (core_clk            ),
-    // Interface to core
-    .dmem_req_ack   (core_dmem_req_ack   ),
-    .dmem_req       (core_dmem_req       ),
-    .dmem_cmd       (core_dmem_cmd       ),
-    .dmem_width     (core_dmem_width     ),
-    .dmem_addr      (core_dmem_addr      ),
-    .dmem_wdata     (core_dmem_wdata     ),
-    .dmem_rdata     (core_dmem_rdata     ),
-    .dmem_resp      (core_dmem_resp      ),
-`ifdef SCR1_TCM_EN
-    // Interface to TCM
-    .port1_req_ack  (tcm_dmem_req_ack    ),
-    .port1_req      (tcm_dmem_req        ),
-    .port1_cmd      (tcm_dmem_cmd        ),
-    .port1_width    (tcm_dmem_width      ),
-    .port1_addr     (tcm_dmem_addr       ),
-    .port1_wdata    (tcm_dmem_wdata      ),
-    .port1_rdata    (tcm_dmem_rdata      ),
-    .port1_resp     (tcm_dmem_resp       ),
-`else // SCR1_TCM_EN
-    .port1_req_ack  (1'b0),
-    .port1_req      (                    ),
-    .port1_cmd      (                    ),
-    .port1_width    (                    ),
-    .port1_addr     (                    ),
-    .port1_wdata    (                    ),
-    .port1_rdata    (32'h0               ),
-    .port1_resp     (SCR1_MEM_RESP_RDY_ER),
-`endif // SCR1_TCM_EN
-    // Interface to memory-mapped timer
-    .port2_req_ack  (timer_dmem_req_ack  ),
-    .port2_req      (timer_dmem_req      ),
-    .port2_cmd      (timer_dmem_cmd      ),
-    .port2_width    (timer_dmem_width    ),
-    .port2_addr     (timer_dmem_addr     ),
-    .port2_wdata    (timer_dmem_wdata    ),
-    .port2_rdata    (timer_dmem_rdata    ),
-    .port2_resp     (timer_dmem_resp     ),
-    // Interface to WB bridge
-    .port0_req_ack  (wb_dmem_req_ack    ),
-    .port0_req      (wb_dmem_req        ),
-    .port0_cmd      (wb_dmem_cmd        ),
-    .port0_width    (wb_dmem_width      ),
-    .port0_addr     (wb_dmem_addr       ),
-    .port0_wdata    (wb_dmem_wdata      ),
-    .port0_rdata    (wb_dmem_rdata      ),
-    .port0_resp     (wb_dmem_resp       )
-);
-
-
-//-------------------------------------------------------------------------------
-// Instruction memory WB bridge
-//-------------------------------------------------------------------------------
-scr1_imem_wb i_imem_wb (
-    .core_rst_n     (core_rst_n_local   ),
-    .core_clk       (core_clk           ),
-    // Interface to imem router
-    .imem_req_ack   (wb_imem_req_ack   ),
-    .imem_req       (wb_imem_req       ),
-    .imem_addr      (wb_imem_addr      ),
-    .imem_rdata     (wb_imem_rdata     ),
-    .imem_resp      (wb_imem_resp      ),
-    // WB interface
-    .wb_rst_n       (wb_rst_n          ),
-    .wb_clk         (wb_clk            ),
-    .wbd_stb_o      (wbd_imem_stb_o    ), 
-    .wbd_adr_o      (wbd_imem_adr_o    ), 
-    .wbd_we_o       (wbd_imem_we_o     ),  
-    .wbd_dat_o      (wbd_imem_dat_o    ), 
-    .wbd_sel_o      (wbd_imem_sel_o    ), 
-    .wbd_dat_i      (wbd_imem_dat_i    ), 
-    .wbd_ack_i      (wbd_imem_ack_i    ), 
-    .wbd_err_i      (wbd_imem_err_i    )
-);
-
-
-//-------------------------------------------------------------------------------
-// Data memory WB bridge
-//-------------------------------------------------------------------------------
-scr1_dmem_wb i_dmem_wb (
-    .core_rst_n     (core_rst_n_local   ),
-    .core_clk       (core_clk           ),
-    // Interface to dmem router
-    .dmem_req_ack   (wb_dmem_req_ack   ),
-    .dmem_req       (wb_dmem_req       ),
-    .dmem_cmd       (wb_dmem_cmd       ),
-    .dmem_width     (wb_dmem_width     ),
-    .dmem_addr      (wb_dmem_addr      ),
-    .dmem_wdata     (wb_dmem_wdata     ),
-    .dmem_rdata     (wb_dmem_rdata     ),
-    .dmem_resp      (wb_dmem_resp      ),
-    // WB interface
-    .wb_rst_n       (wb_rst_n          ),
-    .wb_clk         (wb_clk            ),
-    .wbd_stb_o      (wbd_dmem_stb_o    ), 
-    .wbd_adr_o      (wbd_dmem_adr_o    ), 
-    .wbd_we_o       (wbd_dmem_we_o     ),  
-    .wbd_dat_o      (wbd_dmem_dat_o    ), 
-    .wbd_sel_o      (wbd_dmem_sel_o    ), 
-    .wbd_dat_i      (wbd_dmem_dat_i    ), 
-    .wbd_ack_i      (wbd_dmem_ack_i    ), 
-    .wbd_err_i      (wbd_dmem_err_i    )
-);
 
 endmodule : scr1_top_wb
 

diff --git a/verilog/rtl/syntacore/scr1/src/wb_top.files b/verilog/rtl/syntacore/scr1/src/wb_top.files
index 25f9f8f..1d67b0c 100644
--- a/verilog/rtl/syntacore/scr1/src/wb_top.files
+++ b/verilog/rtl/syntacore/scr1/src/wb_top.files

@@ -22,4 +22,5 @@
 top/scr1_dmem_wb.sv
 top/scr1_imem_wb.sv
 top/scr1_top_wb.sv
+top/scr1_intf.sv
 ../../../lib/sync_fifo.sv

diff --git a/verilog/rtl/syntacore/scr1/synth/synth.tcl b/verilog/rtl/syntacore/scr1/synth/synth.tcl
index 4375c58..3331be6 100755
--- a/verilog/rtl/syntacore/scr1/synth/synth.tcl
+++ b/verilog/rtl/syntacore/scr1/synth/synth.tcl

@@ -44,6 +44,8 @@
 	../src/core/pipeline/scr1_pipe_mprf.sv  \
 	../src/core/pipeline/scr1_pipe_csr.sv  \
 	../src/core/pipeline/scr1_pipe_ialu.sv  \
+	../src/core/pipeline/scr1_pipe_mul.sv  \
+	../src/core/pipeline/scr1_pipe_div.sv  \
 	../src/core/pipeline/scr1_pipe_lsu.sv  \
 	../src/core/pipeline/scr1_pipe_hdu.sv  \
 	../src/core/pipeline/scr1_pipe_tdu.sv  \

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 29925ab..ea393bf 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v

@@ -95,6 +95,8 @@
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
+     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
      `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
      `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
@@ -113,6 +115,7 @@
      `include "syntacore/scr1/src/top/scr1_timer.sv"
      `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
      `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+     `include "syntacore/scr1/src/top/scr1_intf.sv"
      `include "syntacore/scr1/src/top/scr1_top_wb.sv"
      `include "lib/sync_fifo.sv"
commit	a999a4e4c59662ad04dfa2997b8033ff63eb7ce5	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Sat Jul 24 19:56:01 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Sat Jul 24 19:56:01 2021 +0530
tree	7d3f1371dbf8b469a136d2cc5dd601f2bde7afcb
parent	d454c617a6466def28fd346aa5fba73ef3c48ac8 [diff]