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foss-eda-tools/third_party/shuttle/sky130/mpw-006/slot-006/9e72593103dbe37327495fc2cea6009f42a200a0^!/.
commit
9e72593103dbe37327495fc2cea6009f42a200a0
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Mon Sep 05 14:56:53 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Mon Sep 05 14:56:53 2022 +0530
tree
6ca4aea69be0dfba5970fcc02c858f67ddca7c09
parent
67e3f06cb651c503efc286695c2072fb762ccd70 [diff]
gds based lvs check for all macro

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index a04b0ca..90542f5 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 66bb6bb..efc5da6 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ

diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index f715632..4cdf315 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl

@@ -99,6 +99,10 @@
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "1"

diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index b317ba7..86a397e 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl

@@ -124,9 +124,9 @@
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
 
-#set ::env(GLB_RT_ADJUSTMENT) {0.25}
-set ::env(GRT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0}
 set ::env(CELL_PAD) {8}
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index f69b2c4..61bbbff 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -109,6 +109,10 @@
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"

diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index de21996..51f3ba1 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -107,14 +107,9 @@
 set ::env(GRT_ADJUSTMENT) 0.1
 set ::env(DPL_CELL_PADDING) 1
 
-#set ::env(GLB_RT_ADJUSTMENT) 0
-#set ::env(GLB_RT_L2_ADJUSTMENT) 0.21
-#set ::env(GLB_RT_L3_ADJUSTMENT) 0.21
-#set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
-#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-#set ::env(GLB_RT_ALLOW_CONGESTION) 0
-#set ::env(GLB_RT_OVERFLOW_ITERS) 200
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
 
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}

diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 3c4ead4..b1d2727 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl

@@ -82,11 +82,16 @@
 ## Routing
 set ::env(GRT_ADJUSTMENT) 0.2
 
+set ::env(PL_TIME_DRIVEN) "1"
+
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
@@ -96,6 +101,7 @@
 #Need to cross-check why global timing opimization creating setup vio with hugh hold fix
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
 
+#PDN
 set ::env(FP_PDN_VPITCH) 100
 set ::env(FP_PDN_HPITCH) 100
 set ::env(FP_PDN_VWIDTH) 6.2

diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
index 6745049..e4cba2f 100644
--- a/openlane/ycr_iconnect/config.tcl
+++ b/openlane/ycr_iconnect/config.tcl

@@ -63,32 +63,21 @@
 set ::env(DIE_AREA) "0 0 380 1100"
 
 set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) 2
-set ::env(GRT_ADJUSTMENT) {0.2}
+#set ::env(CELL_PAD) 2
+#set ::env(GRT_ADJUSTMENT) {0.2}
 
 #set ::env(GLB_RT_ADJUSTMENT) {0.2}
 
 #set ::env(PL_ROUTABILITY_DRIVEN) "1"
 set ::env(PL_TIME_DRIVEN) "1"
 
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
-set ::env(GLB_OPTIMIZE_MIRRORING) {1}
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
-
-### PDN
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 6.2
-set ::env(FP_PDN_HWIDTH) 6.2
-
 #set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
@@ -96,3 +85,7 @@
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2

diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 8ef2d04..706dc3d 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl

@@ -77,6 +77,8 @@
 #set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 3
 
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"

diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/ycr_iconnect/OPENLANE_VERSION b/signoff/ycr_iconnect/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/ycr_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr_iconnect/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/ycr_iconnect/PDK_SOURCES b/signoff/ycr_iconnect/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/ycr_iconnect/PDK_SOURCES
+++ b/signoff/ycr_iconnect/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index d5588cd..b5bf449 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818

diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index e8e14ea..f9d0f46 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES

@@ -1 +1 @@
-open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b

diff --git a/spef/qspim_top.spef.gz b/spef/qspim_top.spef.gz
index 97756af..c9deb40 100644
--- a/spef/qspim_top.spef.gz
+++ b/spef/qspim_top.spef.gz
Binary files differ

diff --git a/spef/uart_i2c_usb_spi_top.spef.gz b/spef/uart_i2c_usb_spi_top.spef.gz
index 064acf0..a570171 100644
--- a/spef/uart_i2c_usb_spi_top.spef.gz
+++ b/spef/uart_i2c_usb_spi_top.spef.gz
Binary files differ

diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz
index 01c47d6..5cd0478 100644
--- a/spef/user_project_wrapper.spef.gz
+++ b/spef/user_project_wrapper.spef.gz
Binary files differ

diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz
index f95b554..5c0042f 100644
--- a/spef/wb_host.spef.gz
+++ b/spef/wb_host.spef.gz
Binary files differ

diff --git a/spef/wb_interconnect.spef.gz b/spef/wb_interconnect.spef.gz
index 1b549ba..e6d692f 100644
--- a/spef/wb_interconnect.spef.gz
+++ b/spef/wb_interconnect.spef.gz
Binary files differ

diff --git a/spef/ycr_core_top.spef.gz b/spef/ycr_core_top.spef.gz
index 28a1c21..7e91d10 100644
--- a/spef/ycr_core_top.spef.gz
+++ b/spef/ycr_core_top.spef.gz
Binary files differ

diff --git a/spef/ycr_iconnect.spef.gz b/spef/ycr_iconnect.spef.gz
index 8eda882..99f5a9e 100644
--- a/spef/ycr_iconnect.spef.gz
+++ b/spef/ycr_iconnect.spef.gz
Binary files differ

diff --git a/spef/ycr_intf.spef.gz b/spef/ycr_intf.spef.gz
index 6bd2b86..a4ed44f 100644
--- a/spef/ycr_intf.spef.gz
+++ b/spef/ycr_intf.spef.gz
Binary files differ

diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index ab32382..e4a1421 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl

@@ -186,4 +186,92 @@
 	   echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
            report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> wb.min.rpt
         }
-        
+       
+	echo "SRAM Interface Timing.................." > sram.min.rpt
+	echo "SRAM Interface Timing.................." > sram.min.summary.rpt
+
+    ### Caravel SRAM Path ######################################
+    #set sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/din0[*]}]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr1[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb1[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/web0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/wmask0[*]}]]
+ 
+    #set sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout0[*]}]
+	#set sram_oport [concat $sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout1[*]}]]
+    ### Caravel SRAM Path ######################################
+   
+    #TCM SRAM 
+    set tsram_iport [get_pins {mprj/u_tsram0_2kb/din0[*]}]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr0[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr1[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb0[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb1[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/web0[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/wmask0[*]}]]
+
+    set tsram_oport [get_pins {mprj/u_tsram0_2kb/dout0[*]}]
+	set tsram_oport [concat $tsram_oport [get_pins {mprj/u_tsram0_2kb/dout1[*]}]]
+
+	foreach pin $tsram_iport {
+	   echo "SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $tsram_oport {
+	   echo "SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+    #ICACHE SRAM 
+    set isram_iport [                     get_pins {mprj/u_icahce_2kb/din0[*]}]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr0[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr1[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb0[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb1[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/web0[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/wmask0[*]}]]
+
+    set isram_oport [                     get_pins {mprj/u_icache_2kb/dout0[*]}]
+	set isram_oport [concat $isram_oport [get_pins {mprj/u_icache_2kb/dout1[*]}]]
+
+	foreach pin $isram_iport {
+	   echo "ICAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $isram_oport {
+	   echo "ICAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+    #DCACHE SRAM 
+    set dsram_iport [                     get_pins {mprj/u_dcahce_2kb/din0[*]}]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr0[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr1[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb0[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb1[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/web0[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/wmask0[*]}]]
+
+    set dsram_oport [                     get_pins {mprj/u_dcache_2kb/dout0[*]}]
+	set dsram_oport [concat $isram_oport [get_pins {mprj/u_dcache_2kb/dout1[*]}]]
+
+	foreach pin $dsram_iport {
+	   echo "DCAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $dsram_oport {
+	   echo "DCAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+

diff --git a/verilog/gl/qspim_top.v.gz b/verilog/gl/qspim_top.v.gz
index b70a49c..5a16f39 100644
--- a/verilog/gl/qspim_top.v.gz
+++ b/verilog/gl/qspim_top.v.gz
Binary files differ

diff --git a/verilog/gl/uart_i2c_usb_spi_top.v.gz b/verilog/gl/uart_i2c_usb_spi_top.v.gz
index f070157..a2c6b5f 100644
--- a/verilog/gl/uart_i2c_usb_spi_top.v.gz
+++ b/verilog/gl/uart_i2c_usb_spi_top.v.gz
Binary files differ

diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 134f9fa..1090261 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ

diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz
index 44e6327..c014331 100644
--- a/verilog/gl/wb_host.v.gz
+++ b/verilog/gl/wb_host.v.gz
Binary files differ

diff --git a/verilog/gl/wb_interconnect.v.gz b/verilog/gl/wb_interconnect.v.gz
index 9b66c59..73c9b23 100644
--- a/verilog/gl/wb_interconnect.v.gz
+++ b/verilog/gl/wb_interconnect.v.gz
Binary files differ

diff --git a/verilog/gl/ycr_core_top.v.gz b/verilog/gl/ycr_core_top.v.gz
index 76a5ead..e95d74b 100644
--- a/verilog/gl/ycr_core_top.v.gz
+++ b/verilog/gl/ycr_core_top.v.gz
Binary files differ

diff --git a/verilog/gl/ycr_iconnect.v.gz b/verilog/gl/ycr_iconnect.v.gz
index 86ca85b..93d20dc 100644
--- a/verilog/gl/ycr_iconnect.v.gz
+++ b/verilog/gl/ycr_iconnect.v.gz
Binary files differ

diff --git a/verilog/gl/ycr_intf.v.gz b/verilog/gl/ycr_intf.v.gz
index 94c5fa9..7510c02 100644
--- a/verilog/gl/ycr_intf.v.gz
+++ b/verilog/gl/ycr_intf.v.gz
Binary files differ