pdn drc fix
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 3241211..20feabd 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -108,17 +108,18 @@
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
-set ::env(VDD_NETS) "vccd1"
-set ::env(GND_NETS) "vssd1"
-
-set ::env(VDD_PIN) "vccd1"
-set ::env(GND_PIN) "vssd1"
+set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
+set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
+#
+set ::env(VDD_PIN) "vccd1 vccd2 vdda1 vdda2"
+set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2"
set ::env(GLB_RT_OBS) "
li1 200 175 883.1 591.54,\
met1 200 175 883.1 591.54,\
met2 200 175 883.1 591.54,\
met3 200 175 883.1 591.54,\
+ met4 200 175 883.1 591.54,\
li1 200 1300 883.1 1716.54,\
met1 200 1300 883.1 1716.54,\
met2 200 1300 883.1 1716.54,\
@@ -180,7 +181,8 @@
set ::env(QUIT_ON_TR_DRC) "0"
-set ::env(FP_PDN_HPITCH) "100"
+set ::env(FP_PDN_HPITCH) "80"
set ::env(FP_PDN_VPITCH) "180"
+set ::env(FP_PDN_HSPACING) "6"
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 2298dac..b190986 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m34s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,532.38,15,0,0,0,0,0,0,-1,0,0,-1,-1,1472939,10679,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,9849.37,4.62,3.23,0.53,0.52,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,100,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h38m54s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,535.91,15,0,0,0,0,0,0,-1,0,0,-1,-1,1472837,10805,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.64,3.24,0.49,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,80,0.55,0.0,sky130_fd_sc_hd,4,0
