Clean GateSim and RTL Sim + Updated SPI Master
diff --git a/checks/erase_box_user_project_wrapper.gds.log b/checks/erase_box_user_project_wrapper.gds.log
new file mode 100644
index 0000000..f1b10a8
--- /dev/null
+++ b/checks/erase_box_user_project_wrapper.gds.log
@@ -0,0 +1,3298 @@
+/home/dinesha/workarea/opencore/git/yifive_r0/gds//user_project_wrapper.gds /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds user_project_wrapper
+
+Magic 8.3 revision 182 - Compiled on Fri Jun 25 23:58:13 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Using technology "sky130A", version 1.0.116-4-g522a373
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "scr1_top_wb".
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+ 85900 uses
+ 86000 uses
+ 86100 uses
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+ 86400 uses
+ 86500 uses
+ 86600 uses
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+ 86900 uses
+ 87000 uses
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+ 87500 uses
+ 87600 uses
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+ 87800 uses
+ 87900 uses
+ 88000 uses
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+ 88400 uses
+ 88500 uses
+ 88600 uses
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+ 88800 uses
+ 88900 uses
+ 89000 uses
+ 89100 uses
+ 89200 uses
+ 89300 uses
+ 89400 uses
+ 89500 uses
+ 89600 uses
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+ 89800 uses
+ 89900 uses
+ 90000 uses
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+ 90400 uses
+ 90500 uses
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+ 91000 uses
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+ 94000 uses
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+ 94400 uses
+ 94500 uses
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+ 94900 uses
+ 95000 uses
+ 95100 uses
+ 95200 uses
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+ 95400 uses
+ 95500 uses
+ 95600 uses
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+ 95900 uses
+ 96000 uses
+ 96100 uses
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+ 96600 uses
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+ 96800 uses
+ 96900 uses
+ 97000 uses
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+ 97500 uses
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+ 97700 uses
+ 97800 uses
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+ 98000 uses
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+ 98400 uses
+ 98500 uses
+ 98600 uses
+ 98700 uses
+ 98800 uses
+ 98900 uses
+ 99000 uses
+ 99100 uses
+ 99200 uses
+ 99300 uses
+ 99400 uses
+ 99500 uses
+ 99600 uses
+ 99700 uses
+ 99800 uses
+ 99900 uses
+ 100000 uses
+ 100100 uses
+ 100200 uses
+ 100300 uses
+ 100400 uses
+ 100500 uses
+ 100600 uses
+ 100700 uses
+ 100800 uses
+ 100900 uses
+ 101000 uses
+ 101100 uses
+ 101200 uses
+ 101300 uses
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+ 101500 uses
+ 101600 uses
+ 101700 uses
+ 101800 uses
+ 101900 uses
+ 102000 uses
+ 102100 uses
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+ 102300 uses
+ 102400 uses
+ 102500 uses
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+ 102700 uses
+ 102800 uses
+ 102900 uses
+ 103000 uses
+ 103100 uses
+ 103200 uses
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+ 103500 uses
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+ 103800 uses
+ 103900 uses
+ 104000 uses
+ 104100 uses
+ 104200 uses
+ 104300 uses
+ 104400 uses
+ 104500 uses
+ 104600 uses
+ 104700 uses
+ 104800 uses
+ 104900 uses
+ 105000 uses
+ 105100 uses
+ 105200 uses
+ 105300 uses
+ 105400 uses
+ 105500 uses
+ 105600 uses
+ 105700 uses
+ 105800 uses
+ 105900 uses
+ 106000 uses
+ 106100 uses
+ 106200 uses
+ 106300 uses
+ 106400 uses
+ 106500 uses
+ 106600 uses
+ 106700 uses
+ 106800 uses
+ 106900 uses
+ 107000 uses
+ 107100 uses
+ 107200 uses
+ 107300 uses
+ 107400 uses
+ 107500 uses
+ 107600 uses
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+ 107800 uses
+ 107900 uses
+ 108000 uses
+ 108100 uses
+ 108200 uses
+ 108300 uses
+ 108400 uses
+ 108500 uses
+ 108600 uses
+ 108700 uses
+ 108800 uses
+ 108900 uses
+ 109000 uses
+ 109100 uses
+ 109200 uses
+ 109300 uses
+ 109400 uses
+ 109500 uses
+ 109600 uses
+ 109700 uses
+ 109800 uses
+ 109900 uses
+ 110000 uses
+ 110100 uses
+ 110200 uses
+ 110300 uses
+ 110400 uses
+ 110500 uses
+ 110600 uses
+ 110700 uses
+ 110800 uses
+ 110900 uses
+ 111000 uses
+ 111100 uses
+ 111200 uses
+ 111300 uses
+ 111400 uses
+ 111500 uses
+ 111600 uses
+ 111700 uses
+ 111800 uses
+ 111900 uses
+ 112000 uses
+ 112100 uses
+ 112200 uses
+ 112300 uses
+ 112400 uses
+ 112500 uses
+ 112600 uses
+ 112700 uses
+ 112800 uses
+ 112900 uses
+ 113000 uses
+ 113100 uses
+ 113200 uses
+ 113300 uses
+ 113400 uses
+ 113500 uses
+ 113600 uses
+ 113700 uses
+ 113800 uses
+ 113900 uses
+ 114000 uses
+ 114100 uses
+ 114200 uses
+ 114300 uses
+ 114400 uses
+ 114500 uses
+ 114600 uses
+ 114700 uses
+ 114800 uses
+ 114900 uses
+ 115000 uses
+ 115100 uses
+ 115200 uses
+ 115300 uses
+ 115400 uses
+ 115500 uses
+ 115600 uses
+ 115700 uses
+ 115800 uses
+ 115900 uses
+ 116000 uses
+ 116100 uses
+ 116200 uses
+ 116300 uses
+ 116400 uses
+ 116500 uses
+ 116600 uses
+ 116700 uses
+ 116800 uses
+ 116900 uses
+ 117000 uses
+ 117100 uses
+ 117200 uses
+ 117300 uses
+ 117400 uses
+ 117500 uses
+ 117600 uses
+ 117700 uses
+ 117800 uses
+ 117900 uses
+ 118000 uses
+ 118100 uses
+ 118200 uses
+ 118300 uses
+ 118400 uses
+ 118500 uses
+ 118600 uses
+ 118700 uses
+ 118800 uses
+ 118900 uses
+ 119000 uses
+ 119100 uses
+ 119200 uses
+ 119300 uses
+ 119400 uses
+ 119500 uses
+ 119600 uses
+ 119700 uses
+ 119800 uses
+ 119900 uses
+ 120000 uses
+ 120100 uses
+ 120200 uses
+ 120300 uses
+ 120400 uses
+ 120500 uses
+ 120600 uses
+ 120700 uses
+ 120800 uses
+ 120900 uses
+ 121000 uses
+ 121100 uses
+ 121200 uses
+ 121300 uses
+ 121400 uses
+ 121500 uses
+ 121600 uses
+ 121700 uses
+ 121800 uses
+ 121900 uses
+ 122000 uses
+ 122100 uses
+ 122200 uses
+ 122300 uses
+ 122400 uses
+ 122500 uses
+ 122600 uses
+ 122700 uses
+ 122800 uses
+ 122900 uses
+ 123000 uses
+ 123100 uses
+ 123200 uses
+ 123300 uses
+ 123400 uses
+ 123500 uses
+ 123600 uses
+ 123700 uses
+ 123800 uses
+ 123900 uses
+ 124000 uses
+ 124100 uses
+ 124200 uses
+ 124300 uses
+ 124400 uses
+ 124500 uses
+ 124600 uses
+ 124700 uses
+ 124800 uses
+ 124900 uses
+ 125000 uses
+ 125100 uses
+ 125200 uses
+ 125300 uses
+ 125400 uses
+ 125500 uses
+ 125600 uses
+ 125700 uses
+ 125800 uses
+ 125900 uses
+ 126000 uses
+ 126100 uses
+ 126200 uses
+ 126300 uses
+ 126400 uses
+ 126500 uses
+ 126600 uses
+ 126700 uses
+ 126800 uses
+ 126900 uses
+ 127000 uses
+ 127100 uses
+ 127200 uses
+ 127300 uses
+ 127400 uses
+ 127500 uses
+ 127600 uses
+ 127700 uses
+ 127800 uses
+ 127900 uses
+ 128000 uses
+ 128100 uses
+ 128200 uses
+ 128300 uses
+ 128400 uses
+ 128500 uses
+ 128600 uses
+ 128700 uses
+ 128800 uses
+ 128900 uses
+ 129000 uses
+ 129100 uses
+ 129200 uses
+ 129300 uses
+ 129400 uses
+ 129500 uses
+ 129600 uses
+ 129700 uses
+ 129800 uses
+ 129900 uses
+ 130000 uses
+ 130100 uses
+ 130200 uses
+ 130300 uses
+ 130400 uses
+ 130500 uses
+ 130600 uses
+ 130700 uses
+ 130800 uses
+ 130900 uses
+ 131000 uses
+ 131100 uses
+ 131200 uses
+ 131300 uses
+ 131400 uses
+ 131500 uses
+ 131600 uses
+ 131700 uses
+ 131800 uses
+ 131900 uses
+ 132000 uses
+ 132100 uses
+ 132200 uses
+ 132300 uses
+ 132400 uses
+ 132500 uses
+ 132600 uses
+ 132700 uses
+ 132800 uses
+ 132900 uses
+ 133000 uses
+ 133100 uses
+ 133200 uses
+ 133300 uses
+ 133400 uses
+ 133500 uses
+ 133600 uses
+ 133700 uses
+ 133800 uses
+ 133900 uses
+ 134000 uses
+ 134100 uses
+ 134200 uses
+ 134300 uses
+ 134400 uses
+ 134500 uses
+ 134600 uses
+ 134700 uses
+ 134800 uses
+ 134900 uses
+ 135000 uses
+ 135100 uses
+ 135200 uses
+ 135300 uses
+ 135400 uses
+ 135500 uses
+ 135600 uses
+ 135700 uses
+ 135800 uses
+ 135900 uses
+ 136000 uses
+ 136100 uses
+ 136200 uses
+ 136300 uses
+ 136400 uses
+ 136500 uses
+ 136600 uses
+ 136700 uses
+ 136800 uses
+ 136900 uses
+ 137000 uses
+ 137100 uses
+ 137200 uses
+ 137300 uses
+ 137400 uses
+ 137500 uses
+ 137600 uses
+ 137700 uses
+ 137800 uses
+ 137900 uses
+ 138000 uses
+ 138100 uses
+ 138200 uses
+ 138300 uses
+ 138400 uses
+ 138500 uses
+ 138600 uses
+ 138700 uses
+ 138800 uses
+ 138900 uses
+ 139000 uses
+ 139100 uses
+ 139200 uses
+ 139300 uses
+ 139400 uses
+ 139500 uses
+ 139600 uses
+ 139700 uses
+ 139800 uses
+ 139900 uses
+ 140000 uses
+ 140100 uses
+ 140200 uses
+ 140300 uses
+ 140400 uses
+ 140500 uses
+ 140600 uses
+ 140700 uses
+ 140800 uses
+ 140900 uses
+ 141000 uses
+ 141100 uses
+ 141200 uses
+ 141300 uses
+ 141400 uses
+ 141500 uses
+ 141600 uses
+ 141700 uses
+ 141800 uses
+ 141900 uses
+ 142000 uses
+ 142100 uses
+ 142200 uses
+ 142300 uses
+ 142400 uses
+ 142500 uses
+ 142600 uses
+ 142700 uses
+ 142800 uses
+ 142900 uses
+ 143000 uses
+ 143100 uses
+ 143200 uses
+ 143300 uses
+ 143400 uses
+ 143500 uses
+ 143600 uses
+ 143700 uses
+ 143800 uses
+ 143900 uses
+ 144000 uses
+ 144100 uses
+ 144200 uses
+ 144300 uses
+ 144400 uses
+ 144500 uses
+ 144600 uses
+ 144700 uses
+ 144800 uses
+ 144900 uses
+ 145000 uses
+ 145100 uses
+ 145200 uses
+ 145300 uses
+ 145400 uses
+ 145500 uses
+ 145600 uses
+ 145700 uses
+ 145800 uses
+ 145900 uses
+ 146000 uses
+ 146100 uses
+ 146200 uses
+ 146300 uses
+ 146400 uses
+ 146500 uses
+ 146600 uses
+ 146700 uses
+ 146800 uses
+ 146900 uses
+ 147000 uses
+ 147100 uses
+ 147200 uses
+ 147300 uses
+ 147400 uses
+ 147500 uses
+ 147600 uses
+ 147700 uses
+ 147800 uses
+ 147900 uses
+ 148000 uses
+ 148100 uses
+ 148200 uses
+ 148300 uses
+ 148400 uses
+ 148500 uses
+ 148600 uses
+ 148700 uses
+ 148800 uses
+ 148900 uses
+ 149000 uses
+ 149100 uses
+ 149200 uses
+ 149300 uses
+ 149400 uses
+ 149500 uses
+ 149600 uses
+ 149700 uses
+ 149800 uses
+ 149900 uses
+ 150000 uses
+ 150100 uses
+ 150200 uses
+ 150300 uses
+ 150400 uses
+ 150500 uses
+ 150600 uses
+ 150700 uses
+ 150800 uses
+ 150900 uses
+ 151000 uses
+ 151100 uses
+ 151200 uses
+ 151300 uses
+ 151400 uses
+ 151500 uses
+ 151600 uses
+ 151700 uses
+ 151800 uses
+ 151900 uses
+ 152000 uses
+ 152100 uses
+ 152200 uses
+ 152300 uses
+ 152400 uses
+ 152500 uses
+ 152600 uses
+ 152700 uses
+ 152800 uses
+ 152900 uses
+ 153000 uses
+ 153100 uses
+ 153200 uses
+ 153300 uses
+ 153400 uses
+ 153500 uses
+ 153600 uses
+ 153700 uses
+ 153800 uses
+ 153900 uses
+ 154000 uses
+ 154100 uses
+ 154200 uses
+ 154300 uses
+ 154400 uses
+ 154500 uses
+ 154600 uses
+ 154700 uses
+ 154800 uses
+ 154900 uses
+ 155000 uses
+ 155100 uses
+ 155200 uses
+ 155300 uses
+ 155400 uses
+ 155500 uses
+ 155600 uses
+ 155700 uses
+ 155800 uses
+ 155900 uses
+ 156000 uses
+ 156100 uses
+ 156200 uses
+ 156300 uses
+ 156400 uses
+ 156500 uses
+ 156600 uses
+ 156700 uses
+ 156800 uses
+ 156900 uses
+ 157000 uses
+ 157100 uses
+ 157200 uses
+ 157300 uses
+ 157400 uses
+ 157500 uses
+ 157600 uses
+ 157700 uses
+ 157800 uses
+ 157900 uses
+ 158000 uses
+ 158100 uses
+ 158200 uses
+ 158300 uses
+ 158400 uses
+ 158500 uses
+ 158600 uses
+ 158700 uses
+ 158800 uses
+ 158900 uses
+ 159000 uses
+ 159100 uses
+ 159200 uses
+ 159300 uses
+ 159400 uses
+ 159500 uses
+ 159600 uses
+ 159700 uses
+ 159800 uses
+ 159900 uses
+ 160000 uses
+ 160100 uses
+ 160200 uses
+ 160300 uses
+ 160400 uses
+ 160500 uses
+ 160600 uses
+ 160700 uses
+ 160800 uses
+ 160900 uses
+ 161000 uses
+ 161100 uses
+ 161200 uses
+ 161300 uses
+ 161400 uses
+ 161500 uses
+ 161600 uses
+ 161700 uses
+ 161800 uses
+ 161900 uses
+ 162000 uses
+ 162100 uses
+ 162200 uses
+ 162300 uses
+ 162400 uses
+ 162500 uses
+ 162600 uses
+ 162700 uses
+ 162800 uses
+ 162900 uses
+ 163000 uses
+ 163100 uses
+ 163200 uses
+ 163300 uses
+ 163400 uses
+ 163500 uses
+ 163600 uses
+ 163700 uses
+ 163800 uses
+ 163900 uses
+ 164000 uses
+ 164100 uses
+ 164200 uses
+ 164300 uses
+ 164400 uses
+ 164500 uses
+ 164600 uses
+ 164700 uses
+ 164800 uses
+ 164900 uses
+ 165000 uses
+ 165100 uses
+ 165200 uses
+ 165300 uses
+ 165400 uses
+ 165500 uses
+ 165600 uses
+ 165700 uses
+ 165800 uses
+ 165900 uses
+ 166000 uses
+ 166100 uses
+ 166200 uses
+ 166300 uses
+ 166400 uses
+ 166500 uses
+ 166600 uses
+ 166700 uses
+ 166800 uses
+ 166900 uses
+ 167000 uses
+ 167100 uses
+ 167200 uses
+ 167300 uses
+ 167400 uses
+ 167500 uses
+ 167600 uses
+ 167700 uses
+ 167800 uses
+ 167900 uses
+ 168000 uses
+ 168100 uses
+ 168200 uses
+ 168300 uses
+ 168400 uses
+ 168500 uses
+ 168600 uses
+ 168700 uses
+ 168800 uses
+ 168900 uses
+ 169000 uses
+ 169100 uses
+ 169200 uses
+ 169300 uses
+ 169400 uses
+ 169500 uses
+ 169600 uses
+ 169700 uses
+ 169800 uses
+ 169900 uses
+ 170000 uses
+ 170100 uses
+ 170200 uses
+ 170300 uses
+ 170400 uses
+ 170500 uses
+ 170600 uses
+ 170700 uses
+ 170800 uses
+ 170900 uses
+ 171000 uses
+ 171100 uses
+ 171200 uses
+ 171300 uses
+ 171400 uses
+ 171500 uses
+ 171600 uses
+ 171700 uses
+ 171800 uses
+ 171900 uses
+ 172000 uses
+ 172100 uses
+ 172200 uses
+ 172300 uses
+ 172400 uses
+ 172500 uses
+ 172600 uses
+ 172700 uses
+ 172800 uses
+ 172900 uses
+ 173000 uses
+ 173100 uses
+ 173200 uses
+ 173300 uses
+ 173400 uses
+ 173500 uses
+ 173600 uses
+ 173700 uses
+ 173800 uses
+ 173900 uses
+ 174000 uses
+ 174100 uses
+ 174200 uses
+ 174300 uses
+ 174400 uses
+ 174500 uses
+ 174600 uses
+ 174700 uses
+ 174800 uses
+ 174900 uses
+ 175000 uses
+ 175100 uses
+ 175200 uses
+ 175300 uses
+ 175400 uses
+ 175500 uses
+ 175600 uses
+ 175700 uses
+ 175800 uses
+ 175900 uses
+ 176000 uses
+ 176100 uses
+ 176200 uses
+ 176300 uses
+ 176400 uses
+ 176500 uses
+ 176600 uses
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "clk_skew_adjust".
+Reading "sky130_ef_sc_hd__fakediode_2".
+Reading "wb_host".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+Reading "sdrc_top".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+ 20100 uses
+ 20200 uses
+ 20300 uses
+ 20400 uses
+ 20500 uses
+ 20600 uses
+ 20700 uses
+ 20800 uses
+ 20900 uses
+ 21000 uses
+ 21100 uses
+ 21200 uses
+ 21300 uses
+ 21400 uses
+ 21500 uses
+ 21600 uses
+ 21700 uses
+ 21800 uses
+ 21900 uses
+ 22000 uses
+ 22100 uses
+ 22200 uses
+ 22300 uses
+ 22400 uses
+ 22500 uses
+ 22600 uses
+ 22700 uses
+ 22800 uses
+ 22900 uses
+ 23000 uses
+ 23100 uses
+ 23200 uses
+ 23300 uses
+ 23400 uses
+ 23500 uses
+ 23600 uses
+ 23700 uses
+ 23800 uses
+ 23900 uses
+ 24000 uses
+ 24100 uses
+ 24200 uses
+ 24300 uses
+ 24400 uses
+ 24500 uses
+ 24600 uses
+ 24700 uses
+ 24800 uses
+ 24900 uses
+ 25000 uses
+ 25100 uses
+ 25200 uses
+ 25300 uses
+ 25400 uses
+ 25500 uses
+ 25600 uses
+ 25700 uses
+ 25800 uses
+ 25900 uses
+ 26000 uses
+ 26100 uses
+ 26200 uses
+ 26300 uses
+ 26400 uses
+ 26500 uses
+ 26600 uses
+ 26700 uses
+ 26800 uses
+ 26900 uses
+ 27000 uses
+ 27100 uses
+ 27200 uses
+ 27300 uses
+ 27400 uses
+ 27500 uses
+ 27600 uses
+ 27700 uses
+ 27800 uses
+ 27900 uses
+ 28000 uses
+ 28100 uses
+ 28200 uses
+ 28300 uses
+ 28400 uses
+ 28500 uses
+ 28600 uses
+ 28700 uses
+ 28800 uses
+ 28900 uses
+ 29000 uses
+ 29100 uses
+ 29200 uses
+ 29300 uses
+ 29400 uses
+ 29500 uses
+ 29600 uses
+ 29700 uses
+ 29800 uses
+ 29900 uses
+ 30000 uses
+ 30100 uses
+ 30200 uses
+ 30300 uses
+ 30400 uses
+ 30500 uses
+ 30600 uses
+ 30700 uses
+ 30800 uses
+ 30900 uses
+ 31000 uses
+ 31100 uses
+ 31200 uses
+ 31300 uses
+ 31400 uses
+ 31500 uses
+ 31600 uses
+ 31700 uses
+ 31800 uses
+ 31900 uses
+ 32000 uses
+ 32100 uses
+ 32200 uses
+ 32300 uses
+ 32400 uses
+ 32500 uses
+ 32600 uses
+ 32700 uses
+ 32800 uses
+ 32900 uses
+ 33000 uses
+ 33100 uses
+ 33200 uses
+ 33300 uses
+ 33400 uses
+ 33500 uses
+ 33600 uses
+ 33700 uses
+ 33800 uses
+ 33900 uses
+ 34000 uses
+ 34100 uses
+ 34200 uses
+ 34300 uses
+ 34400 uses
+ 34500 uses
+ 34600 uses
+ 34700 uses
+ 34800 uses
+ 34900 uses
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "uart_core".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
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+Reading "wb_interconnect".
+ 100 uses
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+ 35900 uses
+Reading "glbl_cfg".
+ 100 uses
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+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "spim_top".
+ 100 uses
+ 200 uses
+ 300 uses
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+ 500 uses
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+ 11000 uses
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+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
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+ 12600 uses
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+ 23900 uses
+ 24000 uses
+ 24100 uses
+ 24200 uses
+ 24300 uses
+ 24400 uses
+ 24500 uses
+ 24600 uses
+ 24700 uses
+ 24800 uses
+Reading "user_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 20.00 x 3520.00 (-20.00, 0.00 ), ( 0.00, 3520.00) 70400.00
+lambda: 2000.00 x 352000.00 (-2000.00, 0.00 ), ( 0.00, 352000.00) 704000000.00
+internal: 4000 x 704000 ( -4000, 0 ), ( 0, 704000) 2816000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 20.00 x 3520.00 ( 2920.00, 0.00 ), ( 2940.00, 3520.00) 70400.00
+lambda: 2000.00 x 352000.00 ( 292000.00, 0.00 ), ( 294000.00, 352000.00) 704000000.00
+internal: 4000 x 704000 ( 584000, 0 ), ( 588000, 704000) 2816000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2960.00 x 20.00 (-20.00, -20.00), ( 2940.00, 0.00 ) 59200.00
+lambda: 296000.00 x 2000.00 (-2000.00, -2000.00), ( 294000.00, 0.00 ) 592000000.00
+internal: 592000 x 4000 ( -4000, -4000 ), ( 588000, 0 ) 2368000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2960.00 x 20.00 (-20.00, 3520.00), ( 2940.00, 3540.00) 59200.00
+lambda: 296000.00 x 2000.00 (-2000.00, 352000.00), ( 294000.00, 354000.00) 592000000.00
+internal: 592000 x 4000 ( -4000, 704000), ( 588000, 708000) 2368000000
+ Generating output for cell xor_target
+/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds
diff --git a/checks/erase_box_user_project_wrapper_empty.gds.log b/checks/erase_box_user_project_wrapper_empty.gds.log
new file mode 100644
index 0000000..a2e47b6
--- /dev/null
+++ b/checks/erase_box_user_project_wrapper_empty.gds.log
@@ -0,0 +1,45 @@
+/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty.gds /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty_erased.gds user_project_wrapper
+
+Magic 8.3 revision 182 - Compiled on Fri Jun 25 23:58:13 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Using technology "sky130A", version 1.0.116-4-g522a373
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 20.00 x 3520.00 (-20.00, 0.00 ), ( 0.00, 3520.00) 70400.00
+lambda: 2000.00 x 352000.00 (-2000.00, 0.00 ), ( 0.00, 352000.00) 704000000.00
+internal: 4000 x 704000 ( -4000, 0 ), ( 0, 704000) 2816000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 20.00 x 3520.00 ( 2920.00, 0.00 ), ( 2940.00, 3520.00) 70400.00
+lambda: 2000.00 x 352000.00 ( 292000.00, 0.00 ), ( 294000.00, 352000.00) 704000000.00
+internal: 4000 x 704000 ( 584000, 0 ), ( 588000, 704000) 2816000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2960.00 x 20.00 (-20.00, -20.00), ( 2940.00, 0.00 ) 59200.00
+lambda: 296000.00 x 2000.00 (-2000.00, -2000.00), ( 294000.00, 0.00 ) 592000000.00
+internal: 592000 x 4000 ( -4000, -4000 ), ( 588000, 0 ) 2368000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2960.00 x 20.00 (-20.00, 3520.00), ( 2940.00, 3540.00) 59200.00
+lambda: 296000.00 x 2000.00 (-2000.00, 352000.00), ( 294000.00, 354000.00) 592000000.00
+internal: 592000 x 4000 ( -4000, 704000), ( 588000, 708000) 2368000000
+ Generating output for cell xor_target
+/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty_erased.gds
diff --git a/checks/full_log.log b/checks/full_log.log
index 912e28a..2484dda 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -3,7 +3,7 @@
Step 0 done without fatal errors.
Executing Step 1 of 8: Project License Check
{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 503 non-compliant files with the SPDX Standard. Check full log for more information
+ SPDX COMPLIANCE Found 691 non-compliant files with the SPDX Standard. Check full log for more information
SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/a', '/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/test.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-fastroute_4.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.param', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/21-fastroute_5.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/19-fastroute_3.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/18-fastroute_2.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext']
Executing Step 2 of 8: YAML File Check
YAML file valid!
diff --git a/checks/magic_drc.log b/checks/magic_drc.log
new file mode 100644
index 0000000..7f275df
--- /dev/null
+++ b/checks/magic_drc.log
@@ -0,0 +1,3279 @@
+
+Magic 8.3 revision 182 - Compiled on Fri Jun 25 23:58:13 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/usr/local/bin/drc_checks/magic_drc_check.tcl" from command line.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "scr1_top_wb".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+ 20100 uses
+ 20200 uses
+ 20300 uses
+ 20400 uses
+ 20500 uses
+ 20600 uses
+ 20700 uses
+ 20800 uses
+ 20900 uses
+ 21000 uses
+ 21100 uses
+ 21200 uses
+ 21300 uses
+ 21400 uses
+ 21500 uses
+ 21600 uses
+ 21700 uses
+ 21800 uses
+ 21900 uses
+ 22000 uses
+ 22100 uses
+ 22200 uses
+ 22300 uses
+ 22400 uses
+ 22500 uses
+ 22600 uses
+ 22700 uses
+ 22800 uses
+ 22900 uses
+ 23000 uses
+ 23100 uses
+ 23200 uses
+ 23300 uses
+ 23400 uses
+ 23500 uses
+ 23600 uses
+ 23700 uses
+ 23800 uses
+ 23900 uses
+ 24000 uses
+ 24100 uses
+ 24200 uses
+ 24300 uses
+ 24400 uses
+ 24500 uses
+ 24600 uses
+ 24700 uses
+ 24800 uses
+ 24900 uses
+ 25000 uses
+ 25100 uses
+ 25200 uses
+ 25300 uses
+ 25400 uses
+ 25500 uses
+ 25600 uses
+ 25700 uses
+ 25800 uses
+ 25900 uses
+ 26000 uses
+ 26100 uses
+ 26200 uses
+ 26300 uses
+ 26400 uses
+ 26500 uses
+ 26600 uses
+ 26700 uses
+ 26800 uses
+ 26900 uses
+ 27000 uses
+ 27100 uses
+ 27200 uses
+ 27300 uses
+ 27400 uses
+ 27500 uses
+ 27600 uses
+ 27700 uses
+ 27800 uses
+ 27900 uses
+ 28000 uses
+ 28100 uses
+ 28200 uses
+ 28300 uses
+ 28400 uses
+ 28500 uses
+ 28600 uses
+ 28700 uses
+ 28800 uses
+ 28900 uses
+ 29000 uses
+ 29100 uses
+ 29200 uses
+ 29300 uses
+ 29400 uses
+ 29500 uses
+ 29600 uses
+ 29700 uses
+ 29800 uses
+ 29900 uses
+ 30000 uses
+ 30100 uses
+ 30200 uses
+ 30300 uses
+ 30400 uses
+ 30500 uses
+ 30600 uses
+ 30700 uses
+ 30800 uses
+ 30900 uses
+ 31000 uses
+ 31100 uses
+ 31200 uses
+ 31300 uses
+ 31400 uses
+ 31500 uses
+ 31600 uses
+ 31700 uses
+ 31800 uses
+ 31900 uses
+ 32000 uses
+ 32100 uses
+ 32200 uses
+ 32300 uses
+ 32400 uses
+ 32500 uses
+ 32600 uses
+ 32700 uses
+ 32800 uses
+ 32900 uses
+ 33000 uses
+ 33100 uses
+ 33200 uses
+ 33300 uses
+ 33400 uses
+ 33500 uses
+ 33600 uses
+ 33700 uses
+ 33800 uses
+ 33900 uses
+ 34000 uses
+ 34100 uses
+ 34200 uses
+ 34300 uses
+ 34400 uses
+ 34500 uses
+ 34600 uses
+ 34700 uses
+ 34800 uses
+ 34900 uses
+ 35000 uses
+ 35100 uses
+ 35200 uses
+ 35300 uses
+ 35400 uses
+ 35500 uses
+ 35600 uses
+ 35700 uses
+ 35800 uses
+ 35900 uses
+ 36000 uses
+ 36100 uses
+ 36200 uses
+ 36300 uses
+ 36400 uses
+ 36500 uses
+ 36600 uses
+ 36700 uses
+ 36800 uses
+ 36900 uses
+ 37000 uses
+ 37100 uses
+ 37200 uses
+ 37300 uses
+ 37400 uses
+ 37500 uses
+ 37600 uses
+ 37700 uses
+ 37800 uses
+ 37900 uses
+ 38000 uses
+ 38100 uses
+ 38200 uses
+ 38300 uses
+ 38400 uses
+ 38500 uses
+ 38600 uses
+ 38700 uses
+ 38800 uses
+ 38900 uses
+ 39000 uses
+ 39100 uses
+ 39200 uses
+ 39300 uses
+ 39400 uses
+ 39500 uses
+ 39600 uses
+ 39700 uses
+ 39800 uses
+ 39900 uses
+ 40000 uses
+ 40100 uses
+ 40200 uses
+ 40300 uses
+ 40400 uses
+ 40500 uses
+ 40600 uses
+ 40700 uses
+ 40800 uses
+ 40900 uses
+ 41000 uses
+ 41100 uses
+ 41200 uses
+ 41300 uses
+ 41400 uses
+ 41500 uses
+ 41600 uses
+ 41700 uses
+ 41800 uses
+ 41900 uses
+ 42000 uses
+ 42100 uses
+ 42200 uses
+ 42300 uses
+ 42400 uses
+ 42500 uses
+ 42600 uses
+ 42700 uses
+ 42800 uses
+ 42900 uses
+ 43000 uses
+ 43100 uses
+ 43200 uses
+ 43300 uses
+ 43400 uses
+ 43500 uses
+ 43600 uses
+ 43700 uses
+ 43800 uses
+ 43900 uses
+ 44000 uses
+ 44100 uses
+ 44200 uses
+ 44300 uses
+ 44400 uses
+ 44500 uses
+ 44600 uses
+ 44700 uses
+ 44800 uses
+ 44900 uses
+ 45000 uses
+ 45100 uses
+ 45200 uses
+ 45300 uses
+ 45400 uses
+ 45500 uses
+ 45600 uses
+ 45700 uses
+ 45800 uses
+ 45900 uses
+ 46000 uses
+ 46100 uses
+ 46200 uses
+ 46300 uses
+ 46400 uses
+ 46500 uses
+ 46600 uses
+ 46700 uses
+ 46800 uses
+ 46900 uses
+ 47000 uses
+ 47100 uses
+ 47200 uses
+ 47300 uses
+ 47400 uses
+ 47500 uses
+ 47600 uses
+ 47700 uses
+ 47800 uses
+ 47900 uses
+ 48000 uses
+ 48100 uses
+ 48200 uses
+ 48300 uses
+ 48400 uses
+ 48500 uses
+ 48600 uses
+ 48700 uses
+ 48800 uses
+ 48900 uses
+ 49000 uses
+ 49100 uses
+ 49200 uses
+ 49300 uses
+ 49400 uses
+ 49500 uses
+ 49600 uses
+ 49700 uses
+ 49800 uses
+ 49900 uses
+ 50000 uses
+ 50100 uses
+ 50200 uses
+ 50300 uses
+ 50400 uses
+ 50500 uses
+ 50600 uses
+ 50700 uses
+ 50800 uses
+ 50900 uses
+ 51000 uses
+ 51100 uses
+ 51200 uses
+ 51300 uses
+ 51400 uses
+ 51500 uses
+ 51600 uses
+ 51700 uses
+ 51800 uses
+ 51900 uses
+ 52000 uses
+ 52100 uses
+ 52200 uses
+ 52300 uses
+ 52400 uses
+ 52500 uses
+ 52600 uses
+ 52700 uses
+ 52800 uses
+ 52900 uses
+ 53000 uses
+ 53100 uses
+ 53200 uses
+ 53300 uses
+ 53400 uses
+ 53500 uses
+ 53600 uses
+ 53700 uses
+ 53800 uses
+ 53900 uses
+ 54000 uses
+ 54100 uses
+ 54200 uses
+ 54300 uses
+ 54400 uses
+ 54500 uses
+ 54600 uses
+ 54700 uses
+ 54800 uses
+ 54900 uses
+ 55000 uses
+ 55100 uses
+ 55200 uses
+ 55300 uses
+ 55400 uses
+ 55500 uses
+ 55600 uses
+ 55700 uses
+ 55800 uses
+ 55900 uses
+ 56000 uses
+ 56100 uses
+ 56200 uses
+ 56300 uses
+ 56400 uses
+ 56500 uses
+ 56600 uses
+ 56700 uses
+ 56800 uses
+ 56900 uses
+ 57000 uses
+ 57100 uses
+ 57200 uses
+ 57300 uses
+ 57400 uses
+ 57500 uses
+ 57600 uses
+ 57700 uses
+ 57800 uses
+ 57900 uses
+ 58000 uses
+ 58100 uses
+ 58200 uses
+ 58300 uses
+ 58400 uses
+ 58500 uses
+ 58600 uses
+ 58700 uses
+ 58800 uses
+ 58900 uses
+ 59000 uses
+ 59100 uses
+ 59200 uses
+ 59300 uses
+ 59400 uses
+ 59500 uses
+ 59600 uses
+ 59700 uses
+ 59800 uses
+ 59900 uses
+ 60000 uses
+ 60100 uses
+ 60200 uses
+ 60300 uses
+ 60400 uses
+ 60500 uses
+ 60600 uses
+ 60700 uses
+ 60800 uses
+ 60900 uses
+ 61000 uses
+ 61100 uses
+ 61200 uses
+ 61300 uses
+ 61400 uses
+ 61500 uses
+ 61600 uses
+ 61700 uses
+ 61800 uses
+ 61900 uses
+ 62000 uses
+ 62100 uses
+ 62200 uses
+ 62300 uses
+ 62400 uses
+ 62500 uses
+ 62600 uses
+ 62700 uses
+ 62800 uses
+ 62900 uses
+ 63000 uses
+ 63100 uses
+ 63200 uses
+ 63300 uses
+ 63400 uses
+ 63500 uses
+ 63600 uses
+ 63700 uses
+ 63800 uses
+ 63900 uses
+ 64000 uses
+ 64100 uses
+ 64200 uses
+ 64300 uses
+ 64400 uses
+ 64500 uses
+ 64600 uses
+ 64700 uses
+ 64800 uses
+ 64900 uses
+ 65000 uses
+ 65100 uses
+ 65200 uses
+ 65300 uses
+ 65400 uses
+ 65500 uses
+ 65600 uses
+ 65700 uses
+ 65800 uses
+ 65900 uses
+ 66000 uses
+ 66100 uses
+ 66200 uses
+ 66300 uses
+ 66400 uses
+ 66500 uses
+ 66600 uses
+ 66700 uses
+ 66800 uses
+ 66900 uses
+ 67000 uses
+ 67100 uses
+ 67200 uses
+ 67300 uses
+ 67400 uses
+ 67500 uses
+ 67600 uses
+ 67700 uses
+ 67800 uses
+ 67900 uses
+ 68000 uses
+ 68100 uses
+ 68200 uses
+ 68300 uses
+ 68400 uses
+ 68500 uses
+ 68600 uses
+ 68700 uses
+ 68800 uses
+ 68900 uses
+ 69000 uses
+ 69100 uses
+ 69200 uses
+ 69300 uses
+ 69400 uses
+ 69500 uses
+ 69600 uses
+ 69700 uses
+ 69800 uses
+ 69900 uses
+ 70000 uses
+ 70100 uses
+ 70200 uses
+ 70300 uses
+ 70400 uses
+ 70500 uses
+ 70600 uses
+ 70700 uses
+ 70800 uses
+ 70900 uses
+ 71000 uses
+ 71100 uses
+ 71200 uses
+ 71300 uses
+ 71400 uses
+ 71500 uses
+ 71600 uses
+ 71700 uses
+ 71800 uses
+ 71900 uses
+ 72000 uses
+ 72100 uses
+ 72200 uses
+ 72300 uses
+ 72400 uses
+ 72500 uses
+ 72600 uses
+ 72700 uses
+ 72800 uses
+ 72900 uses
+ 73000 uses
+ 73100 uses
+ 73200 uses
+ 73300 uses
+ 73400 uses
+ 73500 uses
+ 73600 uses
+ 73700 uses
+ 73800 uses
+ 73900 uses
+ 74000 uses
+ 74100 uses
+ 74200 uses
+ 74300 uses
+ 74400 uses
+ 74500 uses
+ 74600 uses
+ 74700 uses
+ 74800 uses
+ 74900 uses
+ 75000 uses
+ 75100 uses
+ 75200 uses
+ 75300 uses
+ 75400 uses
+ 75500 uses
+ 75600 uses
+ 75700 uses
+ 75800 uses
+ 75900 uses
+ 76000 uses
+ 76100 uses
+ 76200 uses
+ 76300 uses
+ 76400 uses
+ 76500 uses
+ 76600 uses
+ 76700 uses
+ 76800 uses
+ 76900 uses
+ 77000 uses
+ 77100 uses
+ 77200 uses
+ 77300 uses
+ 77400 uses
+ 77500 uses
+ 77600 uses
+ 77700 uses
+ 77800 uses
+ 77900 uses
+ 78000 uses
+ 78100 uses
+ 78200 uses
+ 78300 uses
+ 78400 uses
+ 78500 uses
+ 78600 uses
+ 78700 uses
+ 78800 uses
+ 78900 uses
+ 79000 uses
+ 79100 uses
+ 79200 uses
+ 79300 uses
+ 79400 uses
+ 79500 uses
+ 79600 uses
+ 79700 uses
+ 79800 uses
+ 79900 uses
+ 80000 uses
+ 80100 uses
+ 80200 uses
+ 80300 uses
+ 80400 uses
+ 80500 uses
+ 80600 uses
+ 80700 uses
+ 80800 uses
+ 80900 uses
+ 81000 uses
+ 81100 uses
+ 81200 uses
+ 81300 uses
+ 81400 uses
+ 81500 uses
+ 81600 uses
+ 81700 uses
+ 81800 uses
+ 81900 uses
+ 82000 uses
+ 82100 uses
+ 82200 uses
+ 82300 uses
+ 82400 uses
+ 82500 uses
+ 82600 uses
+ 82700 uses
+ 82800 uses
+ 82900 uses
+ 83000 uses
+ 83100 uses
+ 83200 uses
+ 83300 uses
+ 83400 uses
+ 83500 uses
+ 83600 uses
+ 83700 uses
+ 83800 uses
+ 83900 uses
+ 84000 uses
+ 84100 uses
+ 84200 uses
+ 84300 uses
+ 84400 uses
+ 84500 uses
+ 84600 uses
+ 84700 uses
+ 84800 uses
+ 84900 uses
+ 85000 uses
+ 85100 uses
+ 85200 uses
+ 85300 uses
+ 85400 uses
+ 85500 uses
+ 85600 uses
+ 85700 uses
+ 85800 uses
+ 85900 uses
+ 86000 uses
+ 86100 uses
+ 86200 uses
+ 86300 uses
+ 86400 uses
+ 86500 uses
+ 86600 uses
+ 86700 uses
+ 86800 uses
+ 86900 uses
+ 87000 uses
+ 87100 uses
+ 87200 uses
+ 87300 uses
+ 87400 uses
+ 87500 uses
+ 87600 uses
+ 87700 uses
+ 87800 uses
+ 87900 uses
+ 88000 uses
+ 88100 uses
+ 88200 uses
+ 88300 uses
+ 88400 uses
+ 88500 uses
+ 88600 uses
+ 88700 uses
+ 88800 uses
+ 88900 uses
+ 89000 uses
+ 89100 uses
+ 89200 uses
+ 89300 uses
+ 89400 uses
+ 89500 uses
+ 89600 uses
+ 89700 uses
+ 89800 uses
+ 89900 uses
+ 90000 uses
+ 90100 uses
+ 90200 uses
+ 90300 uses
+ 90400 uses
+ 90500 uses
+ 90600 uses
+ 90700 uses
+ 90800 uses
+ 90900 uses
+ 91000 uses
+ 91100 uses
+ 91200 uses
+ 91300 uses
+ 91400 uses
+ 91500 uses
+ 91600 uses
+ 91700 uses
+ 91800 uses
+ 91900 uses
+ 92000 uses
+ 92100 uses
+ 92200 uses
+ 92300 uses
+ 92400 uses
+ 92500 uses
+ 92600 uses
+ 92700 uses
+ 92800 uses
+ 92900 uses
+ 93000 uses
+ 93100 uses
+ 93200 uses
+ 93300 uses
+ 93400 uses
+ 93500 uses
+ 93600 uses
+ 93700 uses
+ 93800 uses
+ 93900 uses
+ 94000 uses
+ 94100 uses
+ 94200 uses
+ 94300 uses
+ 94400 uses
+ 94500 uses
+ 94600 uses
+ 94700 uses
+ 94800 uses
+ 94900 uses
+ 95000 uses
+ 95100 uses
+ 95200 uses
+ 95300 uses
+ 95400 uses
+ 95500 uses
+ 95600 uses
+ 95700 uses
+ 95800 uses
+ 95900 uses
+ 96000 uses
+ 96100 uses
+ 96200 uses
+ 96300 uses
+ 96400 uses
+ 96500 uses
+ 96600 uses
+ 96700 uses
+ 96800 uses
+ 96900 uses
+ 97000 uses
+ 97100 uses
+ 97200 uses
+ 97300 uses
+ 97400 uses
+ 97500 uses
+ 97600 uses
+ 97700 uses
+ 97800 uses
+ 97900 uses
+ 98000 uses
+ 98100 uses
+ 98200 uses
+ 98300 uses
+ 98400 uses
+ 98500 uses
+ 98600 uses
+ 98700 uses
+ 98800 uses
+ 98900 uses
+ 99000 uses
+ 99100 uses
+ 99200 uses
+ 99300 uses
+ 99400 uses
+ 99500 uses
+ 99600 uses
+ 99700 uses
+ 99800 uses
+ 99900 uses
+ 100000 uses
+ 100100 uses
+ 100200 uses
+ 100300 uses
+ 100400 uses
+ 100500 uses
+ 100600 uses
+ 100700 uses
+ 100800 uses
+ 100900 uses
+ 101000 uses
+ 101100 uses
+ 101200 uses
+ 101300 uses
+ 101400 uses
+ 101500 uses
+ 101600 uses
+ 101700 uses
+ 101800 uses
+ 101900 uses
+ 102000 uses
+ 102100 uses
+ 102200 uses
+ 102300 uses
+ 102400 uses
+ 102500 uses
+ 102600 uses
+ 102700 uses
+ 102800 uses
+ 102900 uses
+ 103000 uses
+ 103100 uses
+ 103200 uses
+ 103300 uses
+ 103400 uses
+ 103500 uses
+ 103600 uses
+ 103700 uses
+ 103800 uses
+ 103900 uses
+ 104000 uses
+ 104100 uses
+ 104200 uses
+ 104300 uses
+ 104400 uses
+ 104500 uses
+ 104600 uses
+ 104700 uses
+ 104800 uses
+ 104900 uses
+ 105000 uses
+ 105100 uses
+ 105200 uses
+ 105300 uses
+ 105400 uses
+ 105500 uses
+ 105600 uses
+ 105700 uses
+ 105800 uses
+ 105900 uses
+ 106000 uses
+ 106100 uses
+ 106200 uses
+ 106300 uses
+ 106400 uses
+ 106500 uses
+ 106600 uses
+ 106700 uses
+ 106800 uses
+ 106900 uses
+ 107000 uses
+ 107100 uses
+ 107200 uses
+ 107300 uses
+ 107400 uses
+ 107500 uses
+ 107600 uses
+ 107700 uses
+ 107800 uses
+ 107900 uses
+ 108000 uses
+ 108100 uses
+ 108200 uses
+ 108300 uses
+ 108400 uses
+ 108500 uses
+ 108600 uses
+ 108700 uses
+ 108800 uses
+ 108900 uses
+ 109000 uses
+ 109100 uses
+ 109200 uses
+ 109300 uses
+ 109400 uses
+ 109500 uses
+ 109600 uses
+ 109700 uses
+ 109800 uses
+ 109900 uses
+ 110000 uses
+ 110100 uses
+ 110200 uses
+ 110300 uses
+ 110400 uses
+ 110500 uses
+ 110600 uses
+ 110700 uses
+ 110800 uses
+ 110900 uses
+ 111000 uses
+ 111100 uses
+ 111200 uses
+ 111300 uses
+ 111400 uses
+ 111500 uses
+ 111600 uses
+ 111700 uses
+ 111800 uses
+ 111900 uses
+ 112000 uses
+ 112100 uses
+ 112200 uses
+ 112300 uses
+ 112400 uses
+ 112500 uses
+ 112600 uses
+ 112700 uses
+ 112800 uses
+ 112900 uses
+ 113000 uses
+ 113100 uses
+ 113200 uses
+ 113300 uses
+ 113400 uses
+ 113500 uses
+ 113600 uses
+ 113700 uses
+ 113800 uses
+ 113900 uses
+ 114000 uses
+ 114100 uses
+ 114200 uses
+ 114300 uses
+ 114400 uses
+ 114500 uses
+ 114600 uses
+ 114700 uses
+ 114800 uses
+ 114900 uses
+ 115000 uses
+ 115100 uses
+ 115200 uses
+ 115300 uses
+ 115400 uses
+ 115500 uses
+ 115600 uses
+ 115700 uses
+ 115800 uses
+ 115900 uses
+ 116000 uses
+ 116100 uses
+ 116200 uses
+ 116300 uses
+ 116400 uses
+ 116500 uses
+ 116600 uses
+ 116700 uses
+ 116800 uses
+ 116900 uses
+ 117000 uses
+ 117100 uses
+ 117200 uses
+ 117300 uses
+ 117400 uses
+ 117500 uses
+ 117600 uses
+ 117700 uses
+ 117800 uses
+ 117900 uses
+ 118000 uses
+ 118100 uses
+ 118200 uses
+ 118300 uses
+ 118400 uses
+ 118500 uses
+ 118600 uses
+ 118700 uses
+ 118800 uses
+ 118900 uses
+ 119000 uses
+ 119100 uses
+ 119200 uses
+ 119300 uses
+ 119400 uses
+ 119500 uses
+ 119600 uses
+ 119700 uses
+ 119800 uses
+ 119900 uses
+ 120000 uses
+ 120100 uses
+ 120200 uses
+ 120300 uses
+ 120400 uses
+ 120500 uses
+ 120600 uses
+ 120700 uses
+ 120800 uses
+ 120900 uses
+ 121000 uses
+ 121100 uses
+ 121200 uses
+ 121300 uses
+ 121400 uses
+ 121500 uses
+ 121600 uses
+ 121700 uses
+ 121800 uses
+ 121900 uses
+ 122000 uses
+ 122100 uses
+ 122200 uses
+ 122300 uses
+ 122400 uses
+ 122500 uses
+ 122600 uses
+ 122700 uses
+ 122800 uses
+ 122900 uses
+ 123000 uses
+ 123100 uses
+ 123200 uses
+ 123300 uses
+ 123400 uses
+ 123500 uses
+ 123600 uses
+ 123700 uses
+ 123800 uses
+ 123900 uses
+ 124000 uses
+ 124100 uses
+ 124200 uses
+ 124300 uses
+ 124400 uses
+ 124500 uses
+ 124600 uses
+ 124700 uses
+ 124800 uses
+ 124900 uses
+ 125000 uses
+ 125100 uses
+ 125200 uses
+ 125300 uses
+ 125400 uses
+ 125500 uses
+ 125600 uses
+ 125700 uses
+ 125800 uses
+ 125900 uses
+ 126000 uses
+ 126100 uses
+ 126200 uses
+ 126300 uses
+ 126400 uses
+ 126500 uses
+ 126600 uses
+ 126700 uses
+ 126800 uses
+ 126900 uses
+ 127000 uses
+ 127100 uses
+ 127200 uses
+ 127300 uses
+ 127400 uses
+ 127500 uses
+ 127600 uses
+ 127700 uses
+ 127800 uses
+ 127900 uses
+ 128000 uses
+ 128100 uses
+ 128200 uses
+ 128300 uses
+ 128400 uses
+ 128500 uses
+ 128600 uses
+ 128700 uses
+ 128800 uses
+ 128900 uses
+ 129000 uses
+ 129100 uses
+ 129200 uses
+ 129300 uses
+ 129400 uses
+ 129500 uses
+ 129600 uses
+ 129700 uses
+ 129800 uses
+ 129900 uses
+ 130000 uses
+ 130100 uses
+ 130200 uses
+ 130300 uses
+ 130400 uses
+ 130500 uses
+ 130600 uses
+ 130700 uses
+ 130800 uses
+ 130900 uses
+ 131000 uses
+ 131100 uses
+ 131200 uses
+ 131300 uses
+ 131400 uses
+ 131500 uses
+ 131600 uses
+ 131700 uses
+ 131800 uses
+ 131900 uses
+ 132000 uses
+ 132100 uses
+ 132200 uses
+ 132300 uses
+ 132400 uses
+ 132500 uses
+ 132600 uses
+ 132700 uses
+ 132800 uses
+ 132900 uses
+ 133000 uses
+ 133100 uses
+ 133200 uses
+ 133300 uses
+ 133400 uses
+ 133500 uses
+ 133600 uses
+ 133700 uses
+ 133800 uses
+ 133900 uses
+ 134000 uses
+ 134100 uses
+ 134200 uses
+ 134300 uses
+ 134400 uses
+ 134500 uses
+ 134600 uses
+ 134700 uses
+ 134800 uses
+ 134900 uses
+ 135000 uses
+ 135100 uses
+ 135200 uses
+ 135300 uses
+ 135400 uses
+ 135500 uses
+ 135600 uses
+ 135700 uses
+ 135800 uses
+ 135900 uses
+ 136000 uses
+ 136100 uses
+ 136200 uses
+ 136300 uses
+ 136400 uses
+ 136500 uses
+ 136600 uses
+ 136700 uses
+ 136800 uses
+ 136900 uses
+ 137000 uses
+ 137100 uses
+ 137200 uses
+ 137300 uses
+ 137400 uses
+ 137500 uses
+ 137600 uses
+ 137700 uses
+ 137800 uses
+ 137900 uses
+ 138000 uses
+ 138100 uses
+ 138200 uses
+ 138300 uses
+ 138400 uses
+ 138500 uses
+ 138600 uses
+ 138700 uses
+ 138800 uses
+ 138900 uses
+ 139000 uses
+ 139100 uses
+ 139200 uses
+ 139300 uses
+ 139400 uses
+ 139500 uses
+ 139600 uses
+ 139700 uses
+ 139800 uses
+ 139900 uses
+ 140000 uses
+ 140100 uses
+ 140200 uses
+ 140300 uses
+ 140400 uses
+ 140500 uses
+ 140600 uses
+ 140700 uses
+ 140800 uses
+ 140900 uses
+ 141000 uses
+ 141100 uses
+ 141200 uses
+ 141300 uses
+ 141400 uses
+ 141500 uses
+ 141600 uses
+ 141700 uses
+ 141800 uses
+ 141900 uses
+ 142000 uses
+ 142100 uses
+ 142200 uses
+ 142300 uses
+ 142400 uses
+ 142500 uses
+ 142600 uses
+ 142700 uses
+ 142800 uses
+ 142900 uses
+ 143000 uses
+ 143100 uses
+ 143200 uses
+ 143300 uses
+ 143400 uses
+ 143500 uses
+ 143600 uses
+ 143700 uses
+ 143800 uses
+ 143900 uses
+ 144000 uses
+ 144100 uses
+ 144200 uses
+ 144300 uses
+ 144400 uses
+ 144500 uses
+ 144600 uses
+ 144700 uses
+ 144800 uses
+ 144900 uses
+ 145000 uses
+ 145100 uses
+ 145200 uses
+ 145300 uses
+ 145400 uses
+ 145500 uses
+ 145600 uses
+ 145700 uses
+ 145800 uses
+ 145900 uses
+ 146000 uses
+ 146100 uses
+ 146200 uses
+ 146300 uses
+ 146400 uses
+ 146500 uses
+ 146600 uses
+ 146700 uses
+ 146800 uses
+ 146900 uses
+ 147000 uses
+ 147100 uses
+ 147200 uses
+ 147300 uses
+ 147400 uses
+ 147500 uses
+ 147600 uses
+ 147700 uses
+ 147800 uses
+ 147900 uses
+ 148000 uses
+ 148100 uses
+ 148200 uses
+ 148300 uses
+ 148400 uses
+ 148500 uses
+ 148600 uses
+ 148700 uses
+ 148800 uses
+ 148900 uses
+ 149000 uses
+ 149100 uses
+ 149200 uses
+ 149300 uses
+ 149400 uses
+ 149500 uses
+ 149600 uses
+ 149700 uses
+ 149800 uses
+ 149900 uses
+ 150000 uses
+ 150100 uses
+ 150200 uses
+ 150300 uses
+ 150400 uses
+ 150500 uses
+ 150600 uses
+ 150700 uses
+ 150800 uses
+ 150900 uses
+ 151000 uses
+ 151100 uses
+ 151200 uses
+ 151300 uses
+ 151400 uses
+ 151500 uses
+ 151600 uses
+ 151700 uses
+ 151800 uses
+ 151900 uses
+ 152000 uses
+ 152100 uses
+ 152200 uses
+ 152300 uses
+ 152400 uses
+ 152500 uses
+ 152600 uses
+ 152700 uses
+ 152800 uses
+ 152900 uses
+ 153000 uses
+ 153100 uses
+ 153200 uses
+ 153300 uses
+ 153400 uses
+ 153500 uses
+ 153600 uses
+ 153700 uses
+ 153800 uses
+ 153900 uses
+ 154000 uses
+ 154100 uses
+ 154200 uses
+ 154300 uses
+ 154400 uses
+ 154500 uses
+ 154600 uses
+ 154700 uses
+ 154800 uses
+ 154900 uses
+ 155000 uses
+ 155100 uses
+ 155200 uses
+ 155300 uses
+ 155400 uses
+ 155500 uses
+ 155600 uses
+ 155700 uses
+ 155800 uses
+ 155900 uses
+ 156000 uses
+ 156100 uses
+ 156200 uses
+ 156300 uses
+ 156400 uses
+ 156500 uses
+ 156600 uses
+ 156700 uses
+ 156800 uses
+ 156900 uses
+ 157000 uses
+ 157100 uses
+ 157200 uses
+ 157300 uses
+ 157400 uses
+ 157500 uses
+ 157600 uses
+ 157700 uses
+ 157800 uses
+ 157900 uses
+ 158000 uses
+ 158100 uses
+ 158200 uses
+ 158300 uses
+ 158400 uses
+ 158500 uses
+ 158600 uses
+ 158700 uses
+ 158800 uses
+ 158900 uses
+ 159000 uses
+ 159100 uses
+ 159200 uses
+ 159300 uses
+ 159400 uses
+ 159500 uses
+ 159600 uses
+ 159700 uses
+ 159800 uses
+ 159900 uses
+ 160000 uses
+ 160100 uses
+ 160200 uses
+ 160300 uses
+ 160400 uses
+ 160500 uses
+ 160600 uses
+ 160700 uses
+ 160800 uses
+ 160900 uses
+ 161000 uses
+ 161100 uses
+ 161200 uses
+ 161300 uses
+ 161400 uses
+ 161500 uses
+ 161600 uses
+ 161700 uses
+ 161800 uses
+ 161900 uses
+ 162000 uses
+ 162100 uses
+ 162200 uses
+ 162300 uses
+ 162400 uses
+ 162500 uses
+ 162600 uses
+ 162700 uses
+ 162800 uses
+ 162900 uses
+ 163000 uses
+ 163100 uses
+ 163200 uses
+ 163300 uses
+ 163400 uses
+ 163500 uses
+ 163600 uses
+ 163700 uses
+ 163800 uses
+ 163900 uses
+ 164000 uses
+ 164100 uses
+ 164200 uses
+ 164300 uses
+ 164400 uses
+ 164500 uses
+ 164600 uses
+ 164700 uses
+ 164800 uses
+ 164900 uses
+ 165000 uses
+ 165100 uses
+ 165200 uses
+ 165300 uses
+ 165400 uses
+ 165500 uses
+ 165600 uses
+ 165700 uses
+ 165800 uses
+ 165900 uses
+ 166000 uses
+ 166100 uses
+ 166200 uses
+ 166300 uses
+ 166400 uses
+ 166500 uses
+ 166600 uses
+ 166700 uses
+ 166800 uses
+ 166900 uses
+ 167000 uses
+ 167100 uses
+ 167200 uses
+ 167300 uses
+ 167400 uses
+ 167500 uses
+ 167600 uses
+ 167700 uses
+ 167800 uses
+ 167900 uses
+ 168000 uses
+ 168100 uses
+ 168200 uses
+ 168300 uses
+ 168400 uses
+ 168500 uses
+ 168600 uses
+ 168700 uses
+ 168800 uses
+ 168900 uses
+ 169000 uses
+ 169100 uses
+ 169200 uses
+ 169300 uses
+ 169400 uses
+ 169500 uses
+ 169600 uses
+ 169700 uses
+ 169800 uses
+ 169900 uses
+ 170000 uses
+ 170100 uses
+ 170200 uses
+ 170300 uses
+ 170400 uses
+ 170500 uses
+ 170600 uses
+ 170700 uses
+ 170800 uses
+ 170900 uses
+ 171000 uses
+ 171100 uses
+ 171200 uses
+ 171300 uses
+ 171400 uses
+ 171500 uses
+ 171600 uses
+ 171700 uses
+ 171800 uses
+ 171900 uses
+ 172000 uses
+ 172100 uses
+ 172200 uses
+ 172300 uses
+ 172400 uses
+ 172500 uses
+ 172600 uses
+ 172700 uses
+ 172800 uses
+ 172900 uses
+ 173000 uses
+ 173100 uses
+ 173200 uses
+ 173300 uses
+ 173400 uses
+ 173500 uses
+ 173600 uses
+ 173700 uses
+ 173800 uses
+ 173900 uses
+ 174000 uses
+ 174100 uses
+ 174200 uses
+ 174300 uses
+ 174400 uses
+ 174500 uses
+ 174600 uses
+ 174700 uses
+ 174800 uses
+ 174900 uses
+ 175000 uses
+ 175100 uses
+ 175200 uses
+ 175300 uses
+ 175400 uses
+ 175500 uses
+ 175600 uses
+ 175700 uses
+ 175800 uses
+ 175900 uses
+ 176000 uses
+ 176100 uses
+ 176200 uses
+ 176300 uses
+ 176400 uses
+ 176500 uses
+ 176600 uses
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "clk_skew_adjust".
+Reading "sky130_ef_sc_hd__fakediode_2".
+Reading "wb_host".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+Reading "sdrc_top".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+ 20100 uses
+ 20200 uses
+ 20300 uses
+ 20400 uses
+ 20500 uses
+ 20600 uses
+ 20700 uses
+ 20800 uses
+ 20900 uses
+ 21000 uses
+ 21100 uses
+ 21200 uses
+ 21300 uses
+ 21400 uses
+ 21500 uses
+ 21600 uses
+ 21700 uses
+ 21800 uses
+ 21900 uses
+ 22000 uses
+ 22100 uses
+ 22200 uses
+ 22300 uses
+ 22400 uses
+ 22500 uses
+ 22600 uses
+ 22700 uses
+ 22800 uses
+ 22900 uses
+ 23000 uses
+ 23100 uses
+ 23200 uses
+ 23300 uses
+ 23400 uses
+ 23500 uses
+ 23600 uses
+ 23700 uses
+ 23800 uses
+ 23900 uses
+ 24000 uses
+ 24100 uses
+ 24200 uses
+ 24300 uses
+ 24400 uses
+ 24500 uses
+ 24600 uses
+ 24700 uses
+ 24800 uses
+ 24900 uses
+ 25000 uses
+ 25100 uses
+ 25200 uses
+ 25300 uses
+ 25400 uses
+ 25500 uses
+ 25600 uses
+ 25700 uses
+ 25800 uses
+ 25900 uses
+ 26000 uses
+ 26100 uses
+ 26200 uses
+ 26300 uses
+ 26400 uses
+ 26500 uses
+ 26600 uses
+ 26700 uses
+ 26800 uses
+ 26900 uses
+ 27000 uses
+ 27100 uses
+ 27200 uses
+ 27300 uses
+ 27400 uses
+ 27500 uses
+ 27600 uses
+ 27700 uses
+ 27800 uses
+ 27900 uses
+ 28000 uses
+ 28100 uses
+ 28200 uses
+ 28300 uses
+ 28400 uses
+ 28500 uses
+ 28600 uses
+ 28700 uses
+ 28800 uses
+ 28900 uses
+ 29000 uses
+ 29100 uses
+ 29200 uses
+ 29300 uses
+ 29400 uses
+ 29500 uses
+ 29600 uses
+ 29700 uses
+ 29800 uses
+ 29900 uses
+ 30000 uses
+ 30100 uses
+ 30200 uses
+ 30300 uses
+ 30400 uses
+ 30500 uses
+ 30600 uses
+ 30700 uses
+ 30800 uses
+ 30900 uses
+ 31000 uses
+ 31100 uses
+ 31200 uses
+ 31300 uses
+ 31400 uses
+ 31500 uses
+ 31600 uses
+ 31700 uses
+ 31800 uses
+ 31900 uses
+ 32000 uses
+ 32100 uses
+ 32200 uses
+ 32300 uses
+ 32400 uses
+ 32500 uses
+ 32600 uses
+ 32700 uses
+ 32800 uses
+ 32900 uses
+ 33000 uses
+ 33100 uses
+ 33200 uses
+ 33300 uses
+ 33400 uses
+ 33500 uses
+ 33600 uses
+ 33700 uses
+ 33800 uses
+ 33900 uses
+ 34000 uses
+ 34100 uses
+ 34200 uses
+ 34300 uses
+ 34400 uses
+ 34500 uses
+ 34600 uses
+ 34700 uses
+ 34800 uses
+ 34900 uses
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "uart_core".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+Reading "wb_interconnect".
+ 100 uses
+ 200 uses
+ 300 uses
+ 400 uses
+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
+ 900 uses
+ 1000 uses
+ 1100 uses
+ 1200 uses
+ 1300 uses
+ 1400 uses
+ 1500 uses
+ 1600 uses
+ 1700 uses
+ 1800 uses
+ 1900 uses
+ 2000 uses
+ 2100 uses
+ 2200 uses
+ 2300 uses
+ 2400 uses
+ 2500 uses
+ 2600 uses
+ 2700 uses
+ 2800 uses
+ 2900 uses
+ 3000 uses
+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
+ 3500 uses
+ 3600 uses
+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
+ 7700 uses
+ 7800 uses
+ 7900 uses
+ 8000 uses
+ 8100 uses
+ 8200 uses
+ 8300 uses
+ 8400 uses
+ 8500 uses
+ 8600 uses
+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
+ 9400 uses
+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
+ 10400 uses
+ 10500 uses
+ 10600 uses
+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
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+ 21500 uses
+ 21600 uses
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+ 23500 uses
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+ 23700 uses
+ 23800 uses
+ 23900 uses
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+ 30300 uses
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+ 30600 uses
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+ 30900 uses
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+ 31300 uses
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+ 32200 uses
+ 32300 uses
+ 32400 uses
+ 32500 uses
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+ 32700 uses
+ 32800 uses
+ 32900 uses
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+ 33200 uses
+ 33300 uses
+ 33400 uses
+ 33500 uses
+ 33600 uses
+ 33700 uses
+ 33800 uses
+ 33900 uses
+ 34000 uses
+ 34100 uses
+ 34200 uses
+ 34300 uses
+ 34400 uses
+ 34500 uses
+ 34600 uses
+ 34700 uses
+ 34800 uses
+ 34900 uses
+ 35000 uses
+ 35100 uses
+ 35200 uses
+ 35300 uses
+ 35400 uses
+ 35500 uses
+ 35600 uses
+ 35700 uses
+ 35800 uses
+ 35900 uses
+Reading "glbl_cfg".
+ 100 uses
+ 200 uses
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+ 3200 uses
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+ 3600 uses
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+ 3800 uses
+ 3900 uses
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+ 4100 uses
+ 4200 uses
+ 4300 uses
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+ 4500 uses
+ 4600 uses
+ 4700 uses
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+ 4900 uses
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+ 5100 uses
+ 5200 uses
+ 5300 uses
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+ 5500 uses
+ 5600 uses
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+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
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+ 6500 uses
+ 6600 uses
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+ 7100 uses
+ 7200 uses
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+ 7500 uses
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+ 8800 uses
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+ 9100 uses
+ 9200 uses
+ 9300 uses
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+ 9500 uses
+ 9600 uses
+ 9700 uses
+ 9800 uses
+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
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+ 10500 uses
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+ 10700 uses
+ 10800 uses
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+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "spim_top".
+ 100 uses
+ 200 uses
+ 300 uses
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+ 500 uses
+ 600 uses
+ 700 uses
+ 800 uses
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+ 2900 uses
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+ 3100 uses
+ 3200 uses
+ 3300 uses
+ 3400 uses
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+ 3700 uses
+ 3800 uses
+ 3900 uses
+ 4000 uses
+ 4100 uses
+ 4200 uses
+ 4300 uses
+ 4400 uses
+ 4500 uses
+ 4600 uses
+ 4700 uses
+ 4800 uses
+ 4900 uses
+ 5000 uses
+ 5100 uses
+ 5200 uses
+ 5300 uses
+ 5400 uses
+ 5500 uses
+ 5600 uses
+ 5700 uses
+ 5800 uses
+ 5900 uses
+ 6000 uses
+ 6100 uses
+ 6200 uses
+ 6300 uses
+ 6400 uses
+ 6500 uses
+ 6600 uses
+ 6700 uses
+ 6800 uses
+ 6900 uses
+ 7000 uses
+ 7100 uses
+ 7200 uses
+ 7300 uses
+ 7400 uses
+ 7500 uses
+ 7600 uses
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+ 7800 uses
+ 7900 uses
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+ 8100 uses
+ 8200 uses
+ 8300 uses
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+ 8500 uses
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+ 8700 uses
+ 8800 uses
+ 8900 uses
+ 9000 uses
+ 9100 uses
+ 9200 uses
+ 9300 uses
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+ 9900 uses
+ 10000 uses
+ 10100 uses
+ 10200 uses
+ 10300 uses
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+ 10700 uses
+ 10800 uses
+ 10900 uses
+ 11000 uses
+ 11100 uses
+ 11200 uses
+ 11300 uses
+ 11400 uses
+ 11500 uses
+ 11600 uses
+ 11700 uses
+ 11800 uses
+ 11900 uses
+ 12000 uses
+ 12100 uses
+ 12200 uses
+ 12300 uses
+ 12400 uses
+ 12500 uses
+ 12600 uses
+ 12700 uses
+ 12800 uses
+ 12900 uses
+ 13000 uses
+ 13100 uses
+ 13200 uses
+ 13300 uses
+ 13400 uses
+ 13500 uses
+ 13600 uses
+ 13700 uses
+ 13800 uses
+ 13900 uses
+ 14000 uses
+ 14100 uses
+ 14200 uses
+ 14300 uses
+ 14400 uses
+ 14500 uses
+ 14600 uses
+ 14700 uses
+ 14800 uses
+ 14900 uses
+ 15000 uses
+ 15100 uses
+ 15200 uses
+ 15300 uses
+ 15400 uses
+ 15500 uses
+ 15600 uses
+ 15700 uses
+ 15800 uses
+ 15900 uses
+ 16000 uses
+ 16100 uses
+ 16200 uses
+ 16300 uses
+ 16400 uses
+ 16500 uses
+ 16600 uses
+ 16700 uses
+ 16800 uses
+ 16900 uses
+ 17000 uses
+ 17100 uses
+ 17200 uses
+ 17300 uses
+ 17400 uses
+ 17500 uses
+ 17600 uses
+ 17700 uses
+ 17800 uses
+ 17900 uses
+ 18000 uses
+ 18100 uses
+ 18200 uses
+ 18300 uses
+ 18400 uses
+ 18500 uses
+ 18600 uses
+ 18700 uses
+ 18800 uses
+ 18900 uses
+ 19000 uses
+ 19100 uses
+ 19200 uses
+ 19300 uses
+ 19400 uses
+ 19500 uses
+ 19600 uses
+ 19700 uses
+ 19800 uses
+ 19900 uses
+ 20000 uses
+ 20100 uses
+ 20200 uses
+ 20300 uses
+ 20400 uses
+ 20500 uses
+ 20600 uses
+ 20700 uses
+ 20800 uses
+ 20900 uses
+ 21000 uses
+ 21100 uses
+ 21200 uses
+ 21300 uses
+ 21400 uses
+ 21500 uses
+ 21600 uses
+ 21700 uses
+ 21800 uses
+ 21900 uses
+ 22000 uses
+ 22100 uses
+ 22200 uses
+ 22300 uses
+ 22400 uses
+ 22500 uses
+ 22600 uses
+ 22700 uses
+ 22800 uses
+ 22900 uses
+ 23000 uses
+ 23100 uses
+ 23200 uses
+ 23300 uses
+ 23400 uses
+ 23500 uses
+ 23600 uses
+ 23700 uses
+ 23800 uses
+ 23900 uses
+ 24000 uses
+ 24100 uses
+ 24200 uses
+ 24300 uses
+ 24400 uses
+ 24500 uses
+ 24600 uses
+ 24700 uses
+ 24800 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc)
+[INFO]: Saving mag view with DRC errors(/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index b4c0380..1496967 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -191,19 +191,19 @@
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/glbl_cfg/runs/glbl_cfg/results/klayout/glbl_cfg.lyp
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/config.tcl
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic_spice.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/opt.lib
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/trimmed.lib
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/tracks_copy.info
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/synthesis/hierarchy.dot
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/synthesis/yosys.sdc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/16-fastroute.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/18-tritonRoute.param
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/18-tritonRoute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/13-fastroute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/16-tritonRoute.param
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/routing/16-tritonRoute.guide
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/clk_skew_adjust.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__mux2_1.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__fill_2.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__decap_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__diode_2.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__decap_12.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__decap_3.ext
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/tmp/magic/sky130_fd_sc_hd__tapvpwrvgnd_1.ext
@@ -216,28 +216,25 @@
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/runtime_summary_report.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/manufacturability_report.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/1-yosys_4.chk.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/2-opensta.min_max.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/1-yosys_pre.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/2-opensta_tns.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/1-yosys_dff.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/21-opensta_spef.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/2-opensta_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/2-opensta.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/21-opensta_spef_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/21-opensta_spef.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/2-opensta.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/21-opensta_spef.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/21-opensta_spef_tns.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/synthesis/1-yosys_4.stat.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/routing/39-antenna.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/floorplan/3-verilog2def.die_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/floorplan/3-verilog2def.core_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/33-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/37-klayout.magic.lydrc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/31-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/routing/36-antenna.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/floorplan/2-verilog2def.core_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/floorplan/2-verilog2def.die_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/30-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/28-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/klayout/34-klayout.magic.lydrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/placement/8-openphysyn_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/placement/8-openphysyn_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/placement/8-openphysyn_allchecks.rpt
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/synthesis/clk_skew_adjust.synthesis_preroute.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/synthesis/clk_skew_adjust.synthesis_diodes.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/synthesis/clk_skew_adjust.synthesis_optimized.v
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/synthesis/clk_skew_adjust.synthesis.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/cvc/cvc_clk_skew_adjust.error
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/cvc/cvc_clk_skew_adjust.debug
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/cvc/clk_skew_adjust.cdl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/cvc/clk_skew_adjust.power
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/routing/clk_skew_adjust.spef
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/routing/clk_skew_adjust.def.ref
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/magic/.magicrc
@@ -245,8 +242,6 @@
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/lvs/clk_skew_adjust.lvs.powered.v
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/lvs/clk_skew_adjust.lvs.lef.json
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/klayout/clk_skew_adjust.lyp
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/logs/synthesis/2-opensta
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/clk_skew_adjust/runs/clk_skew_adjust/logs/synthesis/21-opensta_spef
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/config.tcl
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/tmp/magic_spice.tcl
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/tmp/opt.lib
@@ -342,6 +337,198 @@
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/logs/synthesis/2-opensta
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/logs/synthesis/26-opensta_spef
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/wb_host/runs/wb_host/logs/synthesis/11-opensta_post_openphysyn
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic_spice.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/opt.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/trimmed.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/tracks_copy.info
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/synthesis/hierarchy.dot
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/synthesis/yosys.sdc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/routing/23-tritonRoute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/routing/23-tritonRoute.param
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/routing/21-fastroute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__inv_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__conb_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__nor2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__and2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a21oi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__fill_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a32o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__or2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__clkbuf_16.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__decap_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__diode_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__buf_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__buf_8.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__nand2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a211o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a21o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a21boi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__buf_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__or3_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__decap_12.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a2bb2o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__and4_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/uart_core.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__decap_3.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__o21ai_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a22oi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__dfrtp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__dfxtp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__tapvpwrvgnd_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a2111o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__fill_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__clkbuf_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__decap_6.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__or4_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__a21bo_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__decap_8.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__inv_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__o21a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__o22a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__and3_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/magic/sky130_fd_sc_hd__dfstp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/tmp/lvs/setup_file.lef.lvs
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/runtime_summary_report.rpt.parsable
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/runtime_summary_report.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/manufacturability_report.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/26-opensta_spef_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/1-yosys_4.chk.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/26-opensta_spef.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/26-opensta_spef_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/2-opensta.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/1-yosys_pre.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/2-opensta_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/11-opensta_post_openphysyn.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/11-opensta_post_openphysyn_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/1-yosys_dff.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/11-opensta_post_openphysyn.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/11-opensta_post_openphysyn.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/2-opensta_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/2-opensta.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/26-opensta_spef.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/2-opensta.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/26-opensta_spef.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/11-opensta_post_openphysyn_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/synthesis/1-yosys_4.stat.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/routing/44-antenna.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/floorplan/3-verilog2def.die_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/floorplan/3-verilog2def.core_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/klayout/36-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/klayout/38-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/klayout/42-klayout.magic.lydrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/placement/9-openphysyn_allchecks.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/placement/9-openphysyn_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/reports/placement/9-openphysyn_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/synthesis/uart_core.synthesis_cts.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/synthesis/uart_core.synthesis.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/synthesis/uart_core.synthesis_diodes.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/synthesis/uart_core.synthesis_optimized.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/synthesis/uart_core.synthesis_preroute.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/routing/uart_core.def.ref
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/routing/uart_core.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/magic/.magicrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/magic/uart_core.gds.lydrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/lvs/uart_core.lvs.lef.json
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/lvs/uart_core.lvs.powered.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/uart/runs/uart/results/klayout/uart_core.lyp
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic_spice.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/opt.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/trimmed.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/tracks_copy.info
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/synthesis/hierarchy.dot
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/synthesis/yosys.sdc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/routing/21-tritonRoute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/routing/17-fastroute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/routing/21-tritonRoute.param
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/routing/18-fastroute_2.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__conb_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__nor2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__and2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a21oi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__fill_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a32o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__or2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__clkbuf_16.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__decap_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__diode_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__nand2_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a211o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a21o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a21boi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__buf_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__or3_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__decap_12.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a2bb2o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__and4_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__decap_3.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__o21ai_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/spim_top.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a22oi_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__dfrtp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__dfxtp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__tapvpwrvgnd_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a2111o_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__o41a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__fill_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__clkbuf_1.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__o32a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__decap_6.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__or4_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__a21bo_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__decap_8.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__inv_2.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__o21a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__o22a_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__and3_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/magic/sky130_fd_sc_hd__dfstp_4.ext
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/tmp/lvs/setup_file.lef.lvs
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/runtime_summary_report.rpt.parsable
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/runtime_summary_report.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/manufacturability_report.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/1-yosys_4.chk.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/24-opensta_spef.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/2-opensta.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/1-yosys_pre.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/2-opensta_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/11-opensta_post_openphysyn.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/11-opensta_post_openphysyn_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/1-yosys_dff.stat
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/24-opensta_spef.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/11-opensta_post_openphysyn.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/11-opensta_post_openphysyn.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/2-opensta_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/2-opensta.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/2-opensta.timing.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/24-opensta_spef_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/24-opensta_spef_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/11-opensta_post_openphysyn_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/24-opensta_spef.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/synthesis/1-yosys_4.stat.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/routing/42-antenna.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/floorplan/3-verilog2def.die_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/floorplan/3-verilog2def.core_area.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/klayout/36-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/klayout/34-klayout.xor.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/klayout/40-klayout.magic.lydrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/placement/9-openphysyn_allchecks.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/placement/9-openphysyn_tns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/placement/9-openphysyn_wns.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/reports/placement/9-openphysyn_violators.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/synthesis/spim_top.synthesis_optimized.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/synthesis/spim_top.synthesis_preroute.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/synthesis/spim_top.synthesis.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/synthesis/spim_top.synthesis_cts.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/routing/spim_top.def.ref
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/routing/spim_top.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/magic/.magicrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/magic/spim_top.gds.lydrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/lvs/spim_top.lvs.powered.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/lvs/spim_top.lvs.lef.json
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/spi_master/runs/spi_master/results/klayout/spim_top.lyp
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/config.tcl
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/magic_spice.tcl
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/opt.lib
@@ -500,6 +687,7 @@
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.powered.v
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.lef.json
/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/klayout/sdrc_top.lyp
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/model/s25fl256s.sv
/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md
/home/dinesha/workarea/opencore/git/yifive_r0/work/_info
/home/dinesha/workarea/opencore/git/yifive_r0/work/_vmake
diff --git a/checks/user_project_wrapper.magic.drc b/checks/user_project_wrapper.magic.drc
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/checks/user_project_wrapper.magic.drc
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/checks/user_project_wrapper.xor.gds.png b/checks/user_project_wrapper.xor.gds.png
new file mode 100644
index 0000000..cd63482
--- /dev/null
+++ b/checks/user_project_wrapper.xor.gds.png
Binary files differ
diff --git a/checks/user_project_wrapper.xor.xml b/checks/user_project_wrapper.xor.xml
new file mode 100644
index 0000000..ad44b6d
--- /dev/null
+++ b/checks/user_project_wrapper.xor.xml
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>XOR /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty_erased.gds vs. /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/xor_checks/xor.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>235/4</name>
+ <description>XOR results for layer 235/4 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>69/20</name>
+ <description>XOR results for layer 69/20 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>70/20</name>
+ <description>XOR results for layer 70/20 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>71/20</name>
+ <description>XOR results for layer 71/20 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>71/44</name>
+ <description>XOR results for layer 71/44 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>72/20</name>
+ <description>XOR results for layer 72/20 </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>81/14</name>
+ <description>XOR results for layer 81/14 </description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/checks/xor.log b/checks/xor.log
new file mode 100644
index 0000000..73bb66b
--- /dev/null
+++ b/checks/xor.log
@@ -0,0 +1,68 @@
+First Layout: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty_erased.gds
+Second Layout: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds
+Design Name: xor_target
+Output GDS will be: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.xor.gds
+Reading /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_empty_erased.gds ..
+Reading /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper_erased.gds ..
+--- Running XOR for 69/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+--- Running XOR for 70/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+--- Running XOR for 71/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.010s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.000s
+--- Running XOR for 71/44 ---
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.010s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.000s
+--- Running XOR for 72/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.010s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+--- Running XOR for 81/14 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+Writing layout file: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.xor.gds ..
+Total run time: 0.140s
diff --git a/checks/xor_total.txt b/checks/xor_total.txt
new file mode 100644
index 0000000..05b29a4
--- /dev/null
+++ b/checks/xor_total.txt
@@ -0,0 +1 @@
+Total XOR differences = 0
\ No newline at end of file
diff --git a/openlane/clk_skew_adjust/config.tcl b/openlane/clk_skew_adjust/config.tcl
index 0c507cc..d1b3e25 100644
--- a/openlane/clk_skew_adjust/config.tcl
+++ b/openlane/clk_skew_adjust/config.tcl
@@ -12,9 +12,11 @@
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-# Base Configurations. Don't Touch
-# section begin
+# Global
+# ------
+
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) clk_skew_adjust
@@ -27,7 +29,6 @@
#
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) "0"
-set ::env(SYNTH_READ_BLACKBOX_LIB) "1"
## Source Verilog Files
@@ -35,55 +36,31 @@
$script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv"
## Clock configurations
-set ::env(CLOCK_PORT) "clk_in"
+#set ::env(CLOCK_PORT) "clk_in"
-set ::env(CLOCK_PERIOD) "10"
+#set ::env(CLOCK_PERIOD) "10"
## Internal Macros
### Macro Placement
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 50 50"
-set ::env(PL_TARGET_DENSITY) 0.85
-set ::env(FP_CORE_UTIL) "60"
-set ::env(FP_PDN_CHECK_NODES) 0
-set ::env(RUN_KLAYOUT_DRC) 0
set ::env(VDD_PIN) [list {vccd1}]
set ::env(GND_PIN) [list {vssd1}]
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-# No Synthesis and CTS
-set ::env(RUN_SIMPLE_CTS) 0
-set ::env(SYNTH_BUFFERING) 0
-set ::env(SYNTH_SIZING) 0
+# Fill this
set ::env(CLOCK_TREE_SYNTH) 0
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(FILL_INSERTION) 1
-set ::env(RUN_SIMPLE_CTS) 0
-set ::env(LVS_CONNECT_BY_LABEL) 1
+
set ::env(CELL_PAD) 0
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
+set ::env(BOTTOM_MARGIN_MULT) 2
+set ::env(TOP_MARGIN_MULT) 2
set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index aa200dd..350ae31 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -36,13 +36,12 @@
set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
-set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
-set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_sel_i*]
-set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
@@ -57,7 +56,7 @@
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfmax*]
set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_o*]
-set_output_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
######################################
@@ -69,7 +68,36 @@
puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
+#set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[29]] Masked SDRAM clock
set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
################################################
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index fa507c1..cd78ed8 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc
@@ -37,27 +37,27 @@
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi0*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi1*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi2*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi3*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[5]]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[4]]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[3]]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[2]]
set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port events_o*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_clk*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn0*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn1*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn3*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_mode*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo0*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo1*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo2*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo3*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_en_tx*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_debug*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[1]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[0]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[5]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[4]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[3]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[2]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[1]]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[0]]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 45d0586..7c87b91 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -37,7 +37,9 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/spi_master/src/spim_top.sv \
+ $script_dir/../../verilog/rtl/spi_master/src/spim_if.sv \
$script_dir/../../verilog/rtl/spi_master/src/spim_regs.sv \
+ $script_dir/../../verilog/rtl/spi_master/src/spim_fifo.sv \
$script_dir/../../verilog/rtl/spi_master/src/spim_clkgen.sv \
$script_dir/../../verilog/rtl/spi_master/src/spim_ctrl.sv \
$script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index 6d3c721..2413319 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -3,9 +3,39 @@
#W
mclk 0000 0
-rst_n 0000 1
-events_o\[1\] 0000 2
-events_o\[0\] 0000 3
+rst_n
+spi_debug\[31\]
+spi_debug\[30\]
+spi_debug\[29\]
+spi_debug\[28\]
+spi_debug\[27\]
+spi_debug\[26\]
+spi_debug\[25\]
+spi_debug\[24\]
+spi_debug\[23\]
+spi_debug\[22\]
+spi_debug\[21\]
+spi_debug\[20\]
+spi_debug\[19\]
+spi_debug\[18\]
+spi_debug\[17\]
+spi_debug\[16\]
+spi_debug\[15\]
+spi_debug\[14\]
+spi_debug\[13\]
+spi_debug\[12\]
+spi_debug\[11\]
+spi_debug\[10\]
+spi_debug\[9\]
+spi_debug\[8\]
+spi_debug\[7\]
+spi_debug\[6\]
+spi_debug\[5\]
+spi_debug\[4\]
+spi_debug\[3\]
+spi_debug\[2\]
+spi_debug\[1\]
+spi_debug\[0\]
#N
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 51dc0f8..f51d3d1 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -34,7 +34,6 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/digital_core/src/digital_core.sv \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
@@ -114,7 +113,7 @@
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
-set ::env(MAGIC_EXT_USE_GDS) "1"
+#set ::env(MAGIC_EXT_USE_GDS) "1"
set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 2843978..c5044dc 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,17 +1,17 @@
-u_core.u_spi_master 300 2700 N
-u_core.u_sdram_ctrl 1000 2700 N
-u_core.u_glbl_cfg 2000 2700 N
-u_core.u_riscv_top 500 800 N
-u_core.u_uart_core 2200 1600 N
-u_core.u_intercon 300 2300 N
-u_core.u_wb_host 300 300 N
-u_core.u_skew_wi 2600 2300 N
-u_core.u_skew_riscv 400 800 N
-u_core.u_skew_uart 2200 1500 N
-u_core.u_skew_spi 200 2700 E
-u_core.u_skew_sdram 900 2700 E
-u_core.u_skew_glbl 2000 3200 N
-u_core.u_skew_wh 1400 300 N
-u_core.u_skew_sd_co 950 3300 N
-u_core.u_skew_sd_ci 1100 3300 N
-u_core.u_skew_sp_co 300 3400 N
+u_spi_master 300 2700 N
+u_sdram_ctrl 1000 2700 N
+u_glbl_cfg 2000 2700 N
+u_riscv_top 500 800 N
+u_uart_core 2200 1600 N
+u_intercon 300 2300 N
+u_wb_host 300 300 N
+u_skew_wi 2600 2300 N
+u_skew_riscv 400 800 N
+u_skew_uart 2200 1500 N
+u_skew_spi 200 2700 E
+u_skew_sdram 900 2700 E
+u_skew_glbl 2000 3200 N
+u_skew_wh 1400 300 N
+u_skew_sd_co 950 3300 N
+u_skew_sd_ci 1100 3300 N
+u_skew_sp_co 300 3400 N
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
index 3d2887c..61ff946 100644
--- a/signoff/clk_skew_adjust/final_summary_report.csv
+++ b/signoff/clk_skew_adjust/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m8s,0h0m33s,20000.0,0.0025,12000.0,28,387.16,30,0,0,0,0,0,0,0,0,0,-1,0,389,195,-2.16,-2.16,-2.16,-2.16,-2.03,-2.16,-2.16,-2.16,-2.16,-2.03,237416,0.0,3.57,4.52,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,20,12,0,32,83.1255195344971,12.03,10,AREA 0,5,60,1,153.6,153.18,0.85,0,sky130_fd_sc_hd,0,4
+0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m6s,0h0m30s,64878.892733564026,0.0011560000000000001,25951.55709342561,51,384.71,30,0,0,0,0,0,0,0,0,0,0,0,677,212,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,12.65,11.49,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,16,5,0,21,90.9090909090909,11,10,AREA 0,5,40,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,0,3
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index e90cae1..390656f 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m41s,0h5m12s,40668.57142857143,0.35,20334.285714285714,27,639.77,7117,0,0,0,0,0,0,0,15,0,-1,0,302912,50760,-3.59,-3.59,-3.59,-3.59,-4.18,-3.59,-3.59,-3.59,-3.59,-4.18,239724191,0.0,20.25,16.33,1.79,-1,-1,7052,7280,1239,1467,0,0,0,7117,197,107,81,102,354,212,31,2263,1256,1154,27,350,4248,0,4598,70.52186177715092,14.18,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m28s,0h4m15s,40668.57142857143,0.35,20334.285714285714,27,639.29,7117,0,0,0,0,0,0,0,15,0,-1,0,302912,50760,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,239724191,0.0,20.25,16.33,1.79,-1,-1,7052,7280,1239,1467,0,0,0,7117,197,107,81,102,354,212,31,2263,1256,1154,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index e0a826c..7ecde4c 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h8m3s,0h5m35s,25416.66666666667,0.24,12708.333333333336,19,591.97,3050,0,0,0,0,0,0,0,5,0,-1,0,162786,26689,-1.48,-1.48,-1.55,-1.55,-2.28,-86.69,-86.69,-158.7,-158.7,-255.68,121954058,0.0,9.59,19.86,0.04,-1,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,81.43322475570034,12.28,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m38s,0h3m39s,45283.33333333334,0.24,22641.66666666667,33,605.61,5434,0,0,0,0,0,0,0,1,5,-1,0,248271,41053,-0.54,-0.54,-0.42,-0.42,-0.39,-0.98,-0.98,-0.94,-0.94,-0.89,196972893,0.0,18.06,28.16,0.23,-1,-1,5370,5512,872,1014,0,0,0,5434,217,0,185,97,764,130,35,1615,982,919,24,424,2889,0,3313,96.24639076034649,10.39,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index e37c172..e9d8ff5 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h6m30s,0h4m1s,46133.33333333334,0.12,23066.66666666667,35,545.72,2768,0,0,0,0,0,0,0,1,0,-1,0,91647,20662,-0.67,-0.67,-0.47,-0.47,-0.73,-37.32,-37.32,-45.39,-45.39,-68.63,62910936,0.0,19.11,18.79,0.06,-1,-1,2767,2787,454,474,0,0,0,2768,59,0,30,41,182,125,26,685,435,396,17,278,1410,0,1688,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m4s,0h3m18s,46133.33333333334,0.12,23066.66666666667,35,545.71,2768,0,0,0,0,0,0,0,1,0,-1,0,91647,20662,-0.67,-0.67,-0.47,-0.47,-0.73,-37.32,-37.32,-45.39,-45.39,-68.63,62910936,0.0,19.11,18.79,0.06,-1,-1,2767,2787,454,474,0,0,0,2768,59,0,30,41,182,125,26,685,435,396,17,278,1410,0,1688,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index d2284fa..a4e190b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m41s,0h5m14s,3.3079078455790785,10.2784,1.6539539227895392,0,577.98,17,0,0,0,0,0,0,0,0,28,-1,-1,1297769,6216,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.22,3.66,1.51,1.63,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m41s,0h5m47s,3.3079078455790785,10.2784,1.6539539227895392,0,580.84,17,0,0,0,0,0,0,0,0,30,-1,-1,1296299,5489,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.61,3.74,0.82,1.49,-1,884,1502,853,1471,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 7565689..be336b3 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h10m23s,0h7m30s,30760.0,0.2,15380.0,25,615.57,3076,0,0,0,0,0,0,0,1,0,-1,0,327997,31894,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,274634123,0.0,48.31,13.11,27.06,-1,-1,2798,3440,464,1106,0,0,0,3076,83,0,5,14,30,26,9,783,597,752,15,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h7m6s,0h4m32s,30340.0,0.2,15170.0,25,618.03,3034,0,0,0,0,0,0,0,3,0,-1,0,323344,30030,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,276033708,0.0,49.92,13.67,23.25,-1,-1,2756,3398,457,1099,0,0,0,3034,78,0,3,11,37,27,10,770,589,744,14,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 7923d4a..db261ec 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart user_spi
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/model/s25fl256s.sv b/verilog/dv/model/s25fl256s.sv
new file mode 100644
index 0000000..748f037
--- /dev/null
+++ b/verilog/dv/model/s25fl256s.sv
@@ -0,0 +1,8183 @@
+///////////////////////////////////////////////////////////////////////////////
+// File name : s25fl256s.v
+///////////////////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2012 Spansion, LLC.
+//
+// MODIFICATION HISTORY :
+//
+// version: | author: | mod date: | changes made:
+// V1.0 V.Mancev 19 Nov 09 Initial
+// R.Prokopovic
+// V1.1 V.Mancev 04 Mar 10 addr_cnt for second read in
+// high performance read continuous
+// mode can change its value only
+// when CSNeg = '0'
+// V1.2 V.Mancev 23 Mar 10 During read operations read_out
+// signal changes its value in
+// shorter interval
+// V1.3 V.Mancev 12 Apr 10 HOLD mode corrected
+// Condition for PP operation
+// corrected
+// V1.4 V.Mancev 20 May 10 SRWD bit assignment is corrected
+// Condition for WRR command in
+// write_cycle _decode section is
+// corrected
+// Blocking assignments for signals
+// WSTART and PSTART are replaced
+// with nonblocking assignments
+// Conditions in Page Program
+// section are fixed
+// V1.5 V.Mancev 25 May 10 Conditions in programming
+// sections are fixed
+// Timing control sections for
+// Program and Erase operation are
+// changed
+// V1.6 V.Mancev 03 June 10 bus_cycle_state section for
+// PGSP command is fixed
+// V1.7 V.Mancev 28 July 10 During the QUAD mode HOLD# input
+// is not monitored for its normal
+// function
+// write cycle decode section is
+// changed
+// V1.8 B.Colakovic 24 Aug 10 All redundant signals are removed
+// from BusCycle process
+// V1.9 V.Mancev 30 Sep 10 Latest datasheet aligned
+// B.Colakovic
+//
+// V2.0 V.Mancev 05 Nov 10 Hybrid configuration added
+//
+// V2.1 V.Mancev 12 Nov 10 QUAD Program operation during Erase
+// Suspend is added
+// Warning for Resume to Suspend time
+// is added
+// During Erase Suspend, after Program
+// operation is completed, WEL bit is
+// cleared
+// Implemetation of Software Reset is
+// Changed
+// V2.2 S.Petrovic 18 Apr 11 Corrected timing in always block
+// that generates rising_edge_CSNeg_ipd
+// V2.3 B.Colakovic 05 July 11 Latest datasheet aligned
+// V2.4 B.Colakovic 14 July 11 Optimization issue is fixed
+// V2.5 V.Mancev 19 July 11 Timing check issue is fixed
+// V2.6 V. Mancev 18 Nov 11 Time tHO is changed to 1 ns
+// (customer's request)
+// BRWR instruction is corrected
+// V2.7 S.Petrovic 28 Aug 12 QPP Instruction is allowed on
+// previously programmed page
+// V2.8 V. Mancev 13 Feb 13 Reverted restriction for QPP
+// on programmed page and
+// added clearing with sector erase
+// V2.9 S.Petrovic 13 Nov 28 Corrected FSM state transition
+// started on Power-Up and HW
+// Reset in StateGen process
+// V2.10 V. Mancev 13 Dec 20 Corrected DLP read
+// V2.11 M.Stojanovic 15 May 15 Ignored upper address bits for RD4
+// V2.12 M.Stojanovic 15 May 29 Ignored upper address bits for all
+// commands in QUAD mode
+// V2.13 M.Stojanovic 16 May 11 During QPP and QPP4 commands
+// the same page must not be
+// programmed more than once. However
+// do not generate P_ERR if this
+// occurs.
+// V2.14 M.Krneta 19 May 07 Updated according to the rev *P
+// (QPP and QPP4 commands changed,
+// ECCRD command added,
+// LOCK bit removed)
+// V2.15 B.Barac 20 Jan 24 Bug 49 fixed, issue with not assigning
+// sector in commands P4E4 and P4E
+//
+///////////////////////////////////////////////////////////////////////////////
+// PART DESCRIPTION:
+//
+// Library: FLASH
+// Technology: FLASH MEMORY
+// Part: S25FL256S
+//
+// Description: 256 Megabit Serial Flash Memory
+//
+//////////////////////////////////////////////////////////////////////////////
+// Comments :
+// For correct simulation, simulator resolution should be set to 1 ps
+// A device ordering (trim) option determines whether a feature is enabled
+// or not, or provide relevant parameters:
+// -15th character in TimingModel determines if enhanced high
+// performance option is available
+// (0,2,3,R,A,B,C,D) EHPLC
+// (Y,Z,S,T,K,L) Security EHPLC
+// (4,6,7,8,9,Q) HPLC
+// -15th character in TimingModel determines if RESET# input
+// is available
+// (R,A,B,C,D,Q.6,7,K,L,S,T,M,N,U,V) RESET# is available
+// (0,2,3,4,8,9,Y.Z.W,X) RESET# is tied to the inactive
+// state,inside the package.
+// -16th character in TimingModel determines Sector and Page Size:
+// (0) Sector Size = 64 kB; Page Size = 256 bytes
+// Hybrid Top/Bottom sector size architecture
+// (1) Sector Size = 256 kB; Page Size = 512 bytes
+// Uniform sector size architecture
+//////////////////////////////////////////////////////////////////////////////
+// Known Bugs:
+//
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// MODULE DECLARATION //
+//////////////////////////////////////////////////////////////////////////////
+`timescale 1 ps/1 ps
+
+module s25fl256s
+ (
+ // Data Inputs/Outputs
+ SI ,
+ SO ,
+ // Controls
+ SCK ,
+ CSNeg ,
+ RSTNeg ,
+ WPNeg ,
+ HOLDNeg
+
+);
+
+///////////////////////////////////////////////////////////////////////////////
+// Port / Part Pin Declarations
+///////////////////////////////////////////////////////////////////////////////
+
+ inout SI ;
+ inout SO ;
+
+ input SCK ;
+ input CSNeg ;
+ input RSTNeg ;
+ inout HOLDNeg ;
+ inout WPNeg ;
+
+ // interconnect path delay signals
+ wire SCK_ipd ;
+ wire SI_ipd ;
+ wire SO_ipd ;
+
+ wire SI_in ;
+ assign SI_in = SI_ipd ;
+
+ wire SI_out ;
+ assign SI_out = SI ;
+
+ wire SO_in ;
+ assign SO_in = SO_ipd ;
+
+ wire SO_out ;
+ assign SO_out = SO ;
+
+ wire CSNeg_ipd ;
+ wire HOLDNeg_ipd ;
+ wire WPNeg_ipd ;
+ wire RSTNeg_ipd ;
+
+ wire HOLDNeg_in ;
+ //Internal pull-up
+ assign HOLDNeg_in = (HOLDNeg_ipd === 1'bx) ? 1'b1 : HOLDNeg_ipd;
+
+ wire HOLDNeg_out ;
+ assign HOLDNeg_out = HOLDNeg ;
+
+ wire WPNeg_in ;
+ //Internal pull-up
+ assign WPNeg_in = (WPNeg_ipd === 1'bx) ? 1'b1 : WPNeg_ipd;
+
+ wire WPNeg_out ;
+ assign WPNeg_out = WPNeg ;
+
+ wire RSTNeg_in ;
+ //Internal pull-up
+ assign RSTNeg_in = (RSTNeg_ipd === 1'bx) ? 1'b1 : RSTNeg_ipd;
+
+ // internal delays
+ reg PP_in ;
+ reg PP_out ;
+ reg BP_in ;
+ reg BP_out ;
+ reg SE_in ;
+ reg SE_out ;
+ reg BE_in ;
+ reg BE_out ;
+ reg WRR_in ;
+ reg WRR_out ;
+ reg ERSSUSP_in ;
+ reg ERSSUSP_out ;
+ reg PRGSUSP_in ;
+ reg PRGSUSP_out ;
+ reg PU_in ;
+ reg PU_out ;
+ reg RST_in ;
+ reg RST_out ;
+ reg PPBERASE_in ;
+ reg PPBERASE_out;
+ reg PASSULCK_in ;
+ reg PASSULCK_out;
+ reg PASSACC_in ;
+ reg PASSACC_out;
+
+ // event control registers
+ reg PRGSUSP_out_event;
+ reg ERSSUSP_out_event;
+ reg Reseted_event;
+ reg SCK_ipd_event;
+ reg next_state_event;
+
+ reg rising_edge_PoweredUp;
+ reg rising_edge_Reseted;
+ reg rising_edge_PASSULCK_in;
+ reg rising_edge_RES_out;
+ reg rising_edge_PSTART;
+ reg rising_edge_WSTART;
+ reg rising_edge_ESTART;
+ reg rising_edge_RSTNeg;
+ reg rising_edge_RST;
+ reg falling_edge_RSTNeg;
+ reg falling_edge_RST;
+ reg rising_edge_RST_out;
+ reg rising_edge_CSNeg_ipd = 1'b0;
+ reg falling_edge_CSNeg_ipd = 1'b0;
+ reg rising_edge_SCK_ipd = 1'b0;
+ reg falling_edge_SCK_ipd = 1'b0;
+
+ reg RST ;
+
+ reg SOut_zd = 1'bZ ;
+ reg SOut_z = 1'bZ ;
+
+ wire SI_z ;
+ wire SO_z ;
+
+ reg SIOut_zd = 1'bZ ;
+ reg SIOut_z = 1'bZ ;
+
+ reg WPNegOut_zd = 1'bZ ;
+ reg HOLDNegOut_zd = 1'bZ ;
+
+ assign SI_z = SIOut_z;
+ assign SO_z = SOut_z;
+
+ parameter UserPreload = 1;
+ parameter mem_file_name = "none";//"s25fl256s.mem";
+ parameter otp_file_name = "s25fl256sOTP.mem";//"none";
+
+ parameter TimingModel = "DefaultTimingModel";
+
+ parameter PartID = "s25fl256s";
+ parameter MaxData = 255;
+ parameter MemSize = 28'h1FFFFFF;
+ parameter SecSize256 = 20'h3FFFF;
+ parameter SecSize64 = 16'hFFFF;
+ parameter SecSize4 = 12'hFFF;
+ parameter SecNum64 = 541;
+ parameter SecNum256 = 127;
+ parameter PageNum64 = 20'h3FFFF;
+ parameter PageNum256 = 16'hFFFF;
+ parameter AddrRANGE = 28'h1FFFFFF;
+ parameter HiAddrBit = 31;
+ parameter OTPSize = 1023;
+ parameter OTPLoAddr = 12'h000;
+ parameter OTPHiAddr = 12'h3FF;
+ parameter BYTE = 8;
+
+ // Manufacturer Identification
+ parameter Manuf_ID = 8'h01;
+ parameter DeviceID = 8'h18;
+ // Electronic Signature
+ parameter ESignature = 8'h18;
+ // Device ID
+ //Manufacturer Identification && Memory Type && Memory Capacity
+ parameter Jedec_ID = 8'h01;
+ parameter DeviceID1 = 8'h02;
+ parameter DeviceID2 = 8'h19;
+ parameter ExtendedBytes = 8'h4D;
+ parameter ExtendedID64 = 8'h01;
+ parameter ExtendedID256 = 8'h00;
+ parameter DieRev = 8'h00;
+ parameter MaskRev = 8'h00;
+
+ integer PageSize;
+ integer PageNum;
+ integer SecSize;
+ integer b_act = 0;
+
+ integer ASP_ProtSE = 0;
+ integer Sec_ProtSE = 0;
+
+ integer EHP; //Enhanced High Performance Mode active
+
+ integer BAR_ACC = 0; //Bank Register Access active
+
+ //varaibles to resolve architecture used
+ reg [24*8-1:0] tmp_timing;//stores copy of TimingModel
+ reg [7:0] tmp_char1;//Define EHPLC or HPLC Mode
+ reg [7:0] tmp_char2;//stores "0" or "1" character defining sector/page size
+ integer found = 1'b0;
+
+ // If speedsimulation is needed uncomment following line
+
+ `define SPEEDSIM;
+
+ // powerup
+ reg PoweredUp;
+
+ // Memory Array Configuration
+ reg BottomBoot = 1'b0;
+ reg TopBoot = 1'b0;
+ reg UniformSec = 1'b0;
+
+ // FSM control signals
+ reg PDONE ;
+ reg PSTART ;
+ reg PGSUSP ;
+ reg PGRES ;
+
+ reg TSU ;
+
+ reg RES_TO_SUSP_MIN_TIME;
+ reg RES_TO_SUSP_TYP_TIME;
+
+ reg WDONE ;
+ reg WSTART ;
+
+ reg EDONE ;
+ reg ESTART ;
+ reg ESUSP ;
+ reg ERES ;
+
+ reg Reseted ;
+
+ reg PARAM_REGION = 1'b0;
+
+ // Lock Bit is enabled for customer programming
+ reg WRLOCKENABLE = 1'b1;
+ // Flag that mark if ASP Register is allready programmed
+ reg ASPOTPFLAG = 1'b0;
+
+ //Flag for Password unlock command
+ reg PASS_UNLOCKED = 1'b0;
+ reg [63:0] PASS_TEMP = 64'hFFFFFFFFFFFFFFFF;
+
+ reg QUADRD = 1'b0;
+ reg INITIAL_CONFIG = 1'b0;
+ reg CHECK_FREQ = 1'b0;
+
+ // Programming buffer
+ integer WByte[0:511];
+ // CFI array
+ integer CFI_array[8'h00:8'h50];
+ // OTP Memory Array
+ integer OTPMem[OTPLoAddr:OTPHiAddr];
+ // Flash Memory Array
+ integer Mem[0:AddrRANGE];
+
+ // Registers
+ // VDLR Register
+ reg[7:0] VDLR_reg = 8'h00;
+ reg[7:0] VDLR_reg_in = 8'h00;
+ // NVDLR Register
+ reg[7:0] NVDLR_reg = 8'h00;
+ reg[7:0] NVDLR_reg_in = 8'h00;
+ reg start_dlp = 1'b0;
+
+ // Status Register 1
+ reg[7:0] Status_reg1 = 8'h00;
+ reg[7:0] Status_reg1_in = 8'h00;
+
+ wire SRWD ;
+ wire P_ERR;
+ wire E_ERR;
+ wire [2:0]BP;
+ wire WEL;
+ wire WIP;
+ assign SRWD = Status_reg1[7];
+ assign P_ERR = Status_reg1[6];
+ assign E_ERR = Status_reg1[5];
+ assign BP = Status_reg1[4:2];
+ assign WEL = Status_reg1[1];
+ assign WIP = Status_reg1[0];
+
+ // Status Register 2
+ reg[7:0] Status_reg2 = 8'h00;
+ reg[7:0] Status_reg2_in = 8'h00;
+
+ wire ES ;
+ wire PS ;
+ assign ES = Status_reg2[1];
+ assign PS = Status_reg2[0];
+
+ // Configuration Register 1
+ reg[7:0] Config_reg1 = 8'h00;
+ reg[7:0] Config_reg1_in = 8'h00;
+
+ wire LC1 ;
+ wire LC0 ;
+ wire TBPROT ;
+// wire LOCK ;
+ wire BPNV ;
+ wire TBPARM ;
+ wire QUAD ;
+ wire FREEZE ;
+ assign LC1 = Config_reg1[7];
+ assign LC0 = Config_reg1[6];
+ assign TBPROT = Config_reg1[5];
+// assign LOCK = Config_reg1[4];
+ assign BPNV = Config_reg1[3];
+ assign TBPARM = Config_reg1[2];
+ assign QUAD = Config_reg1[1];
+ assign FREEZE = Config_reg1[0];
+
+ // Autoboot Register
+ reg[31:0] AutoBoot_reg = 32'h00000000;
+ reg[31:0] AutoBoot_reg_in = 32'h00000000;
+
+ wire ABE;
+ assign ABE = AutoBoot_reg[0];
+
+ // Bank Address Register
+ reg [7:0] Bank_Addr_reg = 8'h00;
+ reg [7:0] Bank_Addr_reg_in = 8'h00;
+
+ wire EXTADD;
+ wire BA24;
+
+ assign EXTADD = Bank_Addr_reg[7];
+ assign BA24 = Bank_Addr_reg[0];
+
+ // ECC Status Register
+ reg[7:0] ECCSR = 8'h00;
+
+ wire EECC;
+ wire EECCD;
+ wire ECCDI;
+
+ assign EECC = ECCSR[2];
+ assign EECCD = ECCSR[1];
+ assign ECCDI = ECCSR[0];
+
+ // ASP Register
+ reg[15:0] ASP_reg ;
+ reg[15:0] ASP_reg_in;
+
+ wire RPME ;
+ wire PPBOTP ;
+ wire PWDMLB ;
+ wire PSTMLB ;
+ assign RPME = ASP_reg[5];
+ assign PPBOTP = ASP_reg[3];
+ assign PWDMLB = ASP_reg[2];
+ assign PSTMLB = ASP_reg[1];
+
+ // Password register
+ reg[63:0] Password_reg = 64'hFFFFFFFFFFFFFFFF;
+ reg[63:0] Password_reg_in = 64'hFFFFFFFFFFFFFFFF;
+
+ // PPB Lock Register
+ reg[7:0] PPBL = 8'h00;
+ reg[7:0] PPBL_in = 8'h00;
+
+ wire PPB_LOCK ;
+ assign PPB_LOCK = PPBL[0];
+
+ // PPB Access Register
+ reg[7:0] PPBAR = 8'hFF;
+ reg[7:0] PPBAR_in = 8'hFF;
+
+ reg[SecNum64:0] PPB_bits = {542{1'b1}};
+
+ // DYB Access Register
+ reg[7:0] DYBAR = 8'hFF;
+ reg[7:0] DYBAR_in = 8'hFF;
+
+ reg[SecNum64:0] DYB_bits = {542{1'b1}};
+
+ //The Lock Protection Registers for OTP Memory space
+ reg[7:0] LOCK_BYTE1;
+ reg[7:0] LOCK_BYTE2;
+ reg[7:0] LOCK_BYTE3;
+ reg[7:0] LOCK_BYTE4;
+
+ // Command Register
+ reg write;
+ reg cfg_write;
+ reg read_out;
+ reg dual = 1'b0;
+ reg rd_fast = 1'b1;
+ reg rd_slow = 1'b0;
+ reg ddr = 1'b0;
+ reg ddr80 = 1'b0;
+ reg ddr_fast = 1'b0;
+ reg hold_mode = 1'b0;
+ reg any_read = 1'b0;
+ reg quad_pg = 1'b0;
+
+ wire rd ;
+ wire fast_rd ;
+ wire ddrd ;
+ wire fast_ddr ;
+ wire ddrd80 ;
+
+ wire quadpg ;
+ assign quadpg = quad_pg;
+
+ wire RD_EQU_1;
+ assign RD_EQU_1 = any_read;
+
+ wire RD_EQU_0;
+ assign RD_EQU_0 = ~any_read;
+
+ reg change_TBPARM = 0;
+
+ reg change_BP = 0;
+ reg [2:0] BP_bits = 3'b0;
+
+ reg DOUBLE = 1'b0; //Double Data Rate (DDR) flag
+
+ reg RdPswdProtMode = 1'b0;//Read Password Protection Mode Active flag
+ reg RdPswdProtEnable = 1'b0;//Read Password Protection Mode Support flag
+
+ integer Byte_number = 0;
+
+ reg oe = 1'b0;
+ reg oe_z = 1'b0;
+
+ reg [647:0] CFI_array_tmp ;
+ reg [7:0] CFI_tmp;
+
+ integer start_delay;
+ reg start_autoboot;
+ integer ABSD;
+
+ reg change_addr ;
+ integer Address = 0;
+ integer SectorSuspend = 0;
+
+ //Sector and subsector addresses
+ integer SA = 0;
+
+ // Sector is protect if Sec_Prot(SecNum) = '1'
+ reg [SecNum64:0] Sec_Prot = {542{1'b0}};
+
+ // timing check violation
+ reg Viol = 1'b0;
+
+ integer WOTPByte;
+ integer AddrLo;
+ integer AddrHi;
+
+ reg[7:0] old_bit, new_bit;
+ integer old_int, new_int;
+ reg[63:0] old_pass;
+ reg[63:0] new_pass;
+ integer wr_cnt;
+ integer cnt;
+
+ integer read_cnt = 0;
+ integer byte_cnt = 1;
+ integer read_addr = 0;
+ integer read_addr_tmp = 0;
+ integer Sec_addr = 0;
+ integer SecAddr = 0;
+ integer Page_addr = 0;
+ integer pgm_page = 0;
+
+ reg[7:0] data_out;
+ reg[647:0] ident_out;
+
+ time SCK_cycle = 0;
+ time prev_SCK;
+ time start_ddr;
+ time out_time;
+ time SCK_SO_DDR;
+///////////////////////////////////////////////////////////////////////////////
+//Interconnect Path Delay Section
+///////////////////////////////////////////////////////////////////////////////
+ buf (SCK_ipd, SCK);
+ buf (SI_ipd, SI);
+
+ buf (SO_ipd, SO);
+ buf (CSNeg_ipd, CSNeg);
+ buf (HOLDNeg_ipd, HOLDNeg);
+ buf (WPNeg_ipd, WPNeg);
+ buf (RSTNeg_ipd, RSTNeg);
+
+///////////////////////////////////////////////////////////////////////////////
+// Propagation delay Section
+///////////////////////////////////////////////////////////////////////////////
+ nmos (SI, SI_z , 1);
+
+ nmos (SO, SO_z , 1);
+ nmos (HOLDNeg, HOLDNegOut_zd , 1);
+ nmos (WPNeg, WPNegOut_zd , 1);
+
+ wire deg_pin;
+ wire deg_sin;
+ wire deg_holdin;
+ wire deh_pin;
+ wire deh_sout;
+ wire deh_ddr_sout;
+ wire deh_holdin;
+ //VHDL VITAL CheckEnable equivalents
+ wire quad_rd;
+ assign quad_rd = deg_holdin && ~QUAD && (SIOut_z != 1'bz);
+ wire wr_prot;
+ assign wr_prot = SRWD && WEL && ~QUAD;
+ wire dual_rd;
+ assign dual_rd = dual ;
+ wire ddro;
+ assign ddro = ddr && ~ddr80 && ~dual ;
+ wire ddro80;
+ assign ddro80 = ddr && ddr80 && ~dual ;
+ wire ddr_rd;
+ assign ddr_rd = PoweredUp && ddr;
+ wire sdr_rd;
+ assign sdr_rd = PoweredUp && ~ddr;
+
+specify
+ // tipd delays: interconnect path delays , mapped to input port delays.
+ // In Verilog is not necessary to declare any tipd_ delay variables,
+ // they can be taken from SDF file
+ // With all the other delays real delays would be taken from SDF file
+
+ // tpd delays
+ specparam tpd_SCK_SO_normal =1;
+ specparam tpd_CSNeg_SO =1;
+ specparam tpd_HOLDNeg_SO =1;
+ specparam tpd_RSTNeg_SO =1;
+ //DDR operation values
+ specparam tpd_SCK_SO_DDR =1;
+
+ //tsetup values: setup times
+ specparam tsetup_CSNeg_SCK =1;
+ specparam tsetup_SI_SCK_normal =1;
+ specparam tsetup_WPNeg_CSNeg =1;
+ specparam tsetup_HOLDNeg_SCK =1;
+ specparam tsetup_RSTNeg_CSNeg =1;
+ // DDR operation values
+ specparam tsetup_SI_SCK_DDR =1;
+ specparam tsetup_SI_SCK_DDR_fast =1;
+ specparam tsetup_CSNeg_SCK_DDR =1;
+
+ //thold values: hold times
+ specparam thold_CSNeg_SCK =1;
+ specparam thold_SI_SCK_normal =1;
+ specparam thold_SO_SCK_normal =1;
+ specparam thold_WPNeg_CSNeg =1;
+ specparam thold_HOLDNeg_SCK =1;
+ specparam thold_CSNeg_RSTNeg =1;
+ // DDR operation values
+ specparam thold_SI_SCK_DDR =1;
+ specparam thold_SI_SCK_DDR_fast =1;
+ specparam thold_CSNeg_SCK_DDR =1;
+
+ // tpw values: pulse width
+ specparam tpw_SCK_serial_posedge =1;
+ specparam tpw_SCK_dual_posedge =1;
+ specparam tpw_SCK_fast_posedge =1;
+ specparam tpw_SCK_quadpg_posedge =1;
+ specparam tpw_SCK_serial_negedge =1;
+ specparam tpw_SCK_dual_negedge =1;
+ specparam tpw_SCK_fast_negedge =1;
+ specparam tpw_SCK_quadpg_negedge =1;
+ specparam tpw_CSNeg_read_posedge =1;
+ specparam tpw_CSNeg_pgers_posedge =1;
+ specparam tpw_RSTNeg_negedge =1;
+ specparam tpw_RSTNeg_posedge =1;
+ // DDR operation values
+ specparam tpw_SCK_DDR_posedge =1;
+ specparam tpw_SCK_DDR_negedge =1;
+ specparam tpw_SCK_DDR80_posedge =1;
+ specparam tpw_SCK_DDR80_negedge =1;
+
+ // tperiod min (calculated as 1/max freq)
+ specparam tperiod_SCK_serial_rd =1;// 50 MHz
+ specparam tperiod_SCK_fast_rd =1;//133 MHz
+ specparam tperiod_SCK_dual_rd =1;//104 MHz
+ specparam tperiod_SCK_quadpg =1;// 80 MHz
+ // DDR operation values
+ specparam tperiod_SCK_DDR_rd =1;// 66 MHz
+ specparam tperiod_SCK_DDR80_rd =1;// 80 MHz
+
+ `ifdef SPEEDSIM
+ // Page Program Operation
+ specparam tdevice_PP_256 = 75e7;//tPP
+ // Page Program Operation
+ specparam tdevice_PP_512 = 75e7;//tPP
+ // Typical Byte Programming Time
+ specparam tdevice_BP = 4e8;//tBP
+ // Sector Erase Operation
+ specparam tdevice_SE64 = 650e7;//tSE
+ // Sector Erase Operation
+ specparam tdevice_SE256 = 1875e7;//tSE
+ // Bulk Erase Operation
+ specparam tdevice_BE = 330e9;//tBE
+ // WRR Cycle Time
+ specparam tdevice_WRR = 1; // 2e9;//tW
+ // Erase Suspend/Erase Resume Time
+ specparam tdevice_ERSSUSP = 45e6;//tESL
+ // Program Suspend/Program Resume Time
+ specparam tdevice_PRGSUSP = 1; // 40e6;//
+ // VCC (min) to CS# Low
+ specparam tdevice_PU = 1; // 3e8;//tPU
+ // PPB Erase Time
+ specparam tdevice_PPBERASE = 15e9;//
+ // Password Unlock Time
+ specparam tdevice_PASSULCK = 1e6;//
+ // Password Unlock to Password Unlock Time
+ specparam tdevice_PASSACC = 100e6;
+ // Data In Setup Max time
+ specparam tdevice_TSU = 300e3;
+ `else
+ // Page Program Operation
+ specparam tdevice_PP_256 = 75e7;//tPP
+ // Page Program Operation
+ specparam tdevice_PP_512 = 75e7;//tPP
+ // Typical Byte Programming Time
+ specparam tdevice_BP = 4e8;//tBP
+ // Sector Erase Operation
+ specparam tdevice_SE64 = 650e9;//tSE
+ // Sector Erase Operation
+ specparam tdevice_SE256 = 1875e9;//tSE
+ // Bulk Erase Operation
+ specparam tdevice_BE = 330e12;//tBE
+ // WRR Cycle Time
+ specparam tdevice_WRR = 2e11;//tW
+ // Erase Suspend/Erase Resume Time
+ specparam tdevice_ERSSUSP = 45e6;//tESL
+ // Program Suspend/Program Resume Time
+ specparam tdevice_PRGSUSP = 40e6;//
+ // VCC (min) to CS# Low
+ specparam tdevice_PU = 3e8;//tPU
+ // PPB Erase Time
+ specparam tdevice_PPBERASE = 15e9;//
+ // Password Unlock Time
+ specparam tdevice_PASSULCK = 1e6;//
+ // Password Unlock to Password Unlock Time
+ specparam tdevice_PASSACC = 100e6;
+ // Data In Setup Max time
+ specparam tdevice_TSU = 300e3;
+ `endif // SPEEDSIM
+
+///////////////////////////////////////////////////////////////////////////////
+// Input Port Delays don't require Verilog description
+///////////////////////////////////////////////////////////////////////////////
+// Path delays //
+///////////////////////////////////////////////////////////////////////////////
+ if (~ddr) (SCK => SO) = tpd_SCK_SO_normal;
+ if (ddr || rd_fast) (SCK => SO) = tpd_SCK_SO_DDR;
+
+ if (~ddr && dual) (SCK => SI) = tpd_SCK_SO_normal;
+ if ( ddr && dual) (SCK => SI) = tpd_SCK_SO_DDR;
+
+ if (~ddr && QUAD)(SCK => HOLDNeg) = tpd_SCK_SO_normal;
+ if ( ddr && QUAD)(SCK => HOLDNeg) = tpd_SCK_SO_DDR;
+ if (~ddr && QUAD)(SCK => WPNeg) = tpd_SCK_SO_normal;
+ if ( ddr && QUAD)(SCK => WPNeg) = tpd_SCK_SO_DDR;
+
+ if (CSNeg) (CSNeg => SO) = tpd_CSNeg_SO;
+ if (CSNeg && dual) (CSNeg => SI) = tpd_CSNeg_SO;
+
+ if (CSNeg && QUAD) (CSNeg => HOLDNeg) = tpd_CSNeg_SO;
+ if (CSNeg && QUAD) (CSNeg => WPNeg) = tpd_CSNeg_SO;
+
+ if (~QUAD) (HOLDNeg => SO) = tpd_HOLDNeg_SO;
+ if (~QUAD && dual) (HOLDNeg => SI) = tpd_HOLDNeg_SO;
+
+ (RSTNeg => SO) = tpd_RSTNeg_SO;
+///////////////////////////////////////////////////////////////////////////////
+// Timing Violation //
+///////////////////////////////////////////////////////////////////////////////
+ $setup ( CSNeg , posedge SCK &&& sdr_rd,
+ tsetup_CSNeg_SCK, Viol);
+ $setup ( CSNeg , posedge SCK &&& ddr_rd,
+ tsetup_CSNeg_SCK_DDR, Viol);
+ $setup ( SI , posedge SCK &&& deg_sin,
+ tsetup_SI_SCK_normal, Viol);
+ $setup ( WPNeg , negedge CSNeg &&& wr_prot,
+ tsetup_WPNeg_CSNeg, Viol);
+ $setup ( HOLDNeg , posedge SCK &&& quad_rd,
+ tsetup_HOLDNeg_SCK, Viol);
+ $setup ( SI , posedge SCK &&& ddro,
+ tsetup_SI_SCK_DDR, Viol);
+ $setup ( SI , negedge SCK &&& ddro,
+ tsetup_SI_SCK_DDR, Viol);
+ $setup ( SI , posedge SCK &&& ddro80,
+ tsetup_SI_SCK_DDR, Viol);
+ $setup ( SI , negedge SCK &&& ddro80,
+ tsetup_SI_SCK_DDR, Viol);
+
+ $setup ( RSTNeg , negedge CSNeg,
+ tsetup_RSTNeg_CSNeg, Viol);
+
+ $hold ( posedge SCK &&& sdr_rd , CSNeg,
+ thold_CSNeg_SCK, Viol);
+ $hold ( posedge SCK &&& ddr_rd , CSNeg,
+ thold_CSNeg_SCK_DDR, Viol);
+ $hold ( posedge SCK &&& deg_sin , SI ,
+ thold_SI_SCK_normal, Viol);
+ $hold ( negedge SCK &&& deh_sout , SO ,
+ thold_SO_SCK_normal, Viol);
+ $hold ( negedge SCK &&& deh_ddr_sout , SO ,
+ thold_SO_SCK_normal, Viol);
+ $hold ( posedge SCK &&& deh_ddr_sout , SO ,
+ thold_SO_SCK_normal, Viol);
+ $hold ( posedge CSNeg &&& wr_prot , WPNeg ,
+ thold_WPNeg_CSNeg, Viol);
+ $hold ( posedge SCK &&& quad_rd , HOLDNeg ,
+ thold_HOLDNeg_SCK, Viol);
+ $hold ( posedge SCK &&& ddro , SI,
+ thold_SI_SCK_DDR, Viol);
+ $hold ( negedge SCK &&& ddro , SI,
+ thold_SI_SCK_DDR, Viol);
+ $hold ( posedge SCK &&& ddro80 , SI,
+ thold_SI_SCK_DDR, Viol);
+ $hold ( negedge SCK &&& ddro80 , SI,
+ thold_SI_SCK_DDR, Viol);
+
+ $hold ( negedge RSTNeg , CSNeg,
+ thold_CSNeg_RSTNeg, Viol);
+
+ $width ( posedge SCK &&& rd , tpw_SCK_serial_posedge);
+ $width ( negedge SCK &&& rd , tpw_SCK_serial_negedge);
+ $width ( posedge SCK &&& dual_rd , tpw_SCK_dual_posedge);
+ $width ( negedge SCK &&& dual_rd , tpw_SCK_dual_negedge);
+ $width ( posedge SCK &&& fast_rd , tpw_SCK_fast_posedge);
+ $width ( negedge SCK &&& fast_rd , tpw_SCK_fast_negedge);
+ $width ( posedge SCK &&& ddrd , tpw_SCK_DDR_posedge);
+ $width ( negedge SCK &&& ddrd , tpw_SCK_DDR_negedge);
+ $width ( posedge SCK &&& ddrd80 , tpw_SCK_DDR80_posedge);
+ $width ( negedge SCK &&& ddrd80 , tpw_SCK_DDR80_negedge);
+ $width ( posedge SCK &&& quadpg , tpw_SCK_quadpg_posedge);
+ $width ( negedge SCK &&& quadpg , tpw_SCK_quadpg_negedge);
+
+ $width ( posedge CSNeg &&& RD_EQU_1, tpw_CSNeg_read_posedge);
+ $width ( posedge CSNeg &&& RD_EQU_0, tpw_CSNeg_pgers_posedge);
+ $width ( negedge RSTNeg , tpw_RSTNeg_negedge);
+ $width ( posedge RSTNeg , tpw_RSTNeg_posedge);
+
+ $period ( posedge SCK &&& rd , tperiod_SCK_serial_rd);
+ $period ( posedge SCK &&& fast_rd , tperiod_SCK_fast_rd);
+ $period ( posedge SCK &&& dual_rd , tperiod_SCK_dual_rd);
+ $period ( posedge SCK &&& quadpg , tperiod_SCK_quadpg);
+ $period ( posedge SCK &&& ddrd , tperiod_SCK_DDR_rd);
+ $period ( posedge SCK &&& ddrd80 , tperiod_SCK_DDR80_rd);
+
+endspecify
+
+///////////////////////////////////////////////////////////////////////////////
+// Main Behavior Block //
+///////////////////////////////////////////////////////////////////////////////
+// FSM states
+ parameter IDLE = 5'd0;
+ parameter RESET_STATE = 5'd1;
+ parameter AUTOBOOT = 5'd2;
+ parameter WRITE_SR = 5'd3;
+ parameter PAGE_PG = 5'd4;
+ parameter OTP_PG = 5'd5;
+ parameter PG_SUSP = 5'd6;
+ parameter SECTOR_ERS = 5'd7;
+ parameter BULK_ERS = 5'd8;
+ parameter ERS_SUSP = 5'd9;
+ parameter ERS_SUSP_PG = 5'd10;
+ parameter ERS_SUSP_PG_SUSP= 5'd11;
+ parameter PASS_PG = 5'd12;
+ parameter PASS_UNLOCK = 5'd13;
+ parameter PPB_PG = 5'd14;
+ parameter PPB_ERS = 5'd15;
+ parameter AUTOBOOT_PG = 5'd16;
+ parameter ASP_PG = 5'd17;
+ parameter PLB_PG = 5'd18;
+ parameter DYB_PG = 5'd19;
+ parameter NVDLR_PG = 5'd20;
+
+ reg [4:0] current_state;
+ reg [4:0] next_state;
+
+// Instruction type
+ parameter NONE = 7'd0;
+ parameter WRR = 7'd1;
+ parameter PP = 7'd2;
+ parameter READ = 7'd3;
+ parameter WRDI = 7'd4;
+ parameter RDSR = 7'd5;
+ parameter WREN = 7'd6;
+ parameter RDSR2 = 7'd7;
+ parameter FSTRD = 7'd8;
+ parameter FSTRD4 = 7'd9;
+ parameter DDRFR = 7'd10;
+ parameter DDRFR4 = 7'd11;
+ parameter PP4 = 7'd12;
+ parameter RD4 = 7'd13;
+ parameter ABRD = 7'd14;
+ parameter ABWR = 7'd15;
+ parameter BRRD = 7'd16;
+ parameter BRWR = 7'd17;
+ parameter P4E = 7'd19;
+ parameter P4E4 = 7'd20;
+ parameter ASPRD = 7'd21;
+ parameter ASPP = 7'd22;
+ parameter CLSR = 7'd23;
+ parameter QPP = 7'd24;
+ parameter QPP4 = 7'd25;
+ parameter RDCR = 7'd26;
+ parameter DOR = 7'd27;
+ parameter DOR4 = 7'd28;
+ parameter DLPRD = 7'd29;
+ parameter OTPP = 7'd30;
+ parameter PNVDLR = 7'd31;
+ parameter OTPR = 7'd32;
+ parameter WVDLR = 7'd33;
+ parameter BE = 7'd34;
+ parameter QOR = 7'd35;
+ parameter QOR4 = 7'd36;
+ parameter ERSP = 7'd37;
+ parameter ERRS = 7'd38;
+ parameter PGSP = 7'd39;
+ parameter PGRS = 7'd40;
+ parameter REMS = 7'd41;
+ parameter RDID = 7'd42;
+ parameter MPM = 7'd43;
+ parameter PLBWR = 7'd44;
+ parameter PLBRD = 7'd45;
+ parameter RES = 7'd46;
+ parameter DIOR = 7'd47;
+ parameter DIOR4 = 7'd48;
+ parameter DDRDIOR = 7'd49;
+ parameter DDRDIOR4 = 7'd50;
+ parameter SE = 7'd51;
+ parameter SE4 = 7'd52;
+ parameter DYBRD = 7'd53;
+ parameter DYBWR = 7'd54;
+ parameter PPBRD = 7'd55;
+ parameter PPBP = 7'd56;
+ parameter PPBERS = 7'd57;
+ parameter PASSRD = 7'd58;
+ parameter PASSP = 7'd59;
+ parameter PASSU = 7'd60;
+ parameter QIOR = 7'd61;
+ parameter QIOR4 = 7'd62;
+ parameter DDRQIOR = 7'd63;
+ parameter DDRQIOR4 = 7'd64;
+ parameter RESET = 7'd65;
+ parameter MBR = 7'd66;
+ parameter BRAC = 7'd67;
+ parameter ECCRD = 7'd68;
+
+ reg [6:0] Instruct;
+
+//Bus cycle state
+ parameter STAND_BY = 3'd0;
+ parameter OPCODE_BYTE = 3'd1;
+ parameter ADDRESS_BYTES = 3'd2;
+ parameter DUMMY_BYTES = 3'd3;
+ parameter MODE_BYTE = 3'd4;
+ parameter DATA_BYTES = 3'd5;
+
+ reg [2:0] bus_cycle_state;
+
+ reg deq_pin;
+ always @(SO_in, SO_z)
+ begin
+ if (SO_in==SO_z)
+ deq_pin=1'b0;
+ else
+ deq_pin=1'b1;
+ end
+ // check when data is generated from model to avoid setuphold check in
+ // this occasion
+ assign deg_pin = deq_pin;
+ assign deh_pin = (deq_pin == 1'b0) && (SO_z != 1'bz);
+ reg deq_sin;
+ always @(SI_in, SIOut_z)
+ begin
+ if (SI_in==SIOut_z)
+ deq_sin=1'b0;
+ else
+ deq_sin=1'b1;
+ end
+ // check when data is generated from model to avoid setuphold check in
+ // this occasion
+ assign deg_sin=deq_sin
+ && (ddr == 1'b0) && (Instruct !== DDRFR)
+ && (Instruct !== DDRFR4) && (Instruct !== DDRDIOR)
+ && (Instruct !== DDRDIOR4) && (Instruct !== DDRQIOR)
+ && (Instruct !== DDRQIOR4) && (SIOut_z != 1'bz);
+ reg deq_sout;
+ always @(SO_out, SIOut_z)
+ begin
+ if (SO_out==SIOut_z)
+ deq_sout=1'b0;
+ else
+ deq_sout=1'b1;
+ end
+ // check when data is generated from model
+ assign deh_sout= (deq_sout == 1'b0)
+ && (ddr == 1'b0) && (SOut_z != 1'bz);
+ assign deh_ddr_sout= (deq_sout == 1'b0)
+ && (ddr == 1'b1) && (SOut_z != 1'bz);
+
+ reg deq_holdin;
+ always @(HOLDNeg_ipd, HOLDNegOut_zd)
+ begin
+ if (HOLDNeg_ipd==HOLDNegOut_zd)
+ deq_holdin=1'b0;
+ else
+ deq_holdin=1'b1;
+ end
+ // check when data is generated from model to avoid setuphold check in
+ // this occasion
+ assign deg_holdin=deq_holdin;
+ assign deh_holdin=(deq_holdin == 1'b0) && (HOLDNegOut_zd != 1'bz);
+
+ //Power Up time;
+ initial
+ begin
+ PoweredUp = 1'b0;
+ $display("%0t=>STATUS: SPI FLASH POWER UP Wait Time: %0d:%0d",$time,tdevice_PU,tdevice_PRGSUSP);
+ #tdevice_PU PoweredUp = 1'b1;
+ $display("%0t=>STATUS: SPI FLASH POWER UP",$time,);
+ end
+
+ initial
+ begin : Init
+ write = 1'b0;
+ cfg_write = 1'b0;
+ read_out = 1'b0;
+ Address = 0;
+ change_addr = 1'b0;
+ cnt = 0;
+ RST = 1'b0;
+ RST_in = 1'b0;
+ RST_out = 1'b1;
+ PDONE = 1'b1;
+ PSTART = 1'b0;
+ PGSUSP = 1'b0;
+ PGRES = 1'b0;
+ PRGSUSP_in = 1'b0;
+ ERSSUSP_in = 1'b0;
+ RES_TO_SUSP_MIN_TIME = 1'b0;
+ RES_TO_SUSP_TYP_TIME = 1'b0;
+
+ EDONE = 1'b1;
+ ESTART = 1'b0;
+ ESUSP = 1'b0;
+ ERES = 1'b0;
+
+ WDONE = 1'b1;
+ WSTART = 1'b0;
+
+ Reseted = 1'b0;
+
+ Instruct = NONE;
+ bus_cycle_state = STAND_BY;
+ current_state = RESET_STATE;
+ next_state = RESET_STATE;
+ end
+
+ // initialize memory and load preload files if any
+ initial
+ begin: InitMemory
+ integer i;
+
+ for (i=0;i<=AddrRANGE;i=i+1)
+ begin
+ Mem[i] = MaxData;
+ end
+
+ if ((UserPreload) && !(mem_file_name == "none"))
+ begin
+ // Memory Preload
+ //s25fl256s.mem, memory preload file
+ // @aaaaaa - <aaaaaa> stands for address
+ // dd - <dd> is byte to be written at Mem(aaaaaa++)
+ // (aaaaaa is incremented at every load)
+ $display("%m: Loading Memfile : %s",mem_file_name);
+ $readmemh(mem_file_name,Mem);
+ end
+
+ for (i=OTPLoAddr;i<=OTPHiAddr;i=i+1)
+ begin
+ OTPMem[i] = MaxData;
+ end
+
+ if (UserPreload && !(otp_file_name == "none"))
+ begin
+ //s25fl256s_otp memory file
+ // / - comment
+ // @aaaaaa - <aaaaaa> stands for address within last defined
+ // sector
+ // dd - <dd> is byte to be written at OTPMem(aaa++)
+ // (aa is incremented at every load)
+ // only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
+ $readmemh(otp_file_name,OTPMem);
+ end
+
+ LOCK_BYTE1[7:0] = OTPMem[16];
+ LOCK_BYTE2[7:0] = OTPMem[17];
+ LOCK_BYTE3[7:0] = OTPMem[18];
+ LOCK_BYTE4[7:0] = OTPMem[19];
+ end
+
+ // initialize memory and load preload files if any
+ initial
+ begin: InitTimingModel
+ integer i;
+ integer j;
+ //UNIFORM OR HYBRID arch model is used
+ //assumptions:
+ //1. TimingModel has format as S25FL128SXXXXXXXX_X_XXpF
+ //it is important that 16-th character from first one is "0" or "1"
+ //2. TimingModel does not have more then 24 characters
+ tmp_timing = TimingModel;//copy of TimingModel
+
+ i = 23;
+ while ((i >= 0) && (found != 1'b1))//search for first non null character
+ begin //i keeps position of first non null character
+ j = 7;
+ while ((j >= 0) && (found != 1'b1))
+ begin
+ if (tmp_timing[i*8+j] != 1'd0)
+ found = 1'b1;
+ else
+ j = j-1;
+ end
+ i = i - 1;
+ end
+ i = i +1;
+ if (found)//if non null character is found
+ begin
+ for (j=0;j<=7;j=j+1)
+ begin
+ //EHPLC/HPLC character is 15
+ tmp_char1[j] = TimingModel[(i-14)*8+j];
+ //256B/512B Page character is 16
+ tmp_char2[j] = TimingModel[(i-15)*8+j];
+ end
+ end
+ if (tmp_char1 == "0" || tmp_char1 == "2" || tmp_char1 == "3" ||
+ tmp_char1 == "R" || tmp_char1 == "A" || tmp_char1 == "B" ||
+ tmp_char1 == "C" || tmp_char1 == "D" || tmp_char1 == "Y" ||
+ tmp_char1 == "Z" || tmp_char1 == "S" || tmp_char1 == "T" ||
+ tmp_char1 == "K" || tmp_char1 == "L")
+ begin
+ EHP = 1;
+ if(tmp_char1 == "Z" || tmp_char1 == "S" || tmp_char1 == "T" ||
+ tmp_char1 == "K" || tmp_char1 == "L" || tmp_char1 == "Y")
+ begin
+ RdPswdProtEnable = 1;
+ end
+ end
+ else if (tmp_char1 == "4" || tmp_char1 == "6" || tmp_char1 == "7" ||
+ tmp_char1 == "8" || tmp_char1 == "9" || tmp_char1 == "Q")
+ begin
+ EHP = 0;
+ end
+
+ if (tmp_char1 == "0" || tmp_char1 == "2" || tmp_char1 == "3" ||
+ tmp_char1 == "R" || tmp_char1 == "A" || tmp_char1 == "B" ||
+ tmp_char1 == "C" || tmp_char1 == "D" || tmp_char1 == "4" ||
+ tmp_char1 == "6" || tmp_char1 == "7" || tmp_char1 == "8" ||
+ tmp_char1 == "9" || tmp_char1 == "Q")
+ begin
+ ASP_reg = 16'hFE7F;
+ ASP_reg_in = 16'hFE7F;
+ end
+ else if (tmp_char1 == "Y" || tmp_char1 == "Z" || tmp_char1 == "S" ||
+ tmp_char1 == "T" || tmp_char1 == "K" || tmp_char1 == "L")
+ begin
+ ASP_reg = 16'hFE4F;
+ ASP_reg_in = 16'hFE4F;
+ end
+
+ if (tmp_char2 == "0")
+ begin
+ PageSize = 255;
+ PageNum = PageNum64;
+ SecSize = SecSize64;
+ end
+ else if (tmp_char2 == "1")
+ begin
+ PageSize = 511;
+ PageNum = PageNum256;
+ SecSize = SecSize256;
+ end
+ end
+
+ //CFI
+ initial
+ begin: InitCFI
+ integer i;
+ integer j;
+ ///////////////////////////////////////////////////////////////////////
+ // ID-CFI array data
+ ///////////////////////////////////////////////////////////////////////
+ // Manufacturer and Device ID
+ CFI_array[8'h00] = Jedec_ID;
+ CFI_array[8'h01] = DeviceID1;
+ CFI_array[8'h02] = DeviceID2;
+ CFI_array[8'h03] = 8'h00;
+ if (tmp_char2 == "0")
+ // Uniform 64kB sectors
+ CFI_array[8'h04] = ExtendedID64;
+ else if (tmp_char2 == "1")
+ // Uniform 256kB sectors
+ CFI_array[8'h04] = ExtendedID256;
+ CFI_array[8'h05] = 8'h80;
+ CFI_array[8'h06] = 8'h00;
+ CFI_array[8'h07] = 8'h00;
+ CFI_array[8'h08] = 8'h00;
+ CFI_array[8'h09] = 8'h00;
+ CFI_array[8'h0A] = 8'h00;
+ CFI_array[8'h0B] = 8'h00;
+ CFI_array[8'h0C] = 8'h00;
+ CFI_array[8'h0D] = 8'h00;
+ CFI_array[8'h0E] = 8'h00;
+ CFI_array[8'h0F] = 8'h00;
+ // CFI Query Identification String
+ CFI_array[8'h10] = 8'h51;
+ CFI_array[8'h11] = 8'h52;
+ CFI_array[8'h12] = 8'h59;
+ CFI_array[8'h13] = 8'h02;
+ CFI_array[8'h14] = 8'h00;
+ CFI_array[8'h15] = 8'h40;
+ CFI_array[8'h16] = 8'h00;
+ CFI_array[8'h17] = 8'h53;
+ CFI_array[8'h18] = 8'h46;
+ CFI_array[8'h19] = 8'h51;
+ CFI_array[8'h1A] = 8'h00;
+ //CFI system interface string
+ CFI_array[8'h1B] = 8'h27;
+ CFI_array[8'h1C] = 8'h36;
+ CFI_array[8'h1D] = 8'h00;
+ CFI_array[8'h1E] = 8'h00;
+ CFI_array[8'h1F] = 8'h06;
+ if (tmp_char2 == "0")
+ begin
+ // 64kB sector and 256B page
+ CFI_array[8'h20] = 8'h08;
+ CFI_array[8'h21] = 8'h08;
+ end
+ else if (tmp_char2 == "1")
+ begin
+ // 256kB sector and 512B page
+ CFI_array[8'h20] = 8'h09;
+ CFI_array[8'h21] = 8'h09;
+ end
+ CFI_array[8'h22] = 8'h10;
+ CFI_array[8'h23] = 8'h02;
+ CFI_array[8'h24] = 8'h02;
+ CFI_array[8'h25] = 8'h03;
+ CFI_array[8'h26] = 8'h03;
+ // Device Geometry Definition(Uniform Sector Devices)
+ CFI_array[8'h27] = 8'h19;
+ CFI_array[8'h28] = 8'h02;
+ CFI_array[8'h29] = 8'h01;
+
+ if (tmp_char2 == "0")
+ // 64kB sectors
+ CFI_array[8'h2A] = 8'h08;
+ else if (tmp_char2 == "1")
+ CFI_array[8'h2A] = 8'h09;
+
+ CFI_array[8'h2B] = 8'h00;
+ if (tmp_char2 == "1")
+ begin
+ CFI_array[8'h2C] = 8'h01;
+ CFI_array[8'h2D] = 8'h7F;
+ CFI_array[8'h2E] = 8'h00;
+ CFI_array[8'h2F] = 8'h00;
+ CFI_array[8'h30] = 8'h04;
+ CFI_array[8'h31] = 8'hFF;
+ CFI_array[8'h32] = 8'hFF;
+ CFI_array[8'h33] = 8'hFF;
+ CFI_array[8'h34] = 8'hFF;
+ end
+ else
+ begin
+ CFI_array[8'h2C] = 8'h02;
+ if (TBPARM)
+ begin
+ // 4KB physical sectors at top
+ CFI_array[8'h2D] = 8'hFD;
+ CFI_array[8'h2E] = 8'h00;
+ CFI_array[8'h2F] = 8'h00;
+ CFI_array[8'h30] = 8'h01;
+ CFI_array[8'h31] = 8'h1F;
+ CFI_array[8'h32] = 8'h01;
+ CFI_array[8'h33] = 8'h10;
+ CFI_array[8'h34] = 8'h00;
+ end
+ else
+ begin
+ // 4KB physical sectors at bottom
+ CFI_array[8'h2D] = 8'h1F;
+ CFI_array[8'h2E] = 8'h00;
+ CFI_array[8'h2F] = 8'h10;
+ CFI_array[8'h30] = 8'h00;
+ CFI_array[8'h31] = 8'hFD;
+ CFI_array[8'h32] = 8'h01;
+ CFI_array[8'h33] = 8'h00;
+ CFI_array[8'h34] = 8'h01;
+ end
+ end
+ CFI_array[8'h35] = 8'hFF;
+ CFI_array[8'h36] = 8'hFF;
+ CFI_array[8'h37] = 8'hFF;
+ CFI_array[8'h38] = 8'hFF;
+ CFI_array[8'h39] = 8'hFF;
+ CFI_array[8'h3A] = 8'hFF;
+ CFI_array[8'h3B] = 8'hFF;
+ CFI_array[8'h3C] = 8'hFF;
+ CFI_array[8'h3D] = 8'hFF;
+ CFI_array[8'h3E] = 8'hFF;
+ CFI_array[8'h3F] = 8'hFF;
+ // CFI Primary Vendor-Specific Extended Query
+ CFI_array[8'h40] = 8'h50;
+ CFI_array[8'h41] = 8'h52;
+ CFI_array[8'h42] = 8'h49;
+ CFI_array[8'h43] = 8'h31;
+ CFI_array[8'h44] = 8'h33;
+ CFI_array[8'h45] = 8'h21;
+ CFI_array[8'h46] = 8'h02;
+ CFI_array[8'h47] = 8'h01;
+ CFI_array[8'h48] = 8'h00;
+ CFI_array[8'h49] = 8'h08;
+ CFI_array[8'h4A] = 8'h00;
+ CFI_array[8'h4B] = 8'h01;
+ CFI_array[8'h4C] = 8'h00;
+ CFI_array[8'h4D] = 8'h00;
+ CFI_array[8'h4E] = 8'h00;
+ CFI_array[8'h4F] = 8'h07;
+ CFI_array[8'h50] = 8'h01;
+
+ begin
+ for(i=80;i>=0;i=i-1)
+ begin
+ CFI_tmp = CFI_array[8'h00-i+80];
+ for(j=7;j>=0;j=j-1)
+ begin
+ CFI_array_tmp[8*i+j] = CFI_tmp[j];
+ end
+ end
+ end
+
+ end
+
+ always @(next_state_event or PoweredUp or RST or RST_out or
+ RSTNeg_in or rising_edge_RSTNeg or falling_edge_RST)
+ begin: StateTransition
+ if (PoweredUp)
+ begin
+ if ((RSTNeg_in == 1'b1) && (RST_out == 1'b1))
+ current_state = #(1000) next_state;
+ else if ((~RSTNeg_in || rising_edge_RSTNeg) && falling_edge_RST)
+ begin
+ // no state transition while RESET# low
+ current_state = RESET_STATE;
+ RST_in = 1'b1;
+ #1000 RST_in = 1'b0;
+ end
+ end
+ end
+
+ always @(posedge RST_in)
+ begin:Threset
+ RST_out = 1'b0;
+ #(35000000-200000) RST_out = 1'b1;
+ end
+
+ always @(negedge CSNeg_ipd)
+ begin:CheckCEOnPowerUP
+ if (~PoweredUp)
+ $display ("%0t=> Device is selected during Power Up",$time);
+ end
+
+ ///////////////////////////////////////////////////////////////////////////
+ //// Internal Delays
+ ///////////////////////////////////////////////////////////////////////////
+
+ always @(posedge PRGSUSP_in)
+ begin:PRGSuspend
+ PRGSUSP_out = 1'b0;
+ #tdevice_PRGSUSP PRGSUSP_out = 1'b1;
+ end
+
+ always @(posedge PPBERASE_in)
+ begin:PPBErs
+ PPBERASE_out = 1'b0;
+ #tdevice_PPBERASE PPBERASE_out = 1'b1;
+ end
+
+ always @(posedge ERSSUSP_in)
+ begin:ERSSuspend
+ ERSSUSP_out = 1'b0;
+ #tdevice_ERSSUSP ERSSUSP_out = 1'b1;
+ end
+
+ always @(posedge PASSULCK_in)
+ begin:PASSULock
+ PASSULCK_out = 1'b0;
+ #tdevice_PASSULCK PASSULCK_out = 1'b1;
+ end
+
+ always @(posedge PASSACC_in)
+ begin:PASSAcc
+ PASSACC_out = 1'b0;
+ #tdevice_PASSACC PASSACC_out = 1'b1;
+ end
+
+///////////////////////////////////////////////////////////////////////////////
+// write cycle decode
+///////////////////////////////////////////////////////////////////////////////
+ integer opcode_cnt = 0;
+ integer addr_cnt = 0;
+ integer mode_cnt = 0;
+ integer dummy_cnt = 0;
+ integer data_cnt = 0;
+ integer bit_cnt = 0;
+
+ reg [4095:0] Data_in = 4096'b0;
+ reg [7:0] opcode;
+ reg [7:0] opcode_in;
+ reg [7:0] opcode_tmp;
+ reg [31:0] addr_bytes;
+ reg [31:0] hiaddr_bytes;
+ reg [31:0] Address_in;
+ reg [7:0] mode_bytes;
+ reg [7:0] mode_in;
+ integer Latency_code;
+ integer quad_data_in [0:1023];
+ reg [3:0] quad_nybble = 4'b0;
+ reg [3:0] Quad_slv;
+ reg [7:0] Byte_slv;
+
+ always @(rising_edge_CSNeg_ipd or falling_edge_CSNeg_ipd or
+ rising_edge_SCK_ipd or falling_edge_SCK_ipd or
+ current_state)
+ begin: Buscycle
+ integer i;
+ integer j;
+ integer k;
+ time CLK_PER;
+ time LAST_CLK;
+
+ if (current_state == RESET_STATE)
+ bus_cycle_state = STAND_BY;
+ else
+ begin
+ if (falling_edge_CSNeg_ipd)
+ begin
+ if (bus_cycle_state==STAND_BY)
+ begin
+ Instruct = NONE;
+ write = 1'b1;
+ cfg_write = 0;
+ opcode_cnt = 0;
+ addr_cnt = 0;
+ mode_cnt = 0;
+ dummy_cnt = 0;
+ data_cnt = 0;
+ opcode_tmp = 0;
+ start_dlp = 0;
+ DOUBLE = 1'b0;
+ QUADRD = 1'b0;
+ CLK_PER = 1'b0;
+ LAST_CLK = 1'b0;
+ if (current_state == AUTOBOOT)
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ else
+ begin
+ bus_cycle_state = OPCODE_BYTE;
+ end
+ end
+ end
+
+ if (rising_edge_SCK_ipd) // Instructions, addresses or data present
+ begin // at SI are latched on the rising edge of SCK
+
+ CLK_PER = $time - LAST_CLK;
+ LAST_CLK = $time;
+ if (CHECK_FREQ)
+ begin
+ if ((CLK_PER < 20000 && Latency_code == 3) ||
+ (CLK_PER < 12500 && Latency_code == 0) ||
+ (CLK_PER < 11100 && Latency_code == 1) ||
+ (CLK_PER < 9600 && Latency_code == 2))
+ begin
+ $display ("More wait states are required for");
+ $display ("this clock frequency value");
+ end
+ if (Instruct == DDRFR || Instruct == DDRFR4 || Instruct == DDRDIOR ||
+ Instruct == DDRDIOR4 || Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ if (CLK_PER < 12500)
+ begin
+ ddr80 = 1'b1;
+ end
+ else
+ begin
+ ddr80 = 1'b0;
+ end
+ end
+ CHECK_FREQ = 0;
+ end
+
+ if (~CSNeg_ipd)
+ begin
+ case (bus_cycle_state)
+ OPCODE_BYTE:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ opcode_in[opcode_cnt] = SI_in;
+ opcode_cnt = opcode_cnt + 1;
+ Latency_code = Config_reg1[7:6];
+ if (opcode_cnt == BYTE)
+ begin
+ for(i=7;i>=0;i=i-1)
+ begin
+ opcode[i] = opcode_in[7-i];
+ end
+ case (opcode)
+ 8'b00000110 : // 06h
+ begin
+ Instruct = WREN;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00000100 : // 04h
+ begin
+ Instruct = WRDI;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00000001 : // 01h
+ begin
+ Instruct = WRR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00000011 : // 03h
+ begin
+ Instruct = READ;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b00010011 : // 13h
+ begin
+ Instruct = RD4;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b01001011 : // 4Bh
+ begin
+ Instruct = OTPR;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b00000101 : // 05h
+ begin
+ Instruct = RDSR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00000111 : // 07h
+ begin
+ Instruct = RDSR2;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00110101 : // 35h
+ begin
+ Instruct = RDCR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10010000 : // 90h
+ begin
+ Instruct = REMS;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b10011111 : // 9Fh
+ begin
+ Instruct = RDID;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10101011 : // ABh
+ begin
+ Instruct = RES;
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ 8'b00001011 : // 0Bh
+ begin
+ Instruct = FSTRD;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00001100 : // 0Ch
+ begin
+ Instruct = FSTRD4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00001101 : // 0Dh
+ begin
+ Instruct = DDRFR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00001110 : // 0Eh
+ begin
+ Instruct = DDRFR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00111011 : // 3Bh
+ begin
+ Instruct = DOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00111100 : // 3Ch
+ begin
+ Instruct = DOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b10111011 : // BBh
+ begin
+ Instruct = DIOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b10111100 : // BCh
+ begin
+ Instruct = DIOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b10111101 : // BDh
+ begin
+ Instruct = DDRDIOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b10111110 : // BEh
+ begin
+ Instruct = DDRDIOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b01101011 : // 6Bh
+ begin
+ Instruct = QOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b01101100 : // 6Ch
+ begin
+ Instruct = QOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b11101011 : // EBh
+ begin
+ Instruct = QIOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b11101100 : // ECh
+ begin
+ Instruct = QIOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b11101101 : // EDh
+ begin
+ Instruct = DDRQIOR;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b11101110 : // EEh
+ begin
+ Instruct = DDRQIOR4;
+ bus_cycle_state = ADDRESS_BYTES;
+ CHECK_FREQ = 1'b1;
+ end
+ 8'b00000010 : // 02h
+ begin
+ Instruct = PP;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b00010010 : // 12h
+ begin
+ Instruct = PP4;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b00110010: // 32h
+ begin
+ Instruct = QPP;
+ bus_cycle_state = ADDRESS_BYTES;
+ quad_pg = 1'b1;
+ end
+ 8'b00111000: // 38h
+ begin
+ Instruct = QPP;
+ bus_cycle_state = ADDRESS_BYTES;
+ quad_pg = 1'b1;
+ end
+ 8'b00110100 : // 34h
+ begin
+ Instruct = QPP4;
+ bus_cycle_state = ADDRESS_BYTES;
+ quad_pg = 1'b1;
+ end
+ 8'b01000010 : // 42h
+ begin
+ Instruct = OTPP;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b10000101 : // 85h
+ begin
+ Instruct = PGSP;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10001010 : // 8Ah
+ begin
+ Instruct = PGRS;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11000111 : // C7h
+ begin
+ Instruct = BE;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b01100000 : // 60h
+ begin
+ Instruct = BE;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11011000 : // D8h
+ begin
+ Instruct = SE;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b11011100 : // DCh
+ begin
+ Instruct = SE4;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b01110101 : // 75h
+ begin
+ Instruct = ERSP;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b01111010 : // 7Ah
+ begin
+ Instruct = ERRS;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00010100 : // 14h
+ begin
+ Instruct = ABRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00010101 : // 15h
+ begin
+ Instruct = ABWR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00010110 : // 16h
+ begin
+ Instruct = BRRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00010111 : // 17h
+ begin
+ Instruct = BRWR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00101011 : // 2Bh
+ begin
+ Instruct = ASPRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00101111 : // 2Fh
+ begin
+ Instruct = ASPP;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11100000 : // E0h
+ begin
+ Instruct = DYBRD;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b11100001 : // E1h
+ begin
+ Instruct = DYBWR;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b11100010 : // E2h
+ begin
+ Instruct = PPBRD;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b11100011 : // E3h
+ begin
+ Instruct = PPBP;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b11100100 : // E4h
+ begin
+ Instruct = PPBERS;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10100110 : // A6h
+ begin
+ Instruct = PLBWR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10100111 : // A7h
+ begin
+ Instruct = PLBRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11100111 : // E7h
+ begin
+ Instruct = PASSRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11101000 : // E8h
+ begin
+ Instruct = PASSP;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11101001 : // E9h
+ begin
+ Instruct = PASSU;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11110000 : // F0h
+ begin
+ Instruct = RESET;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00110000 : // 30h
+ begin
+ Instruct = CLSR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b00100000 : // 20h
+ begin
+ Instruct = P4E;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b00100001 : // 21h
+ begin
+ Instruct = P4E4;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ 8'b01000001 : // 41h
+ begin
+ Instruct = DLPRD;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b01000011 : // 43h
+ begin
+ Instruct = PNVDLR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b01001010 : // 4Ah
+ begin
+ Instruct = WVDLR;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b10111001 : // B9h
+ begin
+ Instruct = BRAC;
+ bus_cycle_state = DATA_BYTES;
+ end
+ 8'b11111111 : // FFh
+ begin
+ Instruct = MBR;
+ bus_cycle_state = MODE_BYTE;
+ end
+ 8'b00011000 : // 18h
+ begin
+ Instruct = ECCRD;
+ bus_cycle_state = ADDRESS_BYTES;
+ end
+ endcase
+ end
+ end
+ end //end of OPCODE BYTE
+
+ ADDRESS_BYTES :
+ begin
+ if ((Instruct == DDRFR) || (Instruct == DDRFR4) ||
+ (Instruct == DDRDIOR) || (Instruct == DDRDIOR4) ||
+ (Instruct == DDRQIOR) || (Instruct == DDRQIOR4))
+ DOUBLE = 1'b1;
+ else
+ DOUBLE = 1'b0;
+ if ((Instruct == QOR) || (Instruct == QOR4) ||
+ (Instruct == QIOR) || (Instruct == QIOR4) ||
+ (Instruct == DDRQIOR) || (Instruct == DDRQIOR4))
+ QUADRD = 1'b1;
+ else
+ QUADRD = 1'b0;
+ if (DOUBLE == 1'b0)
+ begin
+ if (((((Instruct == FSTRD) && (~EXTADD)) ||
+ ((Instruct == DOR) && (~EXTADD)) ||
+ (Instruct == OTPR)) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD)) ||
+ ((Instruct == QOR) && QUAD && (~EXTADD)))
+ begin
+ //Instruction + 3 Bytes Address + Dummy Byte
+ Address_in[addr_cnt] = SI_in;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 3*BYTE)
+ begin
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes ;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (Instruct==FSTRD || Instruct==DOR ||
+ Instruct == QOR)
+ begin
+ if (Latency_code == 3)
+ bus_cycle_state = DATA_BYTES;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if (Instruct==ECCRD)
+ begin
+ //Instruction + 4 Bytes Address + Dummy Byte
+ Address_in[addr_cnt] = SI_in;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 4*BYTE)
+ begin
+ for(i=31;i>=0;i=i-1)
+ begin
+ hiaddr_bytes[31-i] = Address_in[i];
+ end
+ //High order address bits are ignored
+ Address = {hiaddr_bytes[31:4],4'b0000};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if ((((Instruct==FSTRD4) ||
+ (Instruct==DOR4) ||
+ ((Instruct==FSTRD) && EXTADD) ||
+ ((Instruct==DOR) && EXTADD)) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD)) ||
+ ((Instruct==QOR4) && QUAD) ||
+ ((Instruct==QOR) && QUAD && EXTADD))
+ begin
+ //Instruction + 4 Bytes Address + Dummy Byte
+ Address_in[addr_cnt] = SI_in;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 4*BYTE)
+ begin
+ for(i=31;i>=0;i=i-1)
+ begin
+ hiaddr_bytes[31-i] = Address_in[i];
+ end
+ //High order address bits are ignored
+ Address = {7'b0000000,hiaddr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (Latency_code == 3)
+ bus_cycle_state = DATA_BYTES;
+ else
+ begin
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ end
+ else if ((Instruct==DIOR) && (~EXTADD) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD))
+ begin
+ //DUAL I/O High Performance Read(3 Bytes Addr)
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt + 1] = SI_in;
+ read_cnt = 0;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 3*BYTE/2)
+ begin
+ addr_cnt = 0;
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i]=Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if (((Instruct==DIOR4) ||
+ ((Instruct==DIOR) && EXTADD)) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD))
+ begin //DUAL I/O High Performance Read(4Bytes Addr)
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt + 1] = SI_in;
+ read_cnt = 0;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 4*BYTE/2)
+ begin
+ addr_cnt = 0;
+ for(i=31;i>=0;i=i-1)
+ begin
+ addr_bytes[31-i] = Address_in[i];
+ end
+ Address = {7'b0000000,addr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if ((Instruct == QIOR) && (~EXTADD))
+ begin
+ //QUAD I/O High Performance Read (3Bytes Address)
+ if (QUAD)
+ begin
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ read_cnt = 0;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 3*BYTE/4)
+ begin
+ addr_cnt = 0;
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = MODE_BYTE;
+ end
+ end
+ else
+ bus_cycle_state = STAND_BY;
+ end
+ else if ((Instruct==QIOR4) || ((Instruct==QIOR)
+ && EXTADD))
+ begin
+ //QUAD I/O High Performance Read (4Bytes Addr)
+ if (QUAD)
+ begin
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ read_cnt = 0;
+ addr_cnt = addr_cnt +1;
+ if (addr_cnt == 4*BYTE/4)
+ begin
+ addr_cnt =0;
+ for(i=31;i>=0;i=i-1)
+ begin
+ hiaddr_bytes[31-i] = Address_in[i];
+ end
+ //High order address bits are ignored
+ Address = {7'b0000000,hiaddr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = MODE_BYTE;
+ end
+ end
+ else
+ bus_cycle_state = STAND_BY;
+ end
+ else if ((((Instruct==RD4) || (Instruct==PP4) ||
+ (Instruct==SE4) ||(Instruct==PPBRD) ||
+ (Instruct==DYBRD) ||(Instruct==DYBWR) ||
+ (Instruct==PPBP) || (Instruct==P4E4) ||
+ ((Instruct==READ) && EXTADD) ||
+ ((Instruct==PP) && EXTADD) ||
+ ((Instruct==P4E) && EXTADD) ||
+ ((Instruct==SE) && EXTADD)) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD)) ||
+ (QUAD && (Instruct==QPP4 ||
+ ((Instruct==QPP) && EXTADD))))
+ begin
+ Address_in[addr_cnt] = SI_in;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 4*BYTE)
+ begin
+ for(i=31;i>=0;i=i-1)
+ begin
+ hiaddr_bytes[31-i] = Address_in[i];
+ end
+ //High order address bits are ignored
+ Address = {7'b0000000,hiaddr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ else if (((HOLDNeg_in && ~QUAD) || QUAD) &&
+ (~EXTADD))
+ begin
+ Address_in[addr_cnt] = SI_in;
+ addr_cnt = addr_cnt + 1;
+ if (addr_cnt == 3*BYTE)
+ begin
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ end
+ else
+ begin
+ if ((Instruct==DDRFR) && (~EXTADD))
+ //Fast DDR Read Mode
+ begin
+ Address_in[addr_cnt] = SI_in;
+ if ((addr_cnt/2) <= 16)
+ begin
+ opcode_tmp[addr_cnt/2] = SI_in;
+ end
+ addr_cnt = addr_cnt + 1;
+ read_cnt = 0;
+ end
+ else if ((Instruct==DDRFR4) ||
+ ((Instruct==DDRFR) && EXTADD))
+ begin
+ Address_in[addr_cnt] = SI_in;
+ if ((addr_cnt/2) <= 16)
+ begin
+ opcode_tmp[addr_cnt/2] = SI_in;
+ end
+ addr_cnt = addr_cnt + 1;
+ read_cnt = 0;
+ end
+ else if ((Instruct == DDRDIOR) && (~EXTADD))
+ begin //Dual I/O DDR Read Mode
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt+1]= SI_in;
+ if ((addr_cnt/2) <= 16)
+ begin
+ opcode_tmp[addr_cnt/2] = SI_in;
+ end
+ addr_cnt = addr_cnt + 1;
+ read_cnt = 0;
+ end
+ else if ((Instruct==DDRDIOR4) ||
+ ((Instruct==DDRDIOR) && EXTADD))
+ begin //Dual I/O DDR Read Mode
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt+1] = SI_in;
+ if ((addr_cnt/2) <= 16)
+ begin
+ opcode_tmp[addr_cnt/2] = SI_in;
+ end
+ addr_cnt = addr_cnt + 1;
+ read_cnt = 0;
+ end
+ else if ((Instruct==DDRQIOR) && (~EXTADD) && QUAD)
+ begin //Quad I/O DDR Read Mode
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ opcode_tmp[addr_cnt/2] = SI_in;
+ addr_cnt = addr_cnt +1;
+ read_cnt = 0;
+ end
+ else if (QUAD && ((Instruct==DDRQIOR4) ||
+ ((Instruct==DDRQIOR) && EXTADD)))
+ begin
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ opcode_tmp[addr_cnt/2] = SI_in;
+ addr_cnt = addr_cnt +1;
+ read_cnt = 0;
+ end
+ end
+ end
+
+ MODE_BYTE :
+ begin
+ if (((Instruct==DIOR) || (Instruct == DIOR4))
+ && ((HOLDNeg_in && ~QUAD) || QUAD))
+ begin
+ mode_in[2*mode_cnt] = SO_in;
+ mode_in[2*mode_cnt+1] = SI_in;
+ mode_cnt = mode_cnt + 1;
+ if (mode_cnt == BYTE/2)
+ begin
+ mode_cnt = 0;
+ for(i=7;i>=0;i=i-1)
+ begin
+ mode_bytes[i] = mode_in[7-i];
+ end
+ if (Latency_code == 0 || Latency_code == 3)
+ bus_cycle_state = DATA_BYTES;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if (((Instruct==QIOR) || (Instruct == QIOR4))
+ && QUAD)
+ begin
+ mode_in[4*mode_cnt] = HOLDNeg_in;
+ mode_in[4*mode_cnt+1] = WPNeg_in;
+ mode_in[4*mode_cnt+2] = SO_in;
+ mode_in[4*mode_cnt+3] = SI_in;
+ mode_cnt = mode_cnt + 1;
+ if (mode_cnt == BYTE/4)
+ begin
+ mode_cnt = 0;
+ for(i=7;i>=0;i=i-1)
+ begin
+ mode_bytes[i] = mode_in[7-i];
+ end
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if ((Instruct == DDRFR) || (Instruct == DDRFR4))
+ mode_in[2*mode_cnt] = SI_in;
+ else if ((Instruct==DDRDIOR) || (Instruct==DDRDIOR4))
+ begin
+ mode_in[4*mode_cnt] = SO_in;
+ mode_in[4*mode_cnt+1] = SI_in;
+ end
+ else if (((Instruct==DDRQIOR) || (Instruct == DDRQIOR4))
+ && QUAD)
+ begin
+ mode_in[0] = HOLDNeg_in;
+ mode_in[1] = WPNeg_in;
+ mode_in[2] = SO_in;
+ mode_in[3] = SI_in;
+ end
+ dummy_cnt = 0;
+ end
+
+ DUMMY_BYTES :
+ begin
+ Return_DLP(Instruct, EHP, Latency_code,
+ dummy_cnt, start_dlp);
+ if (DOUBLE == 1'b1 && (hold_mode==0) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ if ((((Instruct==FSTRD) || (Instruct==FSTRD4) ||
+ (Instruct==DOR) || (Instruct==DOR4) ||
+ (Instruct==OTPR)) &&
+ ((HOLDNeg_in && ~QUAD) || QUAD)) ||
+ (((Instruct==QOR)||(Instruct==QOR4)) && QUAD))
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (dummy_cnt == BYTE)
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+
+ else if ((Instruct==DDRFR) || (Instruct==DDRFR4))
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (EHP)
+ begin
+ if (((Latency_code == 3) && (dummy_cnt==1)) ||
+ ((Latency_code == 0) && (dummy_cnt==2)) ||
+ ((Latency_code == 1) && (dummy_cnt==4)) ||
+ ((Latency_code == 2) && (dummy_cnt==5)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ else
+ begin
+ if (((Latency_code == 3) && (dummy_cnt==4)) ||
+ ((Latency_code == 0) && (dummy_cnt==5)) ||
+ ((Latency_code == 1) && (dummy_cnt==6)) ||
+ ((Latency_code == 2) && (dummy_cnt==7)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ end
+ else if (Instruct==RES)
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (dummy_cnt == 3*BYTE)
+ bus_cycle_state = DATA_BYTES;
+ end
+ else if (Instruct==ECCRD)
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (dummy_cnt == BYTE)
+ bus_cycle_state = DATA_BYTES;
+ end
+ else if ((Instruct == DIOR) || (Instruct == DIOR4)
+ && ((HOLDNeg_in && ~QUAD) || QUAD))
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (EHP)
+ begin
+ if (((Latency_code == 1) && (dummy_cnt==1)) ||
+ ((Latency_code == 2) && (dummy_cnt==2)))
+ bus_cycle_state = DATA_BYTES;
+ end
+ else
+ begin
+ if (((Latency_code == 3) && (dummy_cnt==4)) ||
+ ((Latency_code == 0) && (dummy_cnt==4)) ||
+ ((Latency_code == 1) && (dummy_cnt==5)) ||
+ ((Latency_code == 2) && (dummy_cnt==6)))
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ else if ((Instruct==DDRDIOR) || (Instruct==DDRDIOR4))
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (EHP)
+ begin
+ if (((Latency_code == 3) && (dummy_cnt==2)) ||
+ ((Latency_code == 0) && (dummy_cnt==4)) ||
+ ((Latency_code == 1) && (dummy_cnt==5)) ||
+ ((Latency_code == 2) && (dummy_cnt==6)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ else
+ begin
+ if (((Latency_code == 3) && (dummy_cnt==4)) ||
+ ((Latency_code == 0) && (dummy_cnt==6)) ||
+ ((Latency_code == 1) && (dummy_cnt==7)) ||
+ ((Latency_code == 2) && (dummy_cnt==8)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ end
+ else if (((Instruct == QIOR) || (Instruct == QIOR4))
+ && QUAD)
+ begin
+ dummy_cnt = dummy_cnt + 1;
+ if (((Latency_code == 3) && (dummy_cnt==1)) ||
+ ((Latency_code == 0) && (dummy_cnt==4)) ||
+ ((Latency_code == 1) && (dummy_cnt==4)) ||
+ ((Latency_code == 2) && (dummy_cnt==5)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ else if (((Instruct==DDRQIOR) || (Instruct==DDRQIOR4))
+ && QUAD)
+ begin
+ dummy_cnt = dummy_cnt + 1;
+
+ if (((Latency_code == 3) && (dummy_cnt==3)) ||
+ ((Latency_code == 0) && (dummy_cnt==6)) ||
+ ((Latency_code == 1) && (dummy_cnt==7)) ||
+ ((Latency_code == 2) && (dummy_cnt==8)))
+ begin
+ bus_cycle_state = DATA_BYTES;
+ end
+ end
+ end
+
+ DATA_BYTES :
+ begin
+
+ if (DOUBLE == 1'b1 && (hold_mode==0))
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+
+ if ((QUAD) && ((Instruct==QPP) || (Instruct == QPP4)))
+ begin
+ quad_nybble = {HOLDNeg_in, WPNeg_in, SO_in, SI_in};
+ if (data_cnt > ((PageSize+1)*2-1))
+ begin
+ //In case of quad mode and QPP,
+ //if more than 512 bytes are sent to the device
+ for(i=0;i<=(PageSize*2-1);i=i+1)
+ begin
+ quad_data_in[i] = quad_data_in[i+1];
+ end
+ quad_data_in[(PageSize+1)*2-1] = quad_nybble;
+ data_cnt = data_cnt +1;
+ end
+ else
+ begin
+ if (quad_nybble !== 4'bZZZZ)
+ begin
+ quad_data_in[data_cnt] = quad_nybble;
+ end
+ data_cnt = data_cnt +1;
+ end
+ end
+ else if ((~QUADRD) && ((HOLDNeg_in && ~QUAD) || QUAD))
+ begin
+ if (data_cnt > ((PageSize+1)*8-1))
+ begin
+ //In case of serial mode and PP,
+ //if more than PageSize are sent to the device
+ //previously latched data are discarded and last
+ //256/512 data bytes are guaranteed to be programmed
+ //correctly within the same page.
+ if (bit_cnt == 0)
+ begin
+ for(i=0;i<=(PageSize*BYTE-1);i=i+1)
+ begin
+ Data_in[i] = Data_in[i+8];
+ end
+ end
+ Data_in[PageSize*BYTE + bit_cnt] = SI_in;
+ bit_cnt = bit_cnt + 1;
+ if (bit_cnt == 8)
+ begin
+ bit_cnt = 0;
+ end
+ data_cnt = data_cnt + 1;
+ end
+ else
+ begin
+ Data_in[data_cnt] = SI_in;
+ data_cnt = data_cnt + 1;
+ bit_cnt = 0;
+ end
+ end
+ end
+ endcase
+ end
+ end
+
+ if (falling_edge_SCK_ipd)
+ begin
+ if (~CSNeg_ipd)
+ begin
+ case (bus_cycle_state)
+ ADDRESS_BYTES :
+ begin
+ if (DOUBLE == 1'b1)
+ begin
+ if ((Instruct==DDRFR) && (~EXTADD))
+ //Fast DDR Read Mode
+ begin
+ Address_in[addr_cnt] = SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 3*BYTE)
+ begin
+ addr_cnt = 0;
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if ((Instruct==DDRFR4) ||
+ ((Instruct==DDRFR) && EXTADD))
+ begin
+ Address_in[addr_cnt] = SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 4*BYTE)
+ begin
+ addr_cnt = 0;
+ for(i=31;i>=0;i=i-1)
+ begin
+ addr_bytes[31-i] = Address_in[i];
+ end
+ Address = {7'b0000000,addr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ begin
+ bus_cycle_state = DUMMY_BYTES;
+ if (DOUBLE == 1'b1 && (hold_mode==0)
+ && VDLR_reg != 8'b00000000)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+ end
+ else if ((Instruct == DDRDIOR) && (~EXTADD))
+ begin //Dual I/O DDR Read Mode
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt+1]= SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 3*BYTE/2)
+ begin
+ addr_cnt = 0;
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ bus_cycle_state = DUMMY_BYTES;
+ end
+ end
+ else if ((Instruct==DDRDIOR4) ||
+ ((Instruct==DDRDIOR) && EXTADD))
+ begin //Dual I/O DDR Read Mode
+ Address_in[2*addr_cnt] = SO_in;
+ Address_in[2*addr_cnt+1] = SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 4*BYTE/2)
+ begin
+ addr_cnt = 0;
+ for(i=31;i>=0;i=i-1)
+ begin
+ addr_bytes[31-i] = Address_in[i];
+ end
+ Address = {7'b0000000,addr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ if (EHP)
+ bus_cycle_state = MODE_BYTE;
+ else
+ begin
+ bus_cycle_state = DUMMY_BYTES;
+ if (DOUBLE == 1'b1 && (hold_mode==0)
+ && VDLR_reg != 8'b00000000)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+ end
+ else if ((Instruct==DDRQIOR) && (~EXTADD) && QUAD)
+ begin //Quad I/O DDR Read Mode
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 3*BYTE/4)
+ begin
+ addr_cnt = 0;
+ for(i=23;i>=0;i=i-1)
+ begin
+ addr_bytes[23-i] = Address_in[i];
+ end
+ addr_bytes[31:25] = 7'b0000000;
+ addr_bytes[24] = Bank_Addr_reg[0];
+ Address = addr_bytes;
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = MODE_BYTE;
+ end
+ end
+ else if (QUAD && ((Instruct==DDRQIOR4) ||
+ ((Instruct==DDRQIOR) && EXTADD)))
+ begin
+ Address_in[4*addr_cnt] = HOLDNeg_in;
+ Address_in[4*addr_cnt+1] = WPNeg_in;
+ Address_in[4*addr_cnt+2] = SO_in;
+ Address_in[4*addr_cnt+3] = SI_in;
+ if (addr_cnt != 0)
+ begin
+ addr_cnt = addr_cnt + 1;
+ end
+ read_cnt = 0;
+ if (addr_cnt == 4*BYTE/4)
+ begin
+ addr_cnt = 0;
+ for(i=31;i>=0;i=i-1)
+ begin
+ addr_bytes[31-i] = Address_in[i];
+ end
+ Address = {7'b0000000,addr_bytes[24:0]};
+ change_addr = 1'b1;
+ #1 change_addr = 1'b0;
+ bus_cycle_state = MODE_BYTE;
+ end
+ end
+ end
+ end
+
+ MODE_BYTE :
+ begin
+ if ((Instruct == DDRFR) || (Instruct == DDRFR4))
+ begin
+ mode_in[2*mode_cnt+1] = SI_in;
+ mode_cnt = mode_cnt + 1;
+ if (mode_cnt == BYTE/2)
+ begin
+ mode_cnt = 0;
+ for(i=7;i>=0;i=i-1)
+ begin
+ mode_bytes[i] = mode_in[7-i];
+ end
+ bus_cycle_state = DUMMY_BYTES;
+ Return_DLP(Instruct, EHP, Latency_code,
+ dummy_cnt, start_dlp);
+ if (DOUBLE == 1'b1 && (hold_mode==0) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+ else if ((Instruct==DDRDIOR) || (Instruct==DDRDIOR4))
+ begin
+ mode_in[4*mode_cnt+2] = SO_in;
+ mode_in[4*mode_cnt+3] = SI_in;
+ mode_cnt = mode_cnt + 1;
+ if (mode_cnt == BYTE/4)
+ begin
+ mode_cnt = 0;
+ for(i=7;i>=0;i=i-1)
+ begin
+ mode_bytes[i] = mode_in[7-i];
+ end
+ bus_cycle_state = DUMMY_BYTES;
+ Return_DLP(Instruct, EHP, Latency_code,
+ dummy_cnt, start_dlp);
+ if (DOUBLE == 1'b1 && (hold_mode==0) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+ else if ((Instruct==DDRQIOR) || (Instruct==DDRQIOR4))
+ begin
+ mode_in[4] = HOLDNeg_in;
+ mode_in[5] = WPNeg_in;
+ mode_in[6] = SO_in;
+ mode_in[7] = SI_in;
+ for(i=7;i>=0;i=i-1)
+ begin
+ mode_bytes[i] = mode_in[7-i];
+ end
+ bus_cycle_state = DUMMY_BYTES;
+ Return_DLP(Instruct, EHP, Latency_code,
+ dummy_cnt, start_dlp);
+ if (DOUBLE == 1'b1 && (hold_mode==0) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+
+ DATA_BYTES:
+ begin
+ if (hold_mode==0)
+ begin
+ if (DOUBLE == 1'b1 )
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+
+ end
+ else
+ begin
+ if ((Instruct==READ) || (Instruct==RD4) ||
+ (Instruct==FSTRD)|| (Instruct==FSTRD4)||
+ (Instruct==RDSR) || (Instruct==RDSR2) ||
+ (Instruct==RDCR) || (Instruct==OTPR) ||
+ (Instruct==DOR) || (Instruct==DOR4) ||
+ (Instruct==DIOR)|| (Instruct==DIOR4)||
+ (Instruct==ABRD) || (Instruct==BRRD) ||
+ (Instruct==ASPRD)|| (Instruct==DYBRD) ||
+ (Instruct==PPBRD)|| (Instruct == ECCRD) ||
+ (Instruct==PASSRD)|| (Instruct==RDID)||
+ (Instruct==RES) || (Instruct==REMS) ||
+ (Instruct==PLBRD)|| (Instruct==DLPRD) ||
+ (current_state == AUTOBOOT &&
+ start_delay == 0) ||
+ (((Instruct==QOR) || (Instruct==QIOR) ||
+ (Instruct==QOR4) ||
+ (Instruct==QIOR4)) && QUAD))
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+ end
+
+ DUMMY_BYTES:
+ begin
+ if (hold_mode==0)
+ begin
+ Return_DLP(Instruct, EHP, Latency_code,
+ dummy_cnt, start_dlp);
+
+ if (DOUBLE == 1'b1 && VDLR_reg != 8'b00000000 &&
+ start_dlp)
+ begin
+ read_out = 1'b1;
+ #10 read_out = 1'b0;
+ end
+ end
+ end
+
+ endcase
+ end
+ end
+
+ if (rising_edge_CSNeg_ipd)
+ begin
+ if (bus_cycle_state != DATA_BYTES)
+ begin
+ if (bus_cycle_state == ADDRESS_BYTES && opcode_tmp == 8'hFF)
+ begin
+ Instruct = MBR;
+ end
+ bus_cycle_state = STAND_BY;
+ end
+ else
+ begin
+ if (bus_cycle_state == DATA_BYTES)
+ begin
+ if (((mode_bytes[7:4] == 4'b1010) &&
+ (Instruct==DIOR || Instruct==DIOR4 ||
+ Instruct==QIOR || Instruct==QIOR4)) ||
+ ((mode_bytes[7:4] == ~mode_bytes[3:0]) &&
+ (Instruct == DDRFR || Instruct == DDRFR4 ||
+ Instruct == DDRDIOR || Instruct == DDRDIOR4 ||
+ Instruct == DDRQIOR || Instruct == DDRQIOR4)))
+ bus_cycle_state = ADDRESS_BYTES;
+ else
+ bus_cycle_state = STAND_BY;
+
+ case (Instruct)
+ WREN,
+ WRDI,
+ BE,
+ SE,
+ SE4,
+ P4E,
+ P4E4,
+ CLSR,
+ BRAC,
+ RESET,
+ PPBERS,
+ PPBP,
+ PLBWR,
+ PGSP,
+ PGRS,
+ ERSP,
+ ERRS:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 0)
+ write = 1'b0;
+ end
+ end
+
+ WRR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 8)
+ //If CS# is driven high after eight
+ //cycle,only the Status Register is
+ //written to.
+ begin
+ write = 1'b0;
+ if (BAR_ACC == 0)
+ begin
+ for(i=0;i<=7;i=i+1)
+ begin
+ Status_reg1_in[i]=
+ Data_in[7-i];
+ end
+ end
+ else
+ begin
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ for(i=0;i<=7;i=i+1)
+ begin
+ Bank_Addr_reg_in[i]=
+ Data_in[7-i];
+ end
+ end
+ end
+ end
+ else if (data_cnt == 16)
+ //After the 16th cycle both the
+ //Status and Configuration Registers
+ //are written to.
+ begin
+ write = 1'b0;
+ if (BAR_ACC == 0)
+ begin
+ cfg_write = 1'b1;
+ for(i=0;i<=7;i=i+1)
+ begin
+ Status_reg1_in[i]=
+ Data_in[7-i];
+ Config_reg1_in[i]=
+ Data_in[15-i];
+ end
+ end
+ else
+ begin
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ for(i=0;i<=7;i=i+1)
+ begin
+ Bank_Addr_reg_in[i]=
+ Data_in[7-i];
+ end
+ end
+ end
+ end
+ end
+ end
+
+ PP,
+ PP4,
+ OTPP:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt > 0)
+ begin
+ if ((data_cnt % 8) == 0)
+ begin
+ write = 1'b0;
+ for(i=0;i<=PageSize;i=i+1)
+ begin
+ for(j=7;j>=0;j=j-1)
+ begin
+ if ((Data_in[(i*8)+(7-j)])
+ !== 1'bX)
+ begin
+ Byte_slv[j] =
+ Data_in[(i*8)+(7-j)];
+ end
+ end
+ WByte[i] = Byte_slv;
+ end
+
+ if (data_cnt > (PageSize+1)*BYTE)
+ Byte_number = PageSize;
+ else
+ Byte_number =
+ ((data_cnt/8) - 1);
+ end
+ end
+ end
+ end
+
+ QPP,
+ QPP4:
+ begin
+ if (data_cnt >0)
+ begin
+ if ((data_cnt % 2) == 0)
+ begin
+ write = 1'b0;
+ quad_pg = 1'b0;
+ for(i=0;i<=PageSize;i=i+1)
+ begin
+ for(j=1;j>=0;j=j-1)
+ begin
+ Quad_slv =
+ quad_data_in[(i*2)+(1-j)];
+ if (j==1)
+ Byte_slv[7:4] = Quad_slv;
+ else if (j==0)
+ Byte_slv[3:0] = Quad_slv;
+ end
+ WByte[i] = Byte_slv;
+ end
+ if (data_cnt > (PageSize+1)*2)
+ Byte_number = PageSize;
+ else
+ Byte_number = ((data_cnt/2)-1);
+ end
+ end
+ end
+
+ ABWR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 32)
+ begin
+ write = 1'b0;
+ for(j=0;j<=31;j=j+1)
+ begin
+ AutoBoot_reg_in[j] = Data_in[31-j];
+ end
+ end
+ end
+ end
+
+ BRWR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 8)
+ begin
+ write = 1'b0;
+ for(j=0;j<=7;j=j+1)
+ begin
+ Bank_Addr_reg_in[j] = Data_in[7-j];
+ end
+ end
+ end
+ end
+
+ ASPP:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 16)
+ begin
+ write = 1'b0;
+ for(j=0;j<=15;j=j+1)
+ begin
+ ASP_reg_in[j] = Data_in[15-j];
+ end
+ end
+ end
+ end
+
+ DYBWR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 8)
+ begin
+ write = 1'b0;
+ for(j=0;j<=7;j=j+1)
+ begin
+ DYBAR_in[j] = Data_in[7-j];
+ end
+ end
+ end
+ end
+
+ PNVDLR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 8)
+ begin
+ write = 1'b0;
+ for(j=0;j<=7;j=j+1)
+ begin
+ NVDLR_reg_in[j] = Data_in[7-j];
+ end
+ end
+ end
+ end
+
+ WVDLR:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 8)
+ begin
+ write = 1'b0;
+ for(j=0;j<=7;j=j+1)
+ begin
+ VDLR_reg_in[j] = Data_in[7-j];
+ end
+ end
+ end
+ end
+
+ PASSP:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 64)
+ begin
+ write = 1'b0;
+ for(j=1;j<=8;j=j+1)
+ begin
+ for(k=1;k<=8;k=k+1)
+ begin
+ Password_reg_in[j*8-k] =
+ Data_in[8*(j-1)+k-1];
+ end
+ end
+ end
+ end
+ end
+
+ PASSU:
+ begin
+ if ((HOLDNeg_in && ~QUAD) || QUAD)
+ begin
+ if (data_cnt == 64)
+ begin
+ write = 1'b0;
+ for(j=1;j<=8;j=j+1)
+ begin
+ for(k=1;k<=8;k=k+1)
+ begin
+ PASS_TEMP[j*8-k] =
+ Data_in[8*(j-1)+k-1];
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ end
+ end
+ end
+ end
+
+///////////////////////////////////////////////////////////////////////////////
+// Timing control for the Page Program
+///////////////////////////////////////////////////////////////////////////////
+ time pob;
+ time elapsed_pgm;
+ time elapsed_tsu;
+ time start_pgm;
+ time start_tsu;
+ time duration_pgm;
+ time duration_tsu;
+ event pdone_event;
+
+ always @(rising_edge_PSTART)
+ begin
+ if ((Instruct == PP) || (Instruct == PP4) || (Instruct == OTPP) ||
+ (Instruct == QPP) || (Instruct == QPP4))
+ if (PageSize == 255)
+ begin
+ pob = tdevice_PP_256;
+ end
+ else
+ begin
+ pob = tdevice_PP_512;
+ end
+ else
+ pob = tdevice_BP;
+ if ((rising_edge_PSTART) && PDONE)
+ begin
+ elapsed_pgm = 0;
+ duration_pgm = pob;
+ PDONE = 1'b0;
+ ->pdone_event;
+ start_pgm = $time;
+ end
+ end
+
+ always @(posedge PGSUSP)
+ begin
+ if (PGSUSP && (~PDONE))
+ begin
+ disable pdone_process;
+ elapsed_pgm = $time - start_pgm;
+ duration_pgm = pob - elapsed_pgm;
+ PDONE = 1'b0;
+ end
+ end
+
+ always @(posedge PGRES)
+ begin
+ start_pgm = $time;
+ ->pdone_event;
+ end
+
+ always @(pdone_event)
+ begin:pdone_process
+ PDONE = 1'b0;
+ #duration_pgm PDONE = 1'b1;
+ end
+
+ always @(SI)
+ begin
+ if ((Instruct == PGSP) || (Instruct == PGRS) ||
+ (Instruct == ERSP) || (Instruct == ERRS))
+ begin
+ start_tsu = $time;
+ end
+ end
+
+ always @(posedge SCK)
+ begin
+ if ((Instruct == PGSP) || (Instruct == PGRS) ||
+ (Instruct == ERSP) || (Instruct == ERRS))
+ begin
+ elapsed_tsu = $time - start_tsu;
+ duration_tsu = tdevice_TSU - elapsed_tsu;
+ if (duration_tsu > 0)
+ begin
+ TSU = 1'b0;
+ end
+ else
+ begin
+ TSU = 1'b1;
+ $display("Warning at", $time);
+ $display("tSU max time violation");
+ end
+ end
+ end
+///////////////////////////////////////////////////////////////////////////////
+// Timing control for the Write Status Register
+///////////////////////////////////////////////////////////////////////////////
+ time wob;
+ always @(posedge WSTART)
+ begin:wdone_process
+ wob = tdevice_WRR;
+ if (WSTART && WDONE)
+ begin
+ WDONE = 1'b0;
+ #wob WDONE = 1'b1;
+ end
+ end
+
+///////////////////////////////////////////////////////////////////////////////
+// Reset Timing
+///////////////////////////////////////////////////////////////////////////////
+
+ time startlo;
+ time starthi;
+ time durationlo;
+ time durationhi;
+
+ always @(negedge RSTNeg_in or Instruct)
+ begin
+ if (~RSTNeg_in)
+ begin
+ RST = 1'b1;
+ #200000 RST = 1'b0; // 200 ns
+ end
+ else if (Instruct == RESET)
+ begin
+ Reseted = 1'b0;
+ #10000 Reseted = 1'b1; // 10 ns
+ end
+ end
+
+ always @(RST_in or rising_edge_Reseted) // Reset done,program terminated
+ begin
+ if ((RST_in && ~RST) || (rising_edge_Reseted))
+ disable pdone_process;
+ disable edone_process;
+ disable wdone_process;
+ PDONE = 1'b1;
+ EDONE = 1'b1;
+ WDONE = 1'b1;
+ end
+
+///////////////////////////////////////////////////////////////////////////////
+// Timing control for the Bulk Erase
+///////////////////////////////////////////////////////////////////////////////
+ time seo;
+ time beo;
+ event edone_event;
+ time elapsed_ers;
+ time start_ers;
+ time duration_ers;
+
+ always @(rising_edge_ESTART)
+ begin
+ if (UniformSec)
+ begin
+ seo = tdevice_SE256;
+ end
+ else
+ begin
+ seo = tdevice_SE64;
+ end
+ beo = tdevice_BE;
+ if ((rising_edge_ESTART) && EDONE)
+ begin
+ if (Instruct == BE)
+ begin
+ duration_ers = beo;
+ end
+ else
+ begin
+ duration_ers = seo;
+ end
+ elapsed_ers = 0;
+ EDONE = 1'b0;
+ ->edone_event;
+ start_ers = $time;
+ end
+ end
+
+ always @(posedge ESUSP)
+ begin
+ if (ESUSP && (~EDONE))
+ begin
+ disable edone_process;
+ elapsed_ers = $time - start_ers;
+ duration_ers = seo - elapsed_ers;
+ EDONE = 1'b0;
+ end
+ end
+
+ always @(posedge ERES)
+ begin
+ if (ERES && (~EDONE))
+ begin
+ start_ers = $time;
+ ->edone_event;
+ end
+ end
+
+ always @(edone_event)
+ begin : edone_process
+ EDONE = 1'b0;
+ #duration_ers EDONE = 1'b1;
+ end
+
+ ///////////////////////////////////////////////////////////////////
+ // Process for clock frequency determination
+ ///////////////////////////////////////////////////////////////////
+ always @(posedge SCK_ipd)
+ begin : clock_period
+ if (SCK_ipd)
+ begin
+ SCK_cycle = $time - prev_SCK;
+ prev_SCK = $time;
+ end
+ end
+
+// /////////////////////////////////////////////////////////////////////////
+// // Main Behavior Process
+// // combinational process for next state generation
+// /////////////////////////////////////////////////////////////////////////
+
+ reg rising_edge_PDONE = 1'b0;
+ reg rising_edge_EDONE = 1'b0;
+ reg rising_edge_WDONE = 1'b0;
+ reg falling_edge_write = 1'b0;
+ reg falling_edge_PPBERASE_in = 1'b0;
+ reg falling_edge_PASSULCK_in = 1'b0;
+
+ integer i;
+ integer j;
+
+ always @(rising_edge_PoweredUp or falling_edge_write or
+ falling_edge_RSTNeg or rising_edge_PDONE or rising_edge_WDONE or
+ rising_edge_EDONE or ERSSUSP_out_event or rising_edge_RSTNeg or
+ PRGSUSP_out_event or rising_edge_CSNeg_ipd or rising_edge_RST_out
+ or falling_edge_PPBERASE_in or falling_edge_PASSULCK_in or RST_out)
+ begin: StateGen1
+
+ integer sect;
+
+ if (rising_edge_PoweredUp && RSTNeg_in && RST_out)
+ begin
+ if (ABE == 1 && RPME !== 0 )
+ begin
+ next_state = AUTOBOOT;
+ read_cnt = 0;
+ byte_cnt = 1;
+ read_addr = {AutoBoot_reg[31:9], 9'b0};
+ start_delay = AutoBoot_reg[8:1];
+ start_autoboot = 0;
+ ABSD = AutoBoot_reg[8:1];
+ end
+ else
+ next_state = IDLE;
+ end
+ else if (PoweredUp)
+ begin
+ if (RST_out == 1'b0)
+ next_state = current_state;
+ else if (falling_edge_write && Instruct == RESET)
+ begin
+ if (ABE == 1 && RPME !== 0)
+ begin
+ read_cnt = 0;
+ byte_cnt = 1;
+ read_addr = {AutoBoot_reg[31:9], 9'b0};
+ start_delay = AutoBoot_reg[8:1];
+ ABSD = AutoBoot_reg[8:1];
+ start_autoboot = 0;
+ next_state = AUTOBOOT;
+ end
+ else
+ next_state = IDLE;
+ end
+ else
+ begin
+ case (current_state)
+ RESET_STATE :
+ begin
+ if ((rising_edge_RST_out && RSTNeg_in) ||
+ (rising_edge_RSTNeg && RST_out))
+ begin
+ if (ABE == 1 && RPME!== 0)
+ begin
+ next_state = AUTOBOOT;
+ read_cnt = 0;
+ byte_cnt = 1;
+ read_addr = {AutoBoot_reg[31:9],9'b0};
+ start_delay = AutoBoot_reg[8:1];
+ start_autoboot = 0;
+ ABSD = AutoBoot_reg[8:1];
+ end
+ else
+ next_state = IDLE;
+ end
+ end
+
+ IDLE :
+ begin
+ if (falling_edge_write && RdPswdProtMode == 0)
+ begin
+ if (Instruct == WRR && WEL == 1 && BAR_ACC == 0
+ && (((~(SRWD == 1 && ~WPNeg_in))&& ~QUAD) || QUAD))
+ // can not execute if HPM is entered or
+ // if WEL bit is zero
+ if (((TBPROT==1 && Config_reg1_in[5]==1'b0) ||
+ (TBPARM==1 && Config_reg1_in[2]==1'b0) ||
+ (BPNV ==1 && Config_reg1_in[3]==1'b0)) &&
+ cfg_write)
+ begin
+ $display ("WARNING: Changing value of ");
+ $display ("Configuration Register OTP ");
+ $display ("bit from 1 to 0 is not");
+ $display ("allowed!!!");
+ end
+ else
+ begin
+ next_state = WRITE_SR;
+ end
+ else if (Instruct == WRR && BAR_ACC == 1)
+ begin
+ // Write to the lower address bits of the BAR
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ next_state = IDLE;
+ end
+ end
+ else if ((Instruct == PP || Instruct == QPP ||
+ Instruct == PP4 || Instruct == QPP4) &&
+ WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ if (Sec_Prot[sect]== 0 && PPB_bits[sect]== 1 &&
+ DYB_bits[sect]== 1)
+ begin
+ next_state = PAGE_PG;
+ end
+ end
+ else if (Instruct==OTPP && WEL==1 && FREEZE==0)
+ begin
+ if (((((Address>=16'h0010 && Address<=16'h0013)
+ ||(Address>=16'h0020 && Address<=16'h00FF))
+ && LOCK_BYTE1[Address/32] == 1) ||
+ ((Address>=16'h0100 && Address<=16'h01FF)
+ && LOCK_BYTE2[(Address-16'h0100)/32]==1) ||
+ ((Address>=16'h0200 && Address<=16'h02FF)
+ && LOCK_BYTE3[(Address-16'h0200)/32]==1) ||
+ ((Address>=16'h0300 && Address<=16'h03FF)
+ && LOCK_BYTE4[(Address-16'h0300)/32] == 1))
+ && (Address + Byte_number <= OTPHiAddr))
+ next_state = OTP_PG;
+ end
+ else if ((Instruct == SE || Instruct == SE4)
+ && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ if (UniformSec || (TopBoot && sect < 510) ||
+ (BottomBoot && sect > 31))
+ begin
+ if (Sec_Prot[sect]== 0 && PPB_bits[sect]== 1
+ && DYB_bits[sect]== 1)
+ next_state = SECTOR_ERS;
+ end
+ else if ((TopBoot && sect >= 510) ||
+ (BottomBoot && sect <= 31))
+ begin
+ if (Sec_ProtSE == 32 && ASP_ProtSE == 32)
+ //Sector erase command is applied to a
+ //64 KB range that includes 4 KB sectors.
+ next_state = SECTOR_ERS;
+ end
+ end
+ else if ((Instruct == P4E || Instruct == P4E4)
+ && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ if (UniformSec || (TopBoot && sect < 510) ||
+ (BottomBoot && sect > 31))
+ begin
+ $display("The instruction is applied to");
+ $display("a sector that is larger than");
+ $display("4 KB.");
+ $display("Instruction is ignored!!!");
+ end
+ else
+ begin
+ if (Sec_Prot[sect]== 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ next_state = SECTOR_ERS;
+ end
+ end
+ else if (Instruct == BE && WEL == 1 &&
+ (Status_reg1[4]== 0 && Status_reg1[3]== 0 &&
+ Status_reg1[2]== 0))
+ next_state = BULK_ERS;
+ else if (Instruct == ABWR && WEL == 1)
+ //Autoboot Register Write Command
+ next_state = AUTOBOOT_PG;
+ else if (Instruct == BRWR)
+ //Bank Register Write Command
+ next_state = IDLE;
+ else if (Instruct == ASPP && WEL == 1)
+ begin
+ //ASP Register Program Command
+ if (~(ASPOTPFLAG))
+ next_state = ASP_PG;
+ end
+ else if (Instruct == PLBWR && WEL == 1 &&
+ RdPswdProtEnable == 0)
+ next_state = PLB_PG;
+ else if (Instruct == PASSP && WEL == 1)
+ begin
+ if (~(PWDMLB== 0 && PSTMLB== 1))
+ next_state = PASS_PG;
+ end
+ else if (Instruct == PASSU && WEL && ~WIP)
+ next_state = PASS_UNLOCK;
+ else if (Instruct == PPBP && WEL == 1)
+ next_state <= PPB_PG;
+ else if (Instruct == PPBERS && WEL && PPBOTP)
+ next_state <= PPB_ERS;
+ else if (Instruct == DYBWR && WEL == 1)
+ next_state = DYB_PG;
+ else if (Instruct == PNVDLR && WEL == 1)
+ next_state = NVDLR_PG;
+ else
+ next_state = IDLE;
+ end
+ if (falling_edge_write && RdPswdProtMode == 1 && ~WIP)
+ begin
+ if (Instruct == PASSU)
+ next_state = PASS_UNLOCK;
+ end
+ end
+
+ AUTOBOOT :
+ begin
+ if (rising_edge_CSNeg_ipd)
+ next_state = IDLE;
+ end
+
+ WRITE_SR :
+ begin
+ if (rising_edge_WDONE)
+ next_state = IDLE;
+ end
+
+ PAGE_PG :
+ begin
+ if (PRGSUSP_out_event && PRGSUSP_out == 1)
+ next_state = PG_SUSP;
+ else if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ PG_SUSP :
+ begin
+ if (falling_edge_write)
+ begin
+ if (Instruct == BRWR)
+ //Bank Register Write Command
+ next_state = PG_SUSP;
+ else if (Instruct == PGRS)
+ next_state = PAGE_PG;
+ end
+ end
+
+ OTP_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ BULK_ERS :
+ begin
+ if (rising_edge_EDONE)
+ next_state = IDLE;
+ end
+
+ SECTOR_ERS :
+ begin
+ if (ERSSUSP_out_event && ERSSUSP_out == 1)
+ next_state = ERS_SUSP;
+ else if (rising_edge_EDONE)
+ next_state = IDLE;
+ end
+
+ ERS_SUSP :
+ begin
+ if (falling_edge_write)
+ begin
+ if ((Instruct == PP || Instruct == QPP ||
+ Instruct == PP4 || Instruct == QPP4) &&
+ WEL == 1)
+ begin
+ if ((PARAM_REGION &&
+ SectorSuspend != Address/(SecSize+1)) ||
+ (~PARAM_REGION && SectorSuspend !=
+ Address/(SecSize+1)+30*b_act))
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ if (PPB_bits[sect]== 1 &&
+ DYB_bits[sect]== 1)
+ begin
+ next_state = ERS_SUSP_PG;
+ end
+ end
+ end
+ else if (Instruct == BRWR)
+ begin
+ //Bank Register Write Command
+ next_state = ERS_SUSP;
+ end
+ else if (Instruct == DYBWR && WEL == 1)
+ next_state = DYB_PG;
+ else if (Instruct == ERRS)
+ next_state = SECTOR_ERS;
+ end
+ end
+
+ ERS_SUSP_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = ERS_SUSP;
+ else if (PRGSUSP_out_event && PRGSUSP_out == 1)
+ next_state = ERS_SUSP_PG_SUSP;
+ end
+
+ ERS_SUSP_PG_SUSP :
+ begin
+ if (rising_edge_PDONE)
+ next_state = ERS_SUSP;
+ if (falling_edge_write)
+ begin
+ if (Instruct == BRWR)
+ begin
+ next_state = ERS_SUSP_PG_SUSP;
+ end
+ else if (Instruct == PGRS)
+ begin
+ next_state = ERS_SUSP_PG;
+ end
+ end
+ end
+
+ PASS_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ PASS_UNLOCK :
+ begin
+ if (falling_edge_PASSULCK_in)
+ next_state = IDLE;
+ end
+
+ PPB_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ PPB_ERS :
+ begin
+ if (falling_edge_PPBERASE_in)
+ next_state = IDLE;
+ end
+
+ AUTOBOOT_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ PLB_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ DYB_PG :
+ begin
+ if (rising_edge_PDONE)
+ if (ES)
+ next_state = ERS_SUSP;
+ else
+ next_state = IDLE;
+ end
+
+ ASP_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ NVDLR_PG :
+ begin
+ if (rising_edge_PDONE)
+ next_state = IDLE;
+ end
+
+ endcase
+ end
+ end
+ end
+
+ ///////////////////////////////////////////////////////////////////////////
+ //FSM Output generation and general functionality
+ ///////////////////////////////////////////////////////////////////////////
+ reg rising_edge_read_out = 1'b0;
+ reg Instruct_event = 1'b0;
+ reg change_addr_event = 1'b0;
+ reg current_state_event = 1'b0;
+ reg rising_edge_DP_out = 1'b0;
+
+ integer WData [0:511];
+ integer WOTPData;
+ integer Addr;
+ integer Addr_tmp;
+
+ always @(Instruct_event)
+ begin
+ read_cnt = 0;
+ byte_cnt = 1;
+ rd_fast = 1'b1;
+ dual = 1'b0;
+ rd_slow = 1'b0;
+ any_read = 1'b0;
+ end
+
+ always @(rising_edge_read_out)
+ begin
+ if (rising_edge_read_out == 1'b1)
+ begin
+ if (PoweredUp == 1'b1)
+ begin
+ oe_z = 1'b1;
+ #1000 oe_z = 1'b0;
+ oe = 1'b1;
+ #1000 oe = 1'b0;
+ end
+ end
+ end
+
+ always @(change_addr_event)
+ begin
+ if (change_addr_event)
+ begin
+ read_addr = Address;
+ end
+ end
+
+ always @(posedge PASSACC_out)
+ begin
+ Status_reg1[0] = 1'b0; //WIP
+ PASSACC_in = 1'b0;
+ end
+
+ always @(Instruct or posedge start_autoboot or oe or current_state_event or
+ falling_edge_write or posedge PDONE or posedge WDONE or oe_z or
+ posedge EDONE or ERSSUSP_out or rising_edge_Reseted or
+ rising_edge_PoweredUp or rising_edge_CSNeg_ipd or PRGSUSP_out or
+ Address)
+ begin: Functionality
+ integer i,j;
+ integer sect;
+
+ if (rising_edge_PoweredUp)
+ begin
+ //the default condition after power-up
+ //The Bank Address Register is loaded to all zeroes
+ Bank_Addr_reg = 8'h0;
+ //The Configuration Register FREEZE bit is cleared.
+ Config_reg1[0] = 0;
+ //The WEL bit is cleared.
+ Status_reg1[1] = 0;
+ //When BPNV is set to '1'. the BP2-0 bits in Status Register are
+ //volatile and will be reset binary 111 after power-on reset
+ if (BPNV == 1 && FREEZE == 0 ) //&& LOCK == 0
+ begin
+ Status_reg1[4] = 1'b0;// BP2
+ Status_reg1[3] = 1'b0;// BP1
+ Status_reg1[2] = 1'b0;// BP0
+ BP_bits = {Status_reg1[4],Status_reg1[3],Status_reg1[2]};
+ change_BP = 1'b1;
+ #1000 change_BP = 1'b0;
+ end
+
+ //As shipped from the factory, all devices default ASP to the
+ //Persistent Protection mode, with all sectors unprotected,
+ //when power is applied. The device programmer or host system must
+ //then choose which sector protection method to use.
+ //For Persistent Protection mode, PPBLOCK defaults to "1"
+ PPBL[0] = 1'b1;
+
+ //All the DYB power-up in the unprotected state
+ DYB_bits = {542{1'b1}};
+
+ end
+
+ if (Instruct == RESET)
+ begin
+ //EXTADD is cleared to “0”
+ Bank_Addr_reg[7] = 1'b0;
+ //P_ERR bit is cleared
+ Status_reg1[6] = 1'b0;
+ //E_ERR bit is cleared
+ Status_reg1[5] = 1'b0;
+ //The WEL bit is cleared.
+ Status_reg1[1] = 1'b0;
+ //The WIP bit is cleared.
+ Status_reg1[0] = 1'b0;
+ //The ES bit is cleared.
+ Status_reg2[1] = 1'b0;
+ //The PS bit is cleared.
+ Status_reg2[0] = 1'b0;
+ //When BPNV is set to '1'. the BP2-0 bits in Status
+ //Register are volatile and will be reseted after
+ //reset command
+ if (BPNV == 1 && FREEZE == 0) //&& LOCK== 0
+ begin
+ Status_reg1[4] = 1'b1;
+ Status_reg1[3] = 1'b1;
+ Status_reg1[2] = 1'b1;
+
+ BP_bits = {Status_reg1[4],Status_reg1[3],
+ Status_reg1[2]};
+ change_BP = 1'b1;
+ #1000 change_BP = 1'b0;
+ end
+ end
+
+ case (current_state)
+ IDLE :
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ ASP_ProtSE = 0;
+ Sec_ProtSE = 0;
+
+ if (BottomBoot)
+ begin
+ for (j=31;j>=0;j=j-1)
+ begin
+ if (PPB_bits[j] == 1 && DYB_bits[j] == 1)
+ begin
+ ASP_ProtSE = ASP_ProtSE + 1;
+ end
+ if (Sec_Prot[j] == 0)
+ begin
+ Sec_ProtSE = Sec_ProtSE + 1;
+ end
+ end
+ end
+ else if (TopBoot)
+ begin
+ for (j=541;j>=510;j=j-1)
+ begin
+ if (PPB_bits[j] == 1 && DYB_bits[j] == 1)
+ begin
+ ASP_ProtSE = ASP_ProtSE + 1;
+ end
+ if (Sec_Prot[j] == 0)
+ begin
+ Sec_ProtSE = Sec_ProtSE + 1;
+ end
+ end
+ end
+
+ if (falling_edge_write && RdPswdProtMode == 1)
+ begin
+ if(Instruct == PASSU)
+ begin
+ if (~WIP)
+ begin
+ PASSULCK_in = 1;
+ Status_reg1[0] = 1'b1; //WIP
+ end
+ else
+ begin
+ $display ("The PASSU command cannot be accepted");
+ $display (" any faster than once every 100us");
+ end
+ end
+ else if (Instruct == CLSR)
+ begin
+ //The Clear Status Register Command resets bit SR1[5]
+ //(Erase Fail Flag) and bit SR1[6] (Program Fail Flag)
+ Status_reg1[5] = 0;
+ Status_reg1[6] = 0;
+ end
+ end
+
+ if (falling_edge_write && RdPswdProtMode == 0)
+ begin
+ read_cnt = 0;
+ byte_cnt = 1;
+ if (Instruct == WREN)
+ Status_reg1[1] = 1'b1;
+ else if (Instruct == WRDI)
+ Status_reg1[1] = 0;
+ else if ((Instruct == WRR) && WEL == 1 && WDONE == 1 &&
+ BAR_ACC == 0)
+ begin
+ if (((~(SRWD == 1 && ~WPNeg_in))&& ~QUAD) || QUAD)
+ begin
+ if (((TBPROT==1 && Config_reg1_in[5]==1'b0) ||
+ (TBPARM==1 && Config_reg1_in[2]==1'b0) ||
+ (BPNV ==1 && Config_reg1_in[3]==1'b0)) &&
+ cfg_write)
+ begin
+ // P_ERR bit is set to 1
+ Status_reg1[6] = 1'b1;
+ end
+ else
+ begin
+ // can not execute if Hardware Protection Mode
+ // is entered or if WEL bit is zero
+ WSTART = 1'b1;
+ WSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ end
+ else
+ Status_reg1[1] = 0;
+ end
+ else if ((Instruct == PP || Instruct == PP4) && WEL ==1 &&
+ PDONE == 1 )
+ begin
+ ReturnSectorID(sect,Address);
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ PGSUSP = 0;
+ PGRES = 0;
+ INITIAL_CONFIG = 1;
+ Status_reg1[0] = 1'b1;
+ SA = sect;
+ Addr = Address;
+ Addr_tmp= Address;
+ wr_cnt = Byte_number;
+ for (i=wr_cnt;i>=0;i=i-1)
+ begin
+ if (Viol != 0)
+ WData[i] = -1;
+ else
+ WData[i] = WByte[i];
+ end
+ end
+ else
+ begin
+ //P_ERR bit will be set when the user attempts to
+ //to program within a protected main memory sector
+ Status_reg1[6] = 1'b1; //P_ERR
+ Status_reg1[1] = 1'b0; //WEL
+ end
+ end
+ else if ((Instruct == QPP || Instruct == QPP4) && WEL ==1 &&
+ PDONE == 1 )
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ PGSUSP = 0;
+ PGRES = 0;
+ INITIAL_CONFIG = 1;
+// QPP_page[pgm_page] = 1'b1;
+ Status_reg1[0] = 1'b1;
+ SA = sect;
+ Addr = Address;
+ Addr_tmp= Address;
+ wr_cnt = Byte_number;
+ for (i=wr_cnt;i>=0;i=i-1)
+ begin
+ if (Viol != 0)
+ WData[i] = -1;
+ else
+ WData[i] = WByte[i];
+ end
+ end
+ else
+ begin
+ //P_ERR bit will be set when the user attempts to
+ //to program within a protected main memory sector
+ Status_reg1[6] = 1'b1; //P_ERR
+ Status_reg1[1] = 1'b0; //WEL
+ end
+ end
+ else if (Instruct == OTPP && WEL == 1)
+ begin
+ // As long as the FREEZE bit remains cleared to a logic
+ // '0' the OTP address space is programmable.
+ if (FREEZE == 0)
+ begin
+ if (((((Address>= 16'h0010 && Address<= 16'h0013) ||
+ (Address >= 16'h0020 && Address <= 16'h00FF))
+ && LOCK_BYTE1[Address/32] == 1) ||
+ ((Address >= 16'h0100 && Address <= 16'h01FF)
+ && LOCK_BYTE2[(Address-16'h0100)/32] == 1) ||
+ ((Address >= 16'h0200 && Address <= 16'h02FF)
+ && LOCK_BYTE3[(Address-16'h0200)/32] == 1) ||
+ ((Address >= 16'h0300 && Address <= 16'h03FF)
+ && LOCK_BYTE4[(Address-16'h0300)/32] == 1)) &&
+ (Address + Byte_number <= OTPHiAddr))
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ Addr = Address;
+ Addr_tmp= Address;
+ wr_cnt = Byte_number;
+ for (i=wr_cnt;i>=0;i=i-1)
+ begin
+ if (Viol != 0)
+ WData[i] = -1;
+ else
+ WData[i] = WByte[i];
+ end
+ end
+ else if ((Address < 8'h10 || (Address > 8'h13 &&
+ Address < 8'h20) || Address > 12'h3FF ))
+ begin
+ Status_reg1[6] = 1'b1;//P_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ if (Address < 8'h20)
+ begin
+ $display ("Given address is ");
+ $display ("in reserved address range");
+ end
+ else if (Address > 12'h3FF)
+ begin
+ $display ("Given address is ");
+ $display ("out of OTP address range");
+ end
+ end
+ else
+ begin
+ //P_ERR bit will be set when the user attempts to
+ // to program within locked OTP region
+ Status_reg1[6] = 1'b1;//P_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ else
+ begin
+ //P_ERR bit will be set when the user attempts to
+ //to program within locked OTP region
+ Status_reg1[6] = 1'b1;//P_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ else if ((Instruct == SE || Instruct == SE4) && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ if (UniformSec || (TopBoot && sect < 510) ||
+ (BottomBoot && sect > 31))
+ begin
+ SectorSuspend = sect;
+ PARAM_REGION = 0;
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ begin
+ ESTART = 1'b1;
+ ESTART <= #5 1'b0;
+ ESUSP = 0;
+ ERES = 0;
+ INITIAL_CONFIG = 1;
+ Status_reg1[0] = 1'b1;
+ Addr = Address;
+ end
+ else
+ begin
+ //E_ERR bit will be set when the user attempts to
+ //erase an individual protected main memory sector
+ Status_reg1[5] = 1'b1;//E_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ else if ((TopBoot && sect >= 510) ||
+ (BottomBoot && sect <= 31))
+ begin
+ if (Sec_ProtSE == 32 && ASP_ProtSE == 32)
+ //Sector erase command is applied to a 64 KB range
+ //that includes 4 KB sectors
+ begin
+ if (TopBoot)
+ begin
+ SectorSuspend = 510 + (541 - sect)/16;
+ end
+ else
+ begin
+ SectorSuspend = sect/16;
+ end
+ PARAM_REGION = 1;
+ ESTART = 1'b1;
+ ESTART <= #5 1'b0;
+ ESUSP = 0;
+ ERES = 0;
+ INITIAL_CONFIG = 1;
+ Status_reg1[0] = 1'b1;
+ Addr = Address;
+ end
+ else
+ begin
+ //E_ERR bit will be set when the user attempts to
+ //erase an individual protected main memory sector
+ Status_reg1[5] = 1'b1;//E_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ end
+ else if ((Instruct == P4E || Instruct == P4E4) && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ if (UniformSec || (TopBoot && sect < 510) ||
+ (BottomBoot && sect > 31))
+ begin
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ else
+ begin
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ //A P4E instruction applied to a sector
+ //that has been Write Protected through the
+ //Block Protect Bits or ASP will not be
+ //executed and will set the E_ERR status
+ begin
+ ESTART = 1'b1;
+ ESTART <= #5 1'b0;
+ ESUSP = 0;
+ ERES = 0;
+ INITIAL_CONFIG = 1;
+ Status_reg1[0] = 1'b1;
+ Addr = Address;
+ end
+ else
+ begin
+ //E_ERR bit will be set when the user attempts to
+ //erase an individual protected main memory sector
+ Status_reg1[5] = 1'b1;//E_ERR
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ end
+ else if (Instruct == BE && WEL == 1)
+ begin
+ if (Status_reg1[4]== 0 && Status_reg1[3]== 0 &&
+ Status_reg1[2]== 0)
+ begin
+ ESTART = 1'b1;
+ ESTART <= #5 1'b0;
+ ESUSP = 0;
+ ERES = 0;
+ INITIAL_CONFIG = 1;
+ Status_reg1[0] = 1'b1;
+ end
+ else
+ begin
+ //The Bulk Erase command will not set E_ERR if a
+ //protected sector is found during the command
+ //execution.
+ Status_reg1[1] = 1'b0;//WEL
+ end
+ end
+ else if (Instruct == PASSP && WEL == 1)
+ begin
+ if (~(PWDMLB== 0 && PSTMLB== 1))
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else
+ begin
+ $display ("Password programming is not allowed");
+ $display (" in Password Protection Mode.");
+ end
+ end
+ else if (Instruct == PASSU && WEL)
+ begin
+ if (~WIP)
+ begin
+ PASSULCK_in = 1;
+ Status_reg1[0] = 1'b1; //WIP
+ end
+ else
+ begin
+ $display ("The PASSU command cannot be accepted");
+ $display (" any faster than once every 100us");
+ end
+ end
+ else if (Instruct == BRWR)
+ begin
+ Bank_Addr_reg[7] = Bank_Addr_reg_in[7];
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ else if (Instruct == WRR && BAR_ACC == 1)
+ begin
+ // Write to the lower address bits of the BAR
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ end
+ else if (Instruct == ASPP && WEL == 1)
+ begin
+ if (~(ASPOTPFLAG))
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else
+ begin
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1;
+ $display ("Once the Protection Mode is selected,");
+ $display ("no further changes to the ASP ");
+ $display ("register is allowed.");
+ end
+ end
+ else if (Instruct == ABWR && WEL == 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == PPBP && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == PPBERS && WEL == 1)
+ begin
+ if (PPBOTP)
+ begin
+ PPBERASE_in = 1'b1;
+ Status_reg1[0] = 1'b1;
+ end
+ else
+ begin
+ Status_reg1[5] = 1'b1;
+ end
+ end
+ else if (Instruct == PLBWR && WEL == 1 &&
+ RdPswdProtEnable == 0)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == DYBWR && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == PNVDLR && WEL == 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == WVDLR && WEL == 1)
+ begin
+ VDLR_reg = VDLR_reg_in;
+ Status_reg1[1] = 1'b0;
+ end
+ else if (Instruct == CLSR)
+ begin
+ //The Clear Status Register Command resets bit SR1[5]
+ //(Erase Fail Flag) and bit SR1[6] (Program Fail Flag)
+ Status_reg1[5] = 0;
+ Status_reg1[6] = 0;
+ end
+
+ if (Instruct == BRAC && P_ERR == 0 && E_ERR == 0)
+ begin
+ BAR_ACC = 1;
+ end
+ else
+ begin
+ BAR_ACC = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ if (Instruct == READ || Instruct == RD4 ||
+ Instruct == RES ||
+ (Instruct == DLPRD && RdPswdProtMode == 0))
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DDRDIOR || Instruct == DDRDIOR4 ||
+ ((Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ && QUAD))
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ ((Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4)
+ && QUAD))
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+ else if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == ECCRD)
+ begin
+ //Read ECC Register
+ SOut_zd = ECCSR[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == READ || Instruct == RD4 ||
+ Instruct == FSTRD || Instruct == FSTRD4 ||
+ Instruct == DDRFR || Instruct == DDRFR4 )
+ begin
+ //Read Memory array
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ if ((Instruct == DDRFR || Instruct == DDRFR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP) is enabled
+ // Optional DLP
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+
+ end
+ else
+ begin
+ read_addr_tmp = read_addr;
+ SecAddr = read_addr/(SecSize+1) ;
+ Sec_addr = read_addr - SecAddr*(SecSize+1);
+ SecAddr = ReturnSectorIDRdPswdMd(TBPROT);
+ read_addr = Sec_addr + SecAddr*(SecSize+1);
+ if (RdPswdProtMode == 0)
+ begin
+ read_addr = read_addr_tmp;
+ end
+ if (Mem[read_addr] !== -1)
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ end
+ else
+ begin
+ SOut_zd = 8'bx;
+ end
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == DDRDIOR || Instruct == DDRDIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((Instruct == DDRDIOR || Instruct == DDRDIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 0;
+ end
+ end
+ else
+ begin
+ read_addr_tmp = read_addr;
+ SecAddr = read_addr/(SecSize+1) ;
+ Sec_addr = read_addr - SecAddr*(SecSize+1);
+ SecAddr = ReturnSectorIDRdPswdMd(TBPROT);
+ read_addr = Sec_addr + SecAddr*(SecSize+1);
+ if (RdPswdProtMode == 0)
+ read_addr = read_addr_tmp;
+
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-2*read_cnt];
+ SIOut_zd = data_out[6-2*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if ((Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4 ||
+ Instruct == DDRQIOR || Instruct == DDRQIOR4 )
+ && QUAD)
+ begin
+ //Read Memory array
+ if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((Instruct == DDRQIOR || Instruct == DDRQIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP) is enabled
+ // Optional DLP
+ data_out[7:0] = VDLR_reg;
+ HOLDNegOut_zd = data_out[7-read_cnt];
+ WPNegOut_zd = data_out[7-read_cnt];
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ read_addr_tmp = read_addr;
+ SecAddr = read_addr/(SecSize+1) ;
+ Sec_addr = read_addr - SecAddr*(SecSize+1);
+ SecAddr = ReturnSectorIDRdPswdMd(TBPROT);
+ read_addr = Sec_addr + SecAddr*(SecSize+1);
+ if (RdPswdProtMode == 0)
+ read_addr = read_addr_tmp;
+
+ data_out[7:0] = Mem[read_addr];
+ HOLDNegOut_zd = data_out[7-4*read_cnt];
+ WPNegOut_zd = data_out[6-4*read_cnt];
+ SOut_zd = data_out[5-4*read_cnt];
+ SIOut_zd = data_out[4-4*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == OTPR)
+ begin
+ if(read_addr>=OTPLoAddr && read_addr<=OTPHiAddr
+ && RdPswdProtMode == 0)
+ begin
+ //Read OTP Memory array
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ data_out[7:0] = OTPMem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ read_addr = read_addr + 1;
+ end
+ end
+ else if ((read_addr > OTPHiAddr)||(RdPswdProtMode==1))
+ begin
+ //OTP Read operation will not wrap to the
+ //starting address after the OTP address is at
+ //its maximum or Read Password Protection Mode
+ //is selected instead, the data beyond the
+ //maximum OTP address will be undefined.
+ SOut_zd = 1'bX;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (Instruct == REMS)
+ begin
+ //Read Manufacturer and Device ID
+ if (read_addr % 2 == 0)
+ begin
+ data_out[7:0] = Manuf_ID;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ read_addr = read_addr + 1;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = DeviceID;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ read_addr = 0;
+ end
+ end
+ end
+ else if (Instruct == RDID)
+ begin
+ ident_out = CFI_array_tmp;
+ if(read_cnt < 648)
+ begin
+ SOut_zd = ident_out[647-read_cnt];
+ read_cnt = read_cnt + 1;
+ end
+ else
+ begin
+ //Continued shifting of output beyond the end of
+ //the defined ID-CFI address space will
+ //provide undefined data.
+ SOut_zd = 1'bX;
+ end
+ end
+ else if (Instruct == RES)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ data_out = ESignature;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == DLPRD && RdPswdProtMode == 0)
+ begin
+ //Read DLP
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = VDLR_reg[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == ABRD && RdPswdProtMode == 0)
+ begin
+ //Read AutoBoot register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = AutoBoot_reg_in[31-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 32)
+ read_cnt = 0;
+ end
+ else if (Instruct == BRRD && RdPswdProtMode == 0)
+ begin
+ //Read Bank Address Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = Bank_Addr_reg[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == ASPRD && RdPswdProtMode == 0)
+ begin
+ //Read ASP Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = ASP_reg[15-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 16)
+ read_cnt = 0;
+ end
+ else if (Instruct == PASSRD && RdPswdProtMode == 0)
+ begin
+ //Read Password Register
+ if (~(PWDMLB == 0 && PSTMLB == 1))
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd =
+ Password_reg[(8*byte_cnt-1)-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ byte_cnt = byte_cnt + 1;
+ if (byte_cnt == 9)
+ byte_cnt = 1;
+ end
+ end
+ end
+ else if (Instruct == PLBRD)
+ begin
+ //Read PPB Lock Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = PPBL[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == DYBRD)
+ begin
+ //Read DYB Access Register
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ DYBAR[7:0] = 8'bXXXXXXXX;
+
+ if (RdPswdProtMode == 0)
+ begin
+ if (DYB_bits[sect] == 1)
+ DYBAR[7:0] = 8'hFF;
+ else
+ begin
+ DYBAR[7:0] = 8'h0;
+ end
+ end
+ SOut_zd = DYBAR[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == PPBRD)
+ begin
+ //Read PPB Access Register
+ ReturnSectorID(sect,Address);
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ PPBAR[7:0] = 8'bXXXXXXXX;
+ if (RdPswdProtMode == 0)
+ begin
+ if (PPB_bits[sect] == 1)
+ PPBAR[7:0] = 8'hFF;
+ else
+ begin
+ PPBAR[7:0] = 8'h0;
+ end
+ end
+ SOut_zd = PPBAR[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ end
+
+ AUTOBOOT:
+ begin
+ if (start_autoboot == 1)
+ begin
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (QUAD == 1)
+ begin
+ if (ABSD > 0) //If ABSD > 0,
+ begin //max SCK frequency is 104MHz
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else // If ABSD = 0, max SCK frequency is 50 MHz
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ data_out[7:0] = Mem[read_addr];
+ HOLDNegOut_zd = data_out[7-4*read_cnt];
+ WPNegOut_zd = data_out[6-4*read_cnt];
+ SOut_zd = data_out[5-4*read_cnt];
+ SIOut_zd = data_out[4-4*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ read_addr = read_addr + 1;
+ end
+ end
+ else
+ begin
+ if (ABSD > 0) //If ABSD > 0,
+ begin //max SCK frequency is 133MHz
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else // If ABSD = 0, max SCK frequency is 50 MHz
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (oe_z)
+ begin
+ if (QUAD == 1)
+ begin
+ if (ABSD > 0) //If ABSD > 0,
+ begin //max SCK frequency is 104MHz
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else // If ABSD = 0, max SCK frequency is 50 MHz
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ end
+ else
+ begin
+ if (ABSD > 0) //If ABSD > 0,
+ begin //max SCK frequency is 133MHz
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else // If ABSD = 0, max SCK frequency is 50 MHz
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ end
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+ end
+ end
+
+ WRITE_SR:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (WDONE == 1)
+ begin
+ Status_reg1[0] = 1'b0; //WIP
+ Status_reg1[1] = 1'b0; //WEL
+ //SRWD bit
+ Status_reg1[7] = Status_reg1_in[7]; //MSB first
+
+// if (LOCK == 0)
+// begin
+ if (FREEZE == 0)
+ //The Freeze Bit, when set to 1, locks the current
+ //state of the BP2-0 bits in Status Register,
+ //the TBPROT and TBPARM bits in the Config Register
+ //As long as the FREEZE bit remains cleared to logic
+ //'0', the other bits of the Configuration register
+ //including FREEZE are writeable.
+ begin
+ Status_reg1[4] = Status_reg1_in[4];//BP2
+ Status_reg1[3] = Status_reg1_in[3];//BP1
+ Status_reg1[2] = Status_reg1_in[2];//BP0
+
+ BP_bits = {Status_reg1[4],Status_reg1[3],
+ Status_reg1[2]};
+ if (TBPROT == 1'b0 && INITIAL_CONFIG == 1'b0)
+ begin
+ Config_reg1[5] = Config_reg1_in[5];//TBPROT
+ end
+ if (TBPARM == 1'b0 && INITIAL_CONFIG == 1'b0 &&
+ tmp_char2 == "0")
+ begin
+ Config_reg1[2] = Config_reg1_in[2];//TBPARM
+ change_TBPARM = 1'b1;
+ #1000 change_TBPARM = 1'b0;
+ end
+ change_BP = 1'b1;
+ #1000 change_BP = 1'b0;
+ end
+// end
+
+ Config_reg1[7] = Config_reg1_in[7];//LC1
+ Config_reg1[6] = Config_reg1_in[6];//LC0
+ Config_reg1[1] = Config_reg1_in[1];//QUAD
+
+ if (FREEZE == 1'b0)
+ begin
+ Config_reg1[0] = Config_reg1_in[0];//FREEZE
+ end
+
+// if (WRLOCKENABLE== 1'b1 && LOCK == 1'b0)
+// begin
+// Config_reg1[4] = Config_reg1_in[4];//LOCK
+// WRLOCKENABLE = 1'b0;
+// end
+ if (BPNV == 1'b0)
+ begin
+ Config_reg1[3] = Config_reg1_in[3];//BPNV
+ end
+ end
+ end
+
+ PAGE_PG :
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if(current_state_event && current_state == PAGE_PG)
+ begin
+ if (~PDONE)
+ begin
+ ADDRHILO_PG(AddrLo, AddrHi, Addr);
+ cnt = 0;
+
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ new_int = WData[i];
+ old_int = Mem[Addr + i - cnt];
+ if (new_int > -1)
+ begin
+ new_bit = new_int;
+ if (old_int > -1)
+ begin
+ old_bit = old_int;
+ for(j=0;j<=7;j=j+1)
+ begin
+ if (~old_bit[j])
+ new_bit[j]=1'b0;
+ end
+ new_int=new_bit;
+ end
+ WData[i]= new_int;
+ end
+ else
+ begin
+ WData[i] = -1;
+ end
+
+ Mem[Addr + i - cnt] = - 1;
+ if ((Addr + i) == AddrHi)
+ begin
+
+ Addr = AddrLo;
+ cnt = i + 1;
+ end
+ end
+ end
+ cnt = 0;
+ end
+
+ if (PDONE)
+ begin
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ quad_pg = 0;
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ Mem[Addr_tmp + i - cnt] = WData[i];
+ if ((Addr_tmp + i) == AddrHi)
+ begin
+ Addr_tmp = AddrLo;
+ cnt = i + 1;
+ end
+ end
+ end
+
+ if (Instruct)
+ begin
+ if (Instruct == PGSP && ~PRGSUSP_in)
+ begin
+ if (~RES_TO_SUSP_MIN_TIME)
+ begin
+ PGSUSP = 1'b1;
+ PGSUSP <= #5 1'b0;
+ PRGSUSP_in = 1'b1;
+ if (RES_TO_SUSP_TYP_TIME)
+ begin
+ $display("Typical periods are needed for ",
+ "Program to progress to completion");
+ end
+ end
+ else
+ begin
+ $display("Minimum for tPRS is not satisfied! ",
+ "PGSP command is ignored");
+ end
+ end
+ end
+ end
+
+ PG_SUSP:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+
+ if (PRGSUSP_out && PRGSUSP_in)
+ begin
+ PRGSUSP_in = 1'b0;
+ //The RDY/BSY bit in the Status Register will indicate that
+ //the device is ready for another operation.
+ Status_reg1[0] = 1'b0;
+ //The Program Suspend (PS) bit in the Status Register will
+ //be set to the logical “1” state to indicate that the
+ //program operation has been suspended.
+ Status_reg2[0] = 1'b1;
+ PDONE = 1'b1;
+ end
+
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == BRRD)
+ begin
+ //Read Bank Address Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = Bank_Addr_reg[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ //Read Array Operations
+ else if (Instruct == READ || Instruct == RD4 ||
+ Instruct == FSTRD || Instruct == FSTRD4 ||
+ Instruct == DDRFR || Instruct == DDRFR4 )
+ begin
+ //Read Memory array
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ if (pgm_page != read_addr / (PageSize+1))
+ begin
+ if ((Instruct == DDRFR || Instruct == DDRFR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+
+ end
+ end
+ else
+ begin
+ SOut_zd = 8'bxxxxxxxx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == DDRDIOR || Instruct == DDRDIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if (pgm_page != read_addr / (PageSize+1))
+ begin
+ if ((Instruct == DDRDIOR || Instruct == DDRDIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-2*read_cnt];
+ SIOut_zd = data_out[6-2*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4 ||
+ Instruct == DDRQIOR || Instruct == DDRQIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if (pgm_page != read_addr / (PageSize+1))
+ begin
+ if ((Instruct == DDRQIOR || Instruct == DDRQIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ HOLDNegOut_zd= data_out[7-read_cnt];
+ WPNegOut_zd = data_out[7-read_cnt];
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ HOLDNegOut_zd = data_out[7-4*read_cnt];
+ WPNegOut_zd = data_out[6-4*read_cnt];
+ SOut_zd = data_out[5-4*read_cnt];
+ SIOut_zd = data_out[4-4*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ HOLDNegOut_zd = 1'bx;
+ WPNegOut_zd = 1'bx;
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ end
+ else if (oe_z)
+ begin
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (falling_edge_write)
+ begin
+ if (Instruct == BRWR)
+ begin
+ Bank_Addr_reg[7] = Bank_Addr_reg_in[7];
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ else if (Instruct == WRR && BAR_ACC == 1)
+ begin
+ // Write to the lower address bits of the BAR
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ end
+ else if (Instruct == PGRS)
+ begin
+ Status_reg2[0] = 1'b0;
+ Status_reg1[0] = 1'b1;
+ PGRES = 1'b1;
+ PGRES <= #5 1'b0;
+ RES_TO_SUSP_MIN_TIME = 1'b1;
+ RES_TO_SUSP_MIN_TIME <= #60000 1'b0;//60 ns
+ RES_TO_SUSP_TYP_TIME = 1'b1;
+ RES_TO_SUSP_TYP_TIME <= #100000000 1'b0;//100us
+ end
+
+ if (Instruct == BRAC && P_ERR == 0 && E_ERR == 0 &&
+ RdPswdProtMode == 0)
+ begin
+ BAR_ACC = 1;
+ end
+ else
+ begin
+ BAR_ACC = 0;
+ end
+ end
+ end
+
+ ERS_SUSP_PG_SUSP:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+
+ if (PRGSUSP_out && PRGSUSP_in)
+ begin
+ PRGSUSP_in = 1'b0;
+ //The RDY/BSY bit in the Status Register will indicate that
+ //the device is ready for another operation.
+ Status_reg1[0] = 1'b0;
+ //The Program Suspend (PS) bit in the Status Register will
+ //be set to the logical “1” state to indicate that the
+ //program operation has been suspended.
+ Status_reg2[0] = 1'b1;
+ end
+
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == BRRD)
+ begin
+ //Read Bank Address Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = Bank_Addr_reg[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ //Read Array Operations
+ else if (Instruct == READ || Instruct == RD4 ||
+ Instruct == FSTRD || Instruct == FSTRD4 ||
+ Instruct == DDRFR || Instruct == DDRFR4 )
+ begin
+ //Read Memory array
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ if ((SectorSuspend != read_addr/(SecSize+1)) &&
+ (pgm_page != read_addr / (PageSize+1)))
+ begin
+ if ((Instruct == DDRFR || Instruct == DDRFR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+
+ end
+ end
+ else
+ begin
+ SOut_zd = 8'bxxxxxxxx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == DDRDIOR || Instruct == DDRDIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((SectorSuspend != read_addr/(SecSize+1)) &&
+ (pgm_page != read_addr / (PageSize+1)))
+ begin
+ if ((Instruct == DDRDIOR || Instruct == DDRDIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-2*read_cnt];
+ SIOut_zd = data_out[6-2*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4 ||
+ Instruct == DDRQIOR || Instruct == DDRQIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((SectorSuspend != read_addr/(SecSize+1)) &&
+ (pgm_page != read_addr / (PageSize+1)))
+ begin
+ if ((Instruct == DDRQIOR || Instruct == DDRQIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ HOLDNegOut_zd =data_out[7-read_cnt];
+ WPNegOut_zd = data_out[7-read_cnt];
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ HOLDNegOut_zd = data_out[7-4*read_cnt];
+ WPNegOut_zd = data_out[6-4*read_cnt];
+ SOut_zd = data_out[5-4*read_cnt];
+ SIOut_zd = data_out[4-4*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ HOLDNegOut_zd = 1'bx;
+ WPNegOut_zd = 1'bx;
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ end
+ else if (oe_z)
+ begin
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (falling_edge_write)
+ begin
+ if (Instruct == BRWR)
+ begin
+ Bank_Addr_reg[7] = Bank_Addr_reg_in[7];
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ else if (Instruct == WRR && BAR_ACC == 1)
+ begin
+ // Write to the lower address bits of the BAR
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ end
+ else if (Instruct == PGRS)
+ begin
+ Status_reg2[0] = 1'b0;
+ Status_reg1[0] = 1'b1;
+ PGRES = 1'b1;
+ PGRES <= #5 1'b0;
+ RES_TO_SUSP_MIN_TIME = 1'b1;
+ RES_TO_SUSP_MIN_TIME <= #60000 1'b0;//60 ns
+ RES_TO_SUSP_TYP_TIME = 1'b1;
+ RES_TO_SUSP_TYP_TIME <= #100000000 1'b0;//100us
+ end
+
+ if (Instruct == BRAC && P_ERR == 0 && E_ERR == 0 &&
+ RdPswdProtMode == 0)
+ begin
+ BAR_ACC = 1;
+ end
+ else
+ begin
+ BAR_ACC = 0;
+ end
+ end
+ end
+
+ OTP_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if(current_state_event && current_state == OTP_PG)
+ begin
+ if (~PDONE)
+ begin
+ if (Address + wr_cnt <= OTPHiAddr)
+ begin
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ new_int = WData[i];
+ old_int = OTPMem[Addr + i];
+ if (new_int > -1)
+ begin
+ new_bit = new_int;
+ if (old_int > -1)
+ begin
+ old_bit = old_int;
+ for(j=0;j<=7;j=j+1)
+ begin
+ if (~old_bit[j])
+ new_bit[j] = 1'b0;
+ end
+ new_int = new_bit;
+ end
+ WData[i] = new_int;
+ end
+ else
+ begin
+ WData[i] = -1;
+ end
+ OTPMem[Addr + i] = -1;
+ end
+ end
+ else
+ begin
+ $display ("Programming will reach over ");
+ $display ("address limit of OTP array");
+ end
+ end
+ end
+
+ if (PDONE)
+ begin
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ OTPMem[Addr + i] = WData[i];
+ end
+ LOCK_BYTE1 = OTPMem[16];
+ LOCK_BYTE2 = OTPMem[17];
+ LOCK_BYTE3 = OTPMem[18];
+ LOCK_BYTE4 = OTPMem[19];
+ end
+ end
+
+ SECTOR_ERS:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if(current_state_event && current_state == SECTOR_ERS)
+ begin
+ if (~EDONE)
+ begin
+ ADDRHILO_SEC(AddrLo, AddrHi, Addr);
+ for (i=AddrLo;i<=AddrHi;i=i+1)
+ begin
+ Mem[i] = -1;
+ end
+ end
+ end
+
+ if (EDONE == 1)
+ begin
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ for (i=AddrLo;i<=AddrHi;i=i+1)
+ begin
+ Mem[i] = MaxData;
+
+ pgm_page = i / (PageSize+1);
+// QPP_page[pgm_page] = 1'b0;
+ end
+ end
+ else if (Instruct == ERSP && ~ERSSUSP_in)
+ begin
+ ESUSP = 1'b1;
+ ESUSP <= #5 1'b0;
+ ERSSUSP_in = 1'b1;
+ if (RES_TO_SUSP_TYP_TIME)
+ begin
+ $display("Typical periods are needed for ",
+ "Program to progress to completion");
+ end
+ end
+ end
+
+ BULK_ERS:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if(current_state_event && current_state == BULK_ERS)
+ begin
+ if (~EDONE)
+ begin
+ for (i=0;i<=AddrRANGE;i=i+1)
+ begin
+ ReturnSectorID(sect,i);
+ if (PPB_bits[sect] == 1 && DYB_bits[sect] == 1)
+ begin
+ Mem[i] = -1;
+ end
+ end
+
+ end
+ end
+
+ if (EDONE == 1)
+ begin
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ for (i=0;i<=AddrRANGE;i=i+1)
+ begin
+ ReturnSectorID(sect,i);
+ if (PPB_bits[sect] == 1 && DYB_bits[sect] == 1)
+ begin
+ Mem[i] = MaxData;
+
+ pgm_page = i / (PageSize+1);
+// QPP_page[pgm_page] = 1'b0;
+ end
+ end
+ end
+ end
+
+ ERS_SUSP:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (ERSSUSP_out == 1)
+ begin
+ ERSSUSP_in = 0;
+ //The Erase Suspend (ES) bit in the Status Register will
+ //be set to the logical “1” state to indicate that the
+ //erase operation has been suspended.
+ Status_reg2[1] = 1'b1;
+ //The WIP bit in the Status Register will indicate that
+ //the device is ready for another operation.
+ Status_reg1[0] = 1'b0;
+ end
+
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == DYBRD)
+ begin
+ //Read DYB Access Register
+ ReturnSectorID(sect,Address);
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (DYB_bits[sect] == 1)
+ DYBAR[7:0] = 8'hFF;
+ else
+ begin
+ DYBAR[7:0] = 8'h0;
+ end
+ SOut_zd = DYBAR[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == BRRD)
+ begin
+ //Read Bank Address Register
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ SOut_zd = Bank_Addr_reg[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == PPBRD)
+ begin
+ //Read PPB Access Register
+ ReturnSectorID(sect,Address);
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ PPBAR[7:0] = 8'bXXXXXXXX;
+ if (RdPswdProtMode == 0)
+ begin
+ if (PPB_bits[sect] == 1)
+ PPBAR[7:0] = 8'hFF;
+ else
+ begin
+ PPBAR[7:0] = 8'h0;
+ end
+ end
+ SOut_zd = PPBAR[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == READ || Instruct == RD4 ||
+ Instruct == FSTRD || Instruct == FSTRD4 ||
+ Instruct == DDRFR || Instruct == DDRFR4 )
+ begin
+ //Read Memory array
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ if ((PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)) ||
+ (~PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)+30*b_act))
+ begin
+ if ((Instruct == DDRFR || Instruct == DDRFR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ SOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == DDRDIOR || Instruct == DDRDIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)) ||
+ (~PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)+30*b_act))
+ begin
+ if ((Instruct == DDRDIOR || Instruct == DDRDIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ SOut_zd = data_out[7-2*read_cnt];
+ SIOut_zd = data_out[6-2*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 4)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else if (Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4 ||
+ Instruct == DDRQIOR || Instruct == DDRQIOR4 )
+ begin
+ //Read Memory array
+ if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ if ((PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)) ||
+ (~PARAM_REGION &&
+ SectorSuspend != read_addr/(SecSize+1)+30*b_act))
+ begin
+ if ((Instruct == DDRQIOR || Instruct == DDRQIOR4) &&
+ (VDLR_reg != 8'b00000000) && start_dlp)
+ begin
+ // Data Learning Pattern (DLP)
+ // is enabled Optional DLP
+ data_out[7:0] = VDLR_reg;
+ HOLDNegOut_zd= data_out[7-read_cnt];
+ WPNegOut_zd = data_out[7-read_cnt];
+ SOut_zd = data_out[7-read_cnt];
+ SIOut_zd = data_out[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ begin
+ read_cnt = 0;
+ start_dlp = 1'b0;
+ end
+ end
+ else
+ begin
+ data_out[7:0] = Mem[read_addr];
+ HOLDNegOut_zd = data_out[7-4*read_cnt];
+ WPNegOut_zd = data_out[6-4*read_cnt];
+ SOut_zd = data_out[5-4*read_cnt];
+ SIOut_zd = data_out[4-4*read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ else
+ begin
+ HOLDNegOut_zd = 1'bx;
+ WPNegOut_zd = 1'bx;
+ SOut_zd = 1'bx;
+ SIOut_zd = 1'bx;
+ if (read_cnt == 2)
+ begin
+ read_cnt = 0;
+ if (read_addr == AddrRANGE)
+ read_addr = 0;
+ else
+ read_addr = read_addr + 1;
+ end
+ end
+ end
+ end
+ else if (oe_z)
+ begin
+ if (Instruct == READ || Instruct == RD4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b1;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else if (Instruct == DOR || Instruct == DOR4 ||
+ Instruct == DIOR || Instruct == DIOR4 ||
+ Instruct == QOR || Instruct == QOR4 ||
+ Instruct == QIOR || Instruct == QIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b0;
+ end
+ else if (Instruct == DDRQIOR || Instruct == DDRQIOR4)
+ begin
+ rd_fast = 1'b0;
+ rd_slow = 1'b0;
+ dual = 1'b1;
+ ddr = 1'b1;
+ end
+ else
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ end
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (falling_edge_write)
+ begin
+ if ((Instruct == PP || Instruct == PP4) && WEL == 1)
+ begin
+ if ((PARAM_REGION &&
+ SectorSuspend != Address/(SecSize+1)) ||
+ (~PARAM_REGION &&
+ SectorSuspend != Address/(SecSize+1)+30*b_act))
+ begin
+ ReturnSectorID(sect,Address);
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ PGSUSP = 0;
+ PGRES = 0;
+ Status_reg1[0] = 1'b1;
+ SA = sect;
+ Addr = Address;
+ Addr_tmp= Address;
+ wr_cnt = Byte_number;
+ for (i=wr_cnt;i>=0;i=i-1)
+ begin
+ if (Viol != 0)
+ WData[i] = -1;
+ else
+ WData[i] = WByte[i];
+ end
+ end
+ else
+ begin
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1;
+ end
+ end
+ else
+ begin
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1;
+ end
+ end
+ else if ((Instruct == QPP || Instruct == QPP4) && WEL == 1)
+ begin
+ if ((PARAM_REGION &&
+ SectorSuspend != Address/(SecSize+1)) ||
+ (~PARAM_REGION &&
+ SectorSuspend != Address/(SecSize+1)+30*b_act))
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+
+ if (Sec_Prot[sect] == 0 &&
+ PPB_bits[sect]== 1 && DYB_bits[sect]== 1)
+ begin
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ PGSUSP = 0;
+ PGRES = 0;
+ Status_reg1[0] = 1'b1;
+// QPP_page[pgm_page] = 1'b1;
+ SA = sect;
+ Addr = Address;
+ Addr_tmp= Address;
+ wr_cnt = Byte_number;
+ for (i=wr_cnt;i>=0;i=i-1)
+ begin
+ if (Viol != 0)
+ WData[i] = -1;
+ else
+ WData[i] = WByte[i];
+ end
+ end
+ else
+ begin
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1;
+ end
+ end
+ else
+ begin
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1;
+ end
+ end
+ else if (Instruct == WREN)
+ Status_reg1[1] = 1'b1;
+ else if (Instruct == CLSR)
+ begin
+ //The Clear Status Register Command resets bit SR1[5]
+ //(Erase Fail Flag) and bit SR1[6] (Program Fail Flag)
+ Status_reg1[5] = 0;
+ Status_reg1[6] = 0;
+ end
+ else if (Instruct == BRWR)
+ begin
+ Bank_Addr_reg[7] = Bank_Addr_reg_in[7];
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ else if (Instruct == WRR && BAR_ACC == 1)
+ begin
+ // Write to the lower address bits of the BAR
+ if (P_ERR == 0 && E_ERR == 0)
+ begin
+ Bank_Addr_reg[0] = Bank_Addr_reg_in[0];
+ if(Bank_Addr_reg_in[1] == 1)
+ begin
+ $display ("WARNING: Changing values of ");
+ $display ("Bank Address Register");
+ $display ("BA25 is not allowed!!!");
+ end
+ end
+ end
+ else if (Instruct == DYBWR && WEL == 1)
+ begin
+ ReturnSectorID(sect,Address);
+ pgm_page = Address / (PageSize+1);
+ PSTART = 1'b1;
+ PSTART <= #5 1'b0;
+ Status_reg1[0] = 1'b1;
+ end
+ else if (Instruct == ERRS)
+ begin
+ Status_reg2[1] = 1'b0;
+ Status_reg1[0] = 1'b1;
+ if (BottomBoot)
+ begin
+ if (PARAM_REGION)
+ begin
+ Addr = SectorSuspend*(SecSize+1);
+ end
+ else
+ begin
+ Addr = (SectorSuspend-30)*(SecSize+1);
+ end
+ end
+ else
+ begin
+ Addr = SectorSuspend*(SecSize+1);
+ end
+ ADDRHILO_SEC(AddrLo, AddrHi, Addr);
+ ERES = 1'b1;
+ ERES <= #5 1'b0;
+ RES_TO_SUSP_TYP_TIME = 1'b1;
+ RES_TO_SUSP_TYP_TIME <= #100000000 1'b0;//100us
+ end
+
+ if (Instruct == BRAC && P_ERR == 0 && E_ERR == 0 &&
+ RdPswdProtMode == 0)
+ begin
+ BAR_ACC = 1;
+ end
+ else
+ begin
+ BAR_ACC = 0;
+ end
+ end
+ end
+
+ ERS_SUSP_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if(current_state_event && current_state == ERS_SUSP_PG)
+ begin
+ if (~PDONE)
+ begin
+ ADDRHILO_PG(AddrLo, AddrHi, Addr);
+ cnt = 0;
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ new_int = WData[i];
+ old_int = Mem[Addr + i - cnt];
+ if (new_int > -1)
+ begin
+ new_bit = new_int;
+ if (old_int > -1)
+ begin
+ old_bit = old_int;
+ for(j=0;j<=7;j=j+1)
+ begin
+ if (~old_bit[j])
+ new_bit[j] = 1'b0;
+ end
+ new_int = new_bit;
+ end
+ WData[i] = new_int;
+ end
+ else
+ begin
+ WData[i] = -1;
+ end
+
+ if ((Addr + i) == AddrHi)
+ begin
+ Addr = AddrLo;
+ cnt = i + 1;
+ end
+ end
+ end
+ cnt =0;
+ end
+
+ if(PDONE == 1)
+ begin
+ Status_reg1[0] = 1'b0;//WIP
+ Status_reg1[1] = 1'b0;//WEL
+ for (i=0;i<=wr_cnt;i=i+1)
+ begin
+ Mem[Addr_tmp + i - cnt] = WData[i];
+ if ((Addr_tmp + i) == AddrHi )
+ begin
+ Addr_tmp = AddrLo;
+ cnt = i + 1;
+ end
+ end
+ end
+
+ if (Instruct)
+ begin
+ if (Instruct == PGSP && ~PRGSUSP_in)
+ begin
+ if (~RES_TO_SUSP_MIN_TIME)
+ begin
+ PGSUSP = 1'b1;
+ PGSUSP <= #5 1'b0;
+ PRGSUSP_in = 1'b1;
+ if (RES_TO_SUSP_TYP_TIME)
+ begin
+ $display("Typical periods are needed for ",
+ "Program to progress to completion");
+ end
+ end
+ else
+ begin
+ $display("Minimum for tPRS is not satisfied! ",
+ "PGSP command is ignored");
+ end
+ end
+ end
+ end
+
+ PASS_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ new_pass = Password_reg_in;
+ old_pass = Password_reg;
+ for (i=0;i<=63;i=i+1)
+ begin
+ if (old_pass[j] == 0)
+ new_pass[j] = 0;
+ end
+
+ if (PDONE == 1)
+ begin
+ Password_reg = new_pass;
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+
+ PASS_UNLOCK:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PASS_TEMP == Password_reg)
+ begin
+ PASS_UNLOCKED = 1'b1;
+ end
+ else
+ begin
+ PASS_UNLOCKED = 1'b0;
+ end
+ if (PASSULCK_out == 1'b1)
+ begin
+ if ((PASS_UNLOCKED == 1'b1) && (~PWDMLB))
+ begin
+ PPBL[0] = 1'b1;
+ Status_reg1[0] = 1'b0; //WIP
+ end
+ else
+ begin
+ Status_reg1[6] = 1'b1;
+ $display ("Incorrect Password");
+ PASSACC_in = 1'b1;
+ end
+ Status_reg1[1] = 1'b0;
+ PASSULCK_in = 1'b0;
+ end
+ end
+
+ PPB_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+ if (PPB_LOCK !== 0)
+ begin
+ PPB_bits[sect]= 1'b0;
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ else
+ begin
+ Status_reg1[5] = 1'b0;
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+ end
+
+ PPB_ERS:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PPBERASE_out == 1'b1)
+ begin
+ if ((PPB_LOCK !== 0) && PPBOTP)
+ begin
+ PPB_bits = {542{1'b1}};
+ end
+ else
+ begin
+ Status_reg1[5] = 1'b1;
+ end
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ PPBERASE_in = 1'b0;
+ end
+ end
+
+ AUTOBOOT_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register 2
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+ for(i=0;i<=3;i=i+1)
+ for(j=0;j<=7;j=j+1)
+ AutoBoot_reg[i*8+j] =
+ AutoBoot_reg_in[(3-i)*8+j];
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+
+ PLB_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+ PPBL[0] = 1'b0;
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+
+ DYB_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+ DYBAR = DYBAR_in;
+ if (DYBAR == 8'hFF)
+ begin
+ DYB_bits[sect]= 1'b1;
+ end
+ else if (DYBAR == 8'h00)
+ begin
+ DYB_bits[sect]= 1'b0;
+ end
+ else
+ begin
+ Status_reg1[6] = 1'b1;
+ end
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+
+ ASP_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+
+ if (RPME == 1'b0 && ASP_reg_in[5] == 1'b1)
+ begin
+ Status_reg1[6] = 1'b1; //P_ERR
+ $display("RPME bit is allready programmed");
+ end
+ else
+ begin
+ ASP_reg[5] = ASP_reg_in[5];//RPME
+ end
+
+ if (PPBOTP == 1'b0 && ASP_reg_in[3] == 1'b1)
+ begin
+ Status_reg1[6] = 1'b1; //P_ERR
+ $display("PPBOTP bit is allready programmed");
+ end
+ else
+ begin
+ ASP_reg[3] = ASP_reg_in[3];//PPBOTP
+ end
+
+ if (PWDMLB == 1'b1 && PSTMLB == 1'b1)
+ begin
+ if (ASP_reg_in[2] == 1'b0 && ASP_reg_in[1] == 1'b0)
+ begin
+ $display("ASPR[2:1] = 00 Illegal condition");
+ Status_reg1[6] = 1'b1; //P_ERR
+ end
+ else
+ begin
+ if (ASP_reg_in[2]!==1'b1 || ASP_reg_in[1]!==1'b1)
+ begin
+ ASPOTPFLAG = 1'b1;
+ end
+ ASP_reg[2] = ASP_reg_in[2];//PWDMLB
+ ASP_reg[1] = ASP_reg_in[1];//PSTMLB
+ end
+ end
+
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ end
+
+ NVDLR_PG:
+ begin
+ rd_fast = 1'b1;
+ rd_slow = 1'b0;
+ dual = 1'b0;
+ ddr = 1'b0;
+ if (oe)
+ begin
+ any_read = 1'b1;
+ if (Instruct == RDSR)
+ begin
+ //Read Status Register 1
+ SOut_zd = Status_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDSR2)
+ begin
+ //Read Status Register
+ SOut_zd = Status_reg2[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ else if (Instruct == RDCR)
+ begin
+ //Read Configuration Register 1
+ SOut_zd = Config_reg1[7-read_cnt];
+ read_cnt = read_cnt + 1;
+ if (read_cnt == 8)
+ read_cnt = 0;
+ end
+ end
+ else if (oe_z)
+ begin
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ end
+
+ if (PDONE)
+ begin
+ if (NVDLR_reg == 0)
+ begin
+ NVDLR_reg = NVDLR_reg_in;
+ VDLR_reg = NVDLR_reg_in;
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ end
+ else
+ begin
+ Status_reg1[0] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ Status_reg1[6] = 1'b1; //P_ERR
+ $display("NVDLR bits allready programmed");
+ end
+ end
+ end
+
+ RESET_STATE:
+ begin
+ //the default condition hardware reset
+ //The Bank Address Register is loaded to all zeroes
+ Bank_Addr_reg = 8'h0;
+ if (BPNV && ~FREEZE) //&& ~LOCK
+ begin
+ Status_reg1[2] = 1'b1;// BP0
+ Status_reg1[3] = 1'b1;// BP1
+ Status_reg1[4] = 1'b1;// BP2
+ BP_bits = 3'b111;
+ change_BP = 1'b1;
+ #1000 change_BP = 1'b0;
+ end
+ //Resets the volatile bits in the Status register 1
+ Status_reg1[6] = 1'b0;
+ Status_reg1[5] = 1'b0;
+ Status_reg1[1] = 1'b0;
+ Status_reg1[0] = 1'b0;
+ //Resets the volatile bits in the Status register 2
+ Status_reg2[1] = 1'b0;
+ Status_reg2[0] = 1'b0;
+ //Resets the volatile bits in the Configuration register 1
+ Config_reg1[0] = 1'b0;
+ //On reset cycles the data pattern reverts back
+ //to what is in the NVDLR
+ VDLR_reg = NVDLR_reg;
+ start_dlp = 1'b0;
+ //Loads the Program Buffer with all ones
+ for(i=0;i<=511;i=i+1)
+ begin
+ WData[i] = MaxData;
+ end
+ if (~PWDMLB)
+ PPBL[0] = 1'b0;
+ else
+ PPBL[0] = 1'b1;
+ end
+
+ endcase
+
+ //Output Disable Control
+ if (CSNeg_ipd )
+ begin
+ SOut_zd = 1'bZ;
+ SIOut_zd = 1'bZ;
+ HOLDNegOut_zd = 1'bZ;
+ WPNegOut_zd = 1'bZ;
+ end
+ end
+
+ assign fast_rd = rd_fast;
+ assign rd = rd_slow;
+ assign ddrd = ddr && ~ddr80;
+ assign ddrd80 = ddr && ddr80;
+ assign fast_ddr = ddr_fast;
+
+ always @(change_TBPARM, posedge PoweredUp)
+ begin
+ if (tmp_char2 == "0")
+ begin
+ if (TBPARM == 0)
+ begin
+ BottomBoot = 1;
+ b_act = 1;
+ end
+ else
+ begin
+ TopBoot = 1;
+ BottomBoot = 0;
+ b_act = 0;
+ end
+ end
+ else if (tmp_char2 == "1")
+ begin
+ UniformSec = 1;
+ end
+ end
+
+ always @(posedge change_BP)
+ begin
+ case (Status_reg1[4:2])
+
+ 3'b000:
+ begin
+ Sec_Prot[541:0] = {542{1'b0}};
+ end
+ 3'b001:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256:(SecNum256+1)*63/64] = 2'b11;
+ Sec_Prot[(SecNum256+1)*63/64-1 : 0] = 126'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/64-1 : 0] = 2'b11;
+ Sec_Prot[SecNum256 : (SecNum256+1)/64] = 126'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64:(SecNum64-29)*63/64] = {38{1'b1}};
+ Sec_Prot[(SecNum64-29)*63/64-1 : 0] = 504'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/64-1 : 0] = {8{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/64] = 534'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64:(SecNum64-29)*63/64+30] = {8{1'b1}};
+ Sec_Prot[(SecNum64-29)*63/64+29 : 0] = 534'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/64+29 : 0] = {38{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/64+30] = 504'h0;
+ end
+ end
+ end
+
+ 3'b010:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256 : (SecNum256+1)*31/32] = {4{1'b1}};
+ Sec_Prot[(SecNum256+1)*31/32-1 : 0] = 124'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/32-1 : 0] = {4{1'b1}};
+ Sec_Prot[SecNum256 : (SecNum256+1)/32] = 124'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*31/32] = {46{1'b1}};
+ Sec_Prot[(SecNum64-29)*31/32-1 : 0] = 496'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/32-1 : 0] = {16{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/32] = 526'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64:(SecNum64-29)*31/32+30] = {16{1'b1}};
+ Sec_Prot[(SecNum64-29)*31/32+29 : 0] = 526'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/32+29 : 0] = {46{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/32+30] = 496'h0;
+ end
+ end
+ end
+
+ 3'b011:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256 : (SecNum256+1)*15/16] = 8'hFF;
+ Sec_Prot[(SecNum256+1)*15/16-1 : 0] = 120'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/16-1 : 0] = 8'hFF;
+ Sec_Prot[SecNum256 : (SecNum256+1)/16] = 120'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*15/16] = {62{1'b1}};
+ Sec_Prot[(SecNum64-29)*15/16-1 : 0] = 480'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/16-1 : 0] = {32{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/16] = 510'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*15/16+30]={32{1'b1}};
+ Sec_Prot[(SecNum64-29)*15/16+29 : 0] = 510'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/16+29 : 0] ={62{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/16+30] = 480'h0;
+ end
+ end
+ end
+
+ 3'b100:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256 : (SecNum256+1)*7/8] = {16{1'b1}};
+ Sec_Prot[(SecNum256+1)*7/8-1 : 0] = 112'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/8-1 : 0] = {16{1'b1}};
+ Sec_Prot[SecNum256 : (SecNum256+1)/8] = 112'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*7/8] = {94{1'b1}};
+ Sec_Prot[(SecNum64-29)*7/8-1 : 0] = 448'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/8-1 : 0] = {64{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/8] = 478'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*7/8+30] ={64{1'b1}};
+ Sec_Prot[(SecNum64-29)*7/8+29 : 0] = 478'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/8+29 : 0] = {94{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/8+30] = 448'h0;
+ end
+ end
+ end
+
+ 3'b101:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256 : (SecNum256+1)*3/4] = {32{1'b1}};
+ Sec_Prot[(SecNum256+1)*3/4-1 : 0] = 96'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/4-1 : 0] = {32{1'b1}};
+ Sec_Prot[SecNum256 : (SecNum256+1)/4] = 96'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*3/4] = {158{1'b1}};
+ Sec_Prot[(SecNum64-29)*3/4-1 : 0] = 384'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/4-1 : 0] = {128{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/4] = 414'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)*3/4+30] = {128{1'b1}};
+ Sec_Prot[(SecNum64-29)*3/4+29 : 0] = 414'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/4+29 : 0] = {158{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/4+30] = 384'h0;
+ end
+ end
+ end
+
+ 3'b110:
+ begin
+ if (tmp_char2 == "1")
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum256 : (SecNum256+1)/2] = {64{1'b1}};
+ Sec_Prot[(SecNum256+1)/2-1 : 0] = 64'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum256+1)/2-1 : 0] = {64{1'b1}};
+ Sec_Prot[SecNum256 : (SecNum256+1)/2] = 64'h0;
+ end
+ end
+ else if (tmp_char2 == "0" && TBPARM == 1)
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)/2] = {286{1'b1}};
+ Sec_Prot[(SecNum64-29)/2-1 : 0] = 256'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/2-1 : 0] = {256{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/2] = 286'h0;
+ end
+ end
+ else
+ begin
+ if (~TBPROT)
+ begin
+ Sec_Prot[SecNum64 : (SecNum64-29)/2+30] = {256{1'b1}};
+ Sec_Prot[(SecNum64-29)/2+29 : 0] = 286'h0;
+ end
+ else
+ begin
+ Sec_Prot[(SecNum64-29)/2+29 : 0] = {286{1'b1}};
+ Sec_Prot[SecNum64 : (SecNum64-29)/2+30] = 256'h0;
+ end
+ end
+ end
+
+ 3'b111:
+ begin
+ Sec_Prot[SecNum64:0] = {542{1'b1}};
+ end
+ endcase
+ end
+
+ always @(SOut_zd or HOLDNeg_in or SIOut_zd)
+ begin
+ if (HOLDNeg_in == 0 && ~QUAD)
+ begin
+ hold_mode = 1'b1;
+ SIOut_z = 1'bZ;
+ SOut_z = 1'bZ;
+ end
+ else
+ begin
+ if (hold_mode == 1)
+ begin
+ SIOut_z <= #(tpd_HOLDNeg_SO) SIOut_zd;
+ SOut_z <= #(tpd_HOLDNeg_SO) SOut_zd;
+ hold_mode = #(tpd_HOLDNeg_SO) 1'b0;
+ end
+ else
+ begin
+ SIOut_z = SIOut_zd;
+ SOut_z = SOut_zd;
+ hold_mode = 1'b0;
+ end
+ end
+ end
+
+ ////////////////////////////////////////////////////////////////////////
+ // autoboot control logic
+ ////////////////////////////////////////////////////////////////////////
+ always @(rising_edge_SCK_ipd or current_state_event)
+ begin
+ if(current_state == AUTOBOOT)
+ begin
+ if (rising_edge_SCK_ipd)
+ begin
+ if (start_delay > 0)
+ start_delay = start_delay - 1;
+ end
+
+ if (start_delay == 0)
+ begin
+ start_autoboot = 1;
+ end
+ end
+ end
+
+ ////////////////////////////////////////////////////////////////////////
+ // functions & tasks
+ ////////////////////////////////////////////////////////////////////////
+ // Procedure FDDR_DPL
+task Return_DLP;
+ input integer Instruct;
+ input integer EHP;
+ input integer Latency_code;
+ input integer dummy_cnt;
+ inout start_dlp;
+ begin
+ if (Instruct == DDRFR || Instruct == DDRFR4)
+ begin
+ if (EHP)
+ begin
+ if (Latency_code == 1)
+ start_dlp = 1'b1;
+ else if (Latency_code == 2 && dummy_cnt >= 1)
+ start_dlp = 1'b1;
+ else if(Latency_code == 3 || Latency_code == 0)
+ begin
+ start_dlp = 1'b0;
+ $display("Warning at", $time);
+ $display("Inappropriate latency is set during DPL mode");
+ end
+ end
+ else
+ begin
+
+ if (Latency_code == 3)
+ start_dlp = 1'b1;
+ else if (Latency_code == 0 && dummy_cnt >= 1)
+ start_dlp = 1'b1;
+ else if(Latency_code == 1 && dummy_cnt >= 2)
+ start_dlp = 1'b1;
+ else if(Latency_code == 2 && dummy_cnt >= 3)
+ start_dlp = 1'b1;
+ else
+ start_dlp = 1'b0;
+ end
+ end
+ if (Instruct == DDRDIOR || Instruct == DDRDIOR4)
+ begin
+ if (EHP)
+ begin
+ if (Latency_code == 1 && dummy_cnt >= 1)
+ start_dlp = 1'b1;
+ else if (Latency_code == 2 && dummy_cnt >= 2)
+ start_dlp = 1'b1;
+ else if( Latency_code == 3 || Latency_code == 0)
+ begin
+ start_dlp = 1'b0;
+ $display("Warning at", $time);
+ $display("Inappropriate latency is set during DPL mode");
+ end
+ else
+ start_dlp = 1'b0;
+ end
+ else
+ begin
+ if (Latency_code == 0 && dummy_cnt >= 2)
+ start_dlp = 1'b1;
+ else if (Latency_code == 1 && dummy_cnt >= 3)
+ start_dlp = 1'b1;
+ else if(Latency_code == 2 && dummy_cnt >= 4)
+ start_dlp = 1'b1;
+ else
+ start_dlp = 1'b0;
+ end
+ end
+ if ((Instruct == DDRQIOR || Instruct == DDRQIOR4) && QUAD)
+ begin
+ if (EHP)
+ begin
+ if (Latency_code == 0 && dummy_cnt >= 2)
+ start_dlp = 1'b1;
+ else if (Latency_code == 1 && dummy_cnt >= 3)
+ start_dlp = 1'b1;
+ else if (Latency_code == 2 && dummy_cnt >= 4)
+ start_dlp = 1'b1;
+ else if( Latency_code == 3)
+ begin
+ start_dlp = 1'b0;
+ $display("Warning at", $time);
+ $display("Inappropriate latency is");
+ $display("set during DPL mode");
+ end
+ else
+ start_dlp = 1'b0;
+
+ end
+ else
+ begin
+ if (Latency_code == 0 && dummy_cnt >= 2)
+ start_dlp = 1'b1;
+ else if (Latency_code == 1 && dummy_cnt >= 3)
+ start_dlp = 1'b1;
+ else if (Latency_code == 2 && dummy_cnt >= 4)
+ start_dlp = 1'b1;
+ else if( Latency_code == 3)
+ begin
+ start_dlp = 1'b0;
+ $display("Warning at", $time);
+ $display("Inappropriate latency is");
+ $display("set during DPL mode");
+ end
+ else
+ start_dlp = 1'b0;
+ end
+ end
+ end
+ endtask
+
+ function integer ReturnSectorIDRdPswdMd;
+ input reg TBPROT;
+ begin
+ if(TBPROT == 0)
+ begin
+ ReturnSectorIDRdPswdMd = 0;
+ end
+ else
+ begin
+ if (UniformSec)
+ begin
+ ReturnSectorIDRdPswdMd = SecNum256;
+ end
+ else
+ begin
+ ReturnSectorIDRdPswdMd = 511;
+ end
+ end
+ end
+ endfunction
+
+ // Procedure ADDRHILO_SEC
+ task ADDRHILO_SEC;
+ inout AddrLOW;
+ inout AddrHIGH;
+ input Addr;
+ integer AddrLOW;
+ integer AddrHIGH;
+ integer Addr;
+ integer sector;
+ begin
+ if (tmp_char2 == "0")
+ begin
+ if (TBPARM == 0)
+ begin
+ if (Addr/(SecSize64+1) <= 1 &&
+ (Instruct == P4E || Instruct == P4E4)) //4KB Sectors
+ begin
+ sector = Addr/(SecSize4+1);
+ AddrLOW = sector*(SecSize4+1);
+ AddrHIGH = sector*(SecSize4+1) + SecSize4;
+ end
+ else
+ begin
+ sector = Addr/(SecSize64+1);
+ AddrLOW = sector*(SecSize64+1);
+ AddrHIGH = sector*(SecSize64+1) + SecSize64;
+ end
+ end
+ else
+ begin
+ if (Addr/(SecSize64+1) >= 510 &&
+ (Instruct == P4E || Instruct == P4E4)) //4KB Sectors
+ begin
+ sector = 510 + (Addr-(SecSize64+1)*510)/(SecSize4+1);
+ AddrLOW = 510*(SecSize64+1)+(sector-510)*(SecSize4+1);
+ AddrHIGH = 510*(SecSize64+1)+
+ (sector-510)*(SecSize4+1) + SecSize4;
+ end
+ else
+ begin
+ sector = Addr/(SecSize64+1);
+ AddrLOW = sector*(SecSize64+1);
+ AddrHIGH = sector*(SecSize64+1) + SecSize64;
+ end
+ end
+ end
+ else if (tmp_char2 == "1")
+ begin
+ sector = Addr/(SecSize256+1);
+ AddrLOW = sector*(SecSize256+1);
+ AddrHIGH = sector*(SecSize256+1) + SecSize256;
+ end
+ end
+ endtask
+
+ // Procedure ADDRHILO_PG
+ task ADDRHILO_PG;
+ inout AddrLOW;
+ inout AddrHIGH;
+ input Addr;
+ integer AddrLOW;
+ integer AddrHIGH;
+ integer Addr;
+ integer page;
+ begin
+ page = Addr / (PageSize + 1);
+ AddrLOW = page * (PageSize + 1);
+ AddrHIGH = page * (PageSize + 1) + PageSize ;
+ end
+ endtask
+
+ // Procedure ReturnSectorID
+ task ReturnSectorID;
+ inout sect;
+ input Address;
+ integer sect;
+ integer Address;
+ integer conv;
+ begin
+ if (tmp_char2 == "0")
+ begin
+ conv = Address / (SecSize64+1);
+ if (BottomBoot)
+ begin
+ if (conv <= 1) //4KB Sectors
+ begin
+ sect = Address/(SecSize4+1);
+ end
+ else
+ begin
+ sect = conv + 30;
+ end
+ end
+ else if (TopBoot)
+ begin
+ if (conv >= 510) //4KB Sectors
+ begin
+ sect = 510 + (Address-(SecSize64+1)*510)/(SecSize4+1);
+ end
+ else
+ begin
+ sect = conv;
+ end
+ end
+ end
+ else
+ begin
+ sect = Address/(SecSize256+1);
+ end
+ end
+ endtask
+
+ always @(PPBL[0], ASP_reg)
+ begin
+ if (PPBL[0] == 0 && PWDMLB == 0 && RPME == 0 && RdPswdProtEnable)
+ begin
+ RdPswdProtMode = 1;
+ AutoBoot_reg[0] = 0;//AUTOBOOT is disabled when Read Password
+ end //Protection is enabled
+ else
+ begin
+ RdPswdProtMode = 0;
+ end
+ end
+
+ ///////////////////////////////////////////////////////////////////////////
+ // edge controll processes
+ ///////////////////////////////////////////////////////////////////////////
+
+ always @(posedge PoweredUp)
+ begin
+ rising_edge_PoweredUp = 1;
+ #1000 rising_edge_PoweredUp = 0;
+ end
+
+ always @(posedge SCK_ipd)
+ begin
+ rising_edge_SCK_ipd = 1'b1;
+ #1000 rising_edge_SCK_ipd = 1'b0;
+ end
+
+ always @(negedge SCK_ipd)
+ begin
+ falling_edge_SCK_ipd = 1'b1;
+ #1000 falling_edge_SCK_ipd = 1'b0;
+ end
+
+ always @(posedge read_out)
+ begin
+ rising_edge_read_out = 1'b1;
+ #1000 rising_edge_read_out = 1'b0;
+ end
+
+ always @(negedge write)
+ begin
+ falling_edge_write = 1;
+ #1000 falling_edge_write = 0;
+ end
+
+ always @(posedge PRGSUSP_out)
+ begin
+ PRGSUSP_out_event = 1;
+ #1000 PRGSUSP_out_event = 0;
+ end
+
+ always @(posedge ERSSUSP_out)
+ begin
+ ERSSUSP_out_event = 1;
+ #1000 ERSSUSP_out_event = 0;
+ end
+
+ always @(posedge CSNeg_ipd)
+ begin
+ rising_edge_CSNeg_ipd = 1'b1;
+ #1000 rising_edge_CSNeg_ipd = 1'b0;
+ end
+
+ always @(negedge CSNeg_ipd)
+ begin
+ falling_edge_CSNeg_ipd = 1'b1;
+ #1000 falling_edge_CSNeg_ipd = 1'b0;
+ end
+
+ always @(negedge RSTNeg_in)
+ begin
+ falling_edge_RSTNeg = 1'b1;
+ #50000 falling_edge_RSTNeg = 1'b0;
+ end
+
+ always @(posedge RSTNeg_in)
+ begin
+ rising_edge_RSTNeg = 1'b1;
+ #10000 rising_edge_RSTNeg = 1'b0;
+ end
+
+ always @(negedge RST)
+ begin
+ falling_edge_RST = 1'b1;
+ #10000 falling_edge_RST = 1'b0;
+ end
+
+ always @(posedge RST)
+ begin
+ rising_edge_RST = 1'b1;
+ #1000 rising_edge_RST = 1'b0;
+ end
+
+ always @(posedge PDONE)
+ begin
+ rising_edge_PDONE = 1'b1;
+ #1000 rising_edge_PDONE = 1'b0;
+ end
+
+ always @(posedge WDONE)
+ begin
+ rising_edge_WDONE = 1'b1;
+ #1000 rising_edge_WDONE = 1'b0;
+ end
+
+ always @(posedge WSTART)
+ begin
+ rising_edge_WSTART = 1'b1;
+ #1000 rising_edge_WSTART = 1'b0;
+ end
+
+ always @(posedge EDONE)
+ begin
+ rising_edge_EDONE = 1'b1;
+ #1000 rising_edge_EDONE = 1'b0;
+ end
+
+ always @(posedge ESTART)
+ begin
+ rising_edge_ESTART = 1'b1;
+ #1000 rising_edge_ESTART = 1'b0;
+ end
+
+ always @(posedge PSTART)
+ begin
+ rising_edge_PSTART = 1'b1;
+ #1000 rising_edge_PSTART = 1'b0;
+ end
+
+ always @(posedge Reseted)
+ begin
+ rising_edge_Reseted = 1'b1;
+ #1000 rising_edge_Reseted = 1'b0;
+ end
+
+ always @(negedge PASSULCK_in)
+ begin
+ falling_edge_PASSULCK_in = 1'b1;
+ #1000 falling_edge_PASSULCK_in = 1'b0;
+ end
+
+ always @(negedge PPBERASE_in)
+ begin
+ falling_edge_PPBERASE_in = 1'b1;
+ #1000 falling_edge_PPBERASE_in = 1'b0;
+ end
+
+ always @(Instruct)
+ begin
+ Instruct_event = 1'b1;
+ #1000 Instruct_event = 1'b0;
+ end
+
+ always @(change_addr)
+ begin
+ change_addr_event = 1'b1;
+ #1000 change_addr_event = 1'b0;
+ end
+
+ always @(next_state)
+ begin
+ next_state_event = 1'b1;
+ #1000 next_state_event = 1'b0;
+ end
+
+ always @(current_state)
+ begin
+ current_state_event = 1'b1;
+ #1000 current_state_event = 1'b0;
+ end
+
+ always @(posedge RST_out)
+ begin
+ rising_edge_RST_out = 1'b1;
+ #1000 rising_edge_RST_out = 1'b0;
+ end
+
+endmodule
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index a90c7b1..457dcf7 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -71,6 +71,7 @@
`timescale 1 ns / 1 ps
+`include "s25fl256s.sv"
`include "uprj_netlists.v"
`include "caravel_netlists.v"
`include "spiflash.v"
@@ -130,8 +131,9 @@
begin
$dumpfile("simx.vcd");
$dumpvars(1,risc_boot_tb);
+ $dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
//$dumpvars(2,risc_boot_tb.uut);
- $dumpvars(4,risc_boot_tb.uut.mprj.u_core);
+ $dumpvars(4,risc_boot_tb.uut.mprj);
//$dumpvars(0,risc_boot_tb.u_user_spiflash);
$display("Waveform Dump started");
end
@@ -302,18 +304,22 @@
//tri user_flash_io2 = mprj_io[35];
//tri user_flash_io3 = mprj_io[36];
- // Quard flash
- spiflash #(
- .FILENAME("user_uart.hex")
- ) u_user_spiflash (
- .csb(user_flash_csb),
- .clk(user_flash_clk),
- .io0(mprj_io[32]),
- .io1(mprj_io[33]),
- .io2(mprj_io[34]),
- .io3(mprj_io[35])
- );
+ // Quard flash
+ s25fl256s #(.mem_file_name("user_uart.hex"),
+ .otp_file_name("none"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (mprj_io[32]),
+ .SO (mprj_io[33]),
+ // Controls
+ .SCK (user_flash_clk),
+ .CSNeg (user_flash_csb),
+ .WPNeg (mprj_io[34]),
+ .HOLDNeg (mprj_io[35]),
+ .RSTNeg (RSTB)
+
+ );
//------------------------------------------------
// Integrate the SDRAM 8 BIT Memory
diff --git a/verilog/dv/risc_boot/run_iverilog b/verilog/dv/risc_boot/run_iverilog
index 30d8ffd..e2f2a4d 100755
--- a/verilog/dv/risc_boot/run_iverilog
+++ b/verilog/dv/risc_boot/run_iverilog
@@ -18,7 +18,7 @@
#add -DWFDUMP to enable waveform dump
iverilog -DWFDUMP -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
-I $CARAVEL_ROOT/verilog/dv/caravel -I $CARAVEL_ROOT/verilog/rtl \
--I ../model -I ../agents -I ../../../verilog/rtl \
+-I ../model -I ../agents -I ../../../verilog/rtl -I ../../../verilog \
-I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs \
risc_boot_tb.v -o risc_boot.vvp
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 8c55f5e..a3a1ac8 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -26,6 +26,7 @@
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
@@ -63,14 +64,14 @@
ifeq ($(SIM),RTL)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
$< -o $@
endif
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 24c1d6d..ae6502e 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -16,7 +16,7 @@
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS
-`define UNIT_DELAY #1
+`define UNIT_DELAY #0.1
`ifdef GL
@@ -24,57 +24,29 @@
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
+ `include "glbl_cfg.v"
+ `include "sdram.v"
+ `include "spi_master.v"
+ `include "uart.v"
+ `include "wb_interconnect.v"
+ `include "user_project_wrapper.v"
+ `include "syntacore.v"
+ `include "wb_host.v"
+ `include "clk_skew_adjust.v"
-
- `include "glbl_cfg.v"
- `include "sdram.v"
- `include "spi_master.v"
- `include "uart.v"
- `include "wb_interconnect.v"
-
- `include "wb_host/src/wb_host.sv"
- `include "lib/async_wb.sv"
- `include "lib/registers.v"
-
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
- `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
- `include "syntacore/scr1/src/core/scr1_tapc.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
- `include "syntacore/scr1/src/core/scr1_core_top.sv"
- `include "syntacore/scr1/src/core/scr1_dm.sv"
- `include "syntacore/scr1/src/core/scr1_dmi.sv"
- `include "syntacore/scr1/src/core/scr1_scu.sv"
-
- `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
- `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
- `include "syntacore/scr1/src/top/scr1_tcm.sv"
- `include "syntacore/scr1/src/top/scr1_timer.sv"
- `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_top_wb.sv"
- `include "lib/sync_fifo.sv"
- `include "lib/async_fifo.sv"
`else
+
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
`include "spi_master/src/spim_top.sv"
+ `include "spi_master/src/spim_if.sv"
+ `include "spi_master/src/spim_fifo.sv"
`include "spi_master/src/spim_regs.sv"
`include "spi_master/src/spim_clkgen.sv"
`include "spi_master/src/spim_ctrl.sv"
@@ -102,7 +74,6 @@
`include "lib/registers.v"
`include "lib/clk_ctl.v"
`include "digital_core/src/glbl_cfg.sv"
- `include "digital_core/src/digital_core.sv"
`include "wb_host/src/wb_host.sv"
`include "lib/async_wb.sv"
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 87bf24c..348ecd0 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -69,12 +69,12 @@
//// ////
//////////////////////////////////////////////////////////////////////
-`default_nettype none
+`default_nettype wire
`timescale 1 ns / 1 ns
+`include "s25fl256s.sv"
`include "uprj_netlists.v"
-`include "spiflash.v"
`include "mt48lc8m8a2.v"
module user_risc_boot_tb;
@@ -126,7 +126,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(0, user_risc_boot_tb);
+ $dumpvars(2, user_risc_boot_tb);
end
`endif
@@ -259,10 +259,15 @@
wire flash_clk = io_out[30];
wire flash_csb = io_out[31];
- tri flash_io0 = (io_oeb[32]== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb[33]== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb[34]== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb[35]== 1'b0) ? io_out[35] : 1'bz;
+ // Creating Pad Delay
+ wire #1 io_oeb_32 = io_oeb[32];
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
assign io_in[32] = flash_io0;
assign io_in[33] = flash_io1;
@@ -271,16 +276,21 @@
// Quard flash
- spiflash #(
- .FILENAME("user_risc_boot.hex")
- ) u_user_spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
- );
+ s25fl256s #(.mem_file_name("user_risc_boot.hex"),
+ .otp_file_name("none"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
//------------------------------------------------
@@ -383,9 +393,35 @@
end
endtask
+`ifdef GL
+wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+wire wbd_uart_stb_i = u_top.u_uart_core.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_core.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_core.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_core.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_core.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_core.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_core.reg_be;
+
+`endif
+
+/**
`ifdef GL
//-----------------------------------------------------------------------------
// RISC IMEM amd DMEM Monitoring TASK
@@ -403,5 +439,6 @@
end
`endif
+**/
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
new file mode 100644
index 0000000..7fca4c3
--- /dev/null
+++ b/verilog/dv/user_spi/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = user_spi
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
+ riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+ riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+ riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+ riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump
+ rm crt_tcm.o user_risc_boot.o
+ifeq ($(SIM),RTL)
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
+ $< -o $@
+else
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex:
+ echo @"This is user boot test, noting to compile the mangment core code"
+
+%.bin: %.elf
+ ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_spi/run_iverilog b/verilog/dv/user_spi/run_iverilog
new file mode 100755
index 0000000..a88ab91
--- /dev/null
+++ b/verilog/dv/user_spi/run_iverilog
@@ -0,0 +1,42 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+
+riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+
+riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+
+riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump
+
+rm crt_tcm.o user_risc_boot.o
+
+#iverilog with waveform dump
+#iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
+
+#iverilog without Dump
+iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
+
+# GLS
+#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
+#
+
+vvp user_spi_tb.vvp | tee test.log
+
+\rm -rf user_spi_tb.vvp
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
new file mode 100644
index 0000000..ae6502e
--- /dev/null
+++ b/verilog/dv/user_spi/uprj_netlists.v
@@ -0,0 +1,121 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
+`define USE_POWER_PINS
+`define UNIT_DELAY #0.1
+
+`ifdef GL
+
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
+
+ `include "glbl_cfg.v"
+ `include "sdram.v"
+ `include "spi_master.v"
+ `include "uart.v"
+ `include "wb_interconnect.v"
+ `include "user_project_wrapper.v"
+ `include "syntacore.v"
+ `include "wb_host.v"
+ `include "clk_skew_adjust.v"
+
+`else
+
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
+ `include "spi_master/src/spim_top.sv"
+ `include "spi_master/src/spim_if.sv"
+ `include "spi_master/src/spim_fifo.sv"
+ `include "spi_master/src/spim_regs.sv"
+ `include "spi_master/src/spim_clkgen.sv"
+ `include "spi_master/src/spim_ctrl.sv"
+ `include "spi_master/src/spim_rx.sv"
+ `include "spi_master/src/spim_tx.sv"
+
+ `include "uart/src/uart_core.sv"
+ `include "uart/src/uart_cfg.sv"
+ `include "uart/src/uart_rxfsm.sv"
+ `include "uart/src/uart_txfsm.sv"
+ `include "lib/async_fifo_th.sv"
+ `include "lib/reset_sync.sv"
+ `include "lib/double_sync_low.v"
+
+ `include "sdram_ctrl/src/top/sdrc_top.v"
+ `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
+ `include "lib/async_fifo.sv"
+ `include "sdram_ctrl/src/core/sdrc_core.v"
+ `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
+ `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
+ `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
+ `include "sdram_ctrl/src/core/sdrc_req_gen.v"
+ `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
+
+ `include "lib/registers.v"
+ `include "lib/clk_ctl.v"
+ `include "digital_core/src/glbl_cfg.sv"
+
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+
+ `include "lib/wb_stagging.sv"
+ `include "wb_interconnect/src/wb_arb.sv"
+ `include "wb_interconnect/src/wb_interconnect.sv"
+
+
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
+ `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
+ `include "syntacore/scr1/src/core/scr1_core_top.sv"
+ `include "syntacore/scr1/src/core/scr1_dm.sv"
+ `include "syntacore/scr1/src/core/scr1_dmi.sv"
+ `include "syntacore/scr1/src/core/scr1_scu.sv"
+
+ `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
+ `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
+ `include "syntacore/scr1/src/top/scr1_tcm.sv"
+ `include "syntacore/scr1/src/top/scr1_timer.sv"
+ `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+ `include "lib/sync_fifo.sv"
+
+ `include "user_project_wrapper.v"
+ // we are using netlist file for clk_skew_adjust as it has
+ // standard cell + power pin
+ `include "gl/clk_skew_adjust.v"
+`endif
diff --git a/verilog/dv/user_spi/user_risc_boot.c b/verilog/dv/user_spi/user_risc_boot.c
new file mode 100644
index 0000000..af9339d
--- /dev/null
+++ b/verilog/dv/user_spi/user_risc_boot.c
@@ -0,0 +1,61 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t long
+
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+
+int main()
+{
+
+ //volatile long *out_ptr = (volatile long*)SC_SIM_OUTPORT;
+ //*out_ptr = 0xAABBCCDD;
+ //*out_ptr = 0xBBCCDDEE;
+ //*out_ptr = 0xCCDDEEFF;
+ //*out_ptr = 0xDDEEFF00;
+
+ // Write software Write & Read Register
+ reg_mprj_globl_reg6 = 0x11223344;
+ reg_mprj_globl_reg7 = 0x22334455;
+ reg_mprj_globl_reg8 = 0x33445566;
+ reg_mprj_globl_reg9 = 0x44556677;
+ reg_mprj_globl_reg10 = 0x55667788;
+ reg_mprj_globl_reg11 = 0x66778899;
+ //reg_mprj_globl_reg12 = 0x778899AA;
+ //reg_mprj_globl_reg13 = 0x8899AABB;
+ //reg_mprj_globl_reg14 = 0x99AABBCC;
+ //reg_mprj_globl_reg15 = 0xAABBCCDD;
+
+ while(1) {}
+ return 0;
+}
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
new file mode 100644
index 0000000..de9fe38
--- /dev/null
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -0,0 +1,612 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// 1. User Risc core is booted using compiled code of ////
+//// user_risc_boot.c ////
+//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
+//// 3. After successful boot, Risc core will write signature ////
+//// in to user register from 0x3000_0018 to 0x3000_002C ////
+//// 4. Through the External Wishbone Interface we read back ////
+//// and validate the user register to declared pass fail ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "s25fl256s.sv"
+`include "uprj_netlists.v"
+`include "mt48lc8m8a2.v"
+
+module user_spi_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("user_spi.vcd");
+ $dumpvars(5, user_spi_tb);
+ end
+ `endif
+
+ initial begin
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write('h3080_0000,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
+ wb_user_core_write('h3080_0000,'h5);
+
+ wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0
+
+
+ test_fail = 0;
+ repeat (200) @(posedge clock);
+ $display("#############################################");
+ $display(" Testing Direct SPI Memory Read ");
+ $display("#############################################");
+ wb_user_core_read_check(32'h00000200,read_data,32'h00000093);
+ wb_user_core_read_check(32'h00000204,read_data,32'h00000113);
+ wb_user_core_read_check(32'h00000208,read_data,32'h00000193);
+ wb_user_core_read_check(32'h0000020C,read_data,32'h00000213);
+ wb_user_core_read_check(32'h00000210,read_data,32'h00000293);
+ wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
+ wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
+ wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
+ wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
+ wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
+ wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
+ wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
+ wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
+ wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
+ wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
+ wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+
+ $display("#############################################");
+ $display(" Testing Single Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+
+ wb_user_core_write(32'h1000000C,{15'h0,1'b0,2'b01,2'b10,4'b0001});
+ wb_user_core_write(32'h10000010,{8'h4,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_write(32'h10000014,32'h00000204);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_write(32'h10000014,32'h00000208);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_write(32'h10000014,32'h0000020C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_write(32'h10000014,32'h00000210);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_write(32'h10000014,32'h00000214);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
+ wb_user_core_write(32'h10000014,32'h00000218);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
+ wb_user_core_write(32'h10000014,32'h0000021C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_write(32'h10000014,32'h00000404);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_write(32'h10000014,32'h00000408);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_write(32'h10000014,32'h0000040C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_write(32'h10000014,32'h00000410);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_write(32'h10000014,32'h00000414);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ wb_user_core_write(32'h10000014,32'h00000418);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
+ wb_user_core_write(32'h10000014,32'h0000041C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ repeat (100) @(posedge clock);
+ $display("#############################################");
+ $display(" Testing Two Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write(32'h1000000C,{15'h0,1'b0,2'b01,2'b10,4'b0001});
+ wb_user_core_write(32'h10000010,{8'h8,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_write(32'h10000014,32'h00000208);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_write(32'h10000014,32'h00000210);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
+ wb_user_core_write(32'h10000014,32'h00000218);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_write(32'h10000014,32'h00000408);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_write(32'h10000014,32'h00000410);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ wb_user_core_write(32'h10000014,32'h00000418);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ repeat (100) @(posedge clock);
+ $display("#############################################");
+ $display(" Testing Three Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write(32'h10000010,{8'hC,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_write(32'h10000014,32'h0000020C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_write(32'h10000014,32'h0000040C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ repeat (100) @(posedge clock);
+ $display("#############################################");
+ $display(" Testing Four Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write(32'h10000010,{8'h10,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_write(32'h10000014,32'h00000210);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_write(32'h10000014,32'h00000410);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ repeat (100) @(posedge clock);
+ $display("#############################################");
+ $display(" Testing Five Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write(32'h10000010,{8'h14,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ $display("#############################################");
+ $display(" Testing Eight Word Indirect SPI Memory Read");
+ $display("#############################################");
+ wb_user_core_write(32'h10000010,{8'h20,2'b01,2'b10,4'b0110,8'h00,8'hEB});
+ wb_user_core_write(32'h10000014,32'h00000200);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000093);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000113);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
+ wb_user_core_write(32'h10000014,32'h00000400);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ repeat (100) @(posedge clock);
+ // $display("+1000 cycles");
+
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: SPI Master Mode (GL) Passed");
+ `else
+ $display("Monitor: SPI Master Mode (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: SPI Master Mode (GL) Failed");
+ `else
+ $display("Monitor: SPI Master Mode (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('0) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[30];
+ wire flash_csb = io_out[31];
+ // Creating Pad Delay
+ wire #1 io_oeb_32 = io_oeb[32];
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+
+ assign io_in[32] = flash_io0;
+ assign io_in[33] = flash_io1;
+ assign io_in[34] = flash_io2;
+ assign io_in[35] = flash_io3;
+
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("user_risc_boot.hex"),
+ .otp_file_name("none"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+
+//------------------------------------------------
+// Integrate the SDRAM 8 BIT Memory
+// -----------------------------------------------
+
+wire [7:0] Dq ; // SDRAM Read/Write Data Bus
+wire [0:0] sdr_dqm ; // SDRAM DATA Mask
+wire [1:0] sdr_ba ; // SDRAM Bank Select
+wire [12:0] sdr_addr ; // SDRAM ADRESS
+wire sdr_cs_n ; // chip select
+wire sdr_cke ; // clock gate
+wire sdr_ras_n ; // ras
+wire sdr_cas_n ; // cas
+wire sdr_we_n ; // write enable
+wire sdram_clk ;
+
+assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
+assign sdr_addr[12:0] = io_out [20:8] ;
+assign sdr_ba[1:0] = io_out [22:21] ;
+assign sdr_dqm[0] = io_out [23] ;
+assign sdr_we_n = io_out [24] ;
+assign sdr_cas_n = io_out [25] ;
+assign sdr_ras_n = io_out [26] ;
+assign sdr_cs_n = io_out [27] ;
+assign sdr_cke = io_out [28] ;
+assign sdram_clk = io_out [29] ;
+assign io_in[29] = sdram_clk;
+assign #(1) io_in[7:0] = Dq;
+
+// to fix the sdram interface timing issue
+wire #(1) sdram_clk_d = sdram_clk;
+
+ // SDRAM 8bit
+mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
+ .Dq (Dq ) ,
+ .Addr (sdr_addr[11:0] ),
+ .Ba (sdr_ba ),
+ .Clk (sdram_clk_d ),
+ .Cke (sdr_cke ),
+ .Cs_n (sdr_cs_n ),
+ .Ras_n (sdr_ras_n ),
+ .Cas_n (sdr_cas_n ),
+ .We_n (sdr_we_n ),
+ .Dqm (sdr_dqm )
+ );
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ user_spi_tb.test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+
+wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_core.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_core.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_core.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_core.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_core.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_core.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_core.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index c05ec68..1f5b0c3 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -26,6 +26,7 @@
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
@@ -68,9 +69,9 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
$< -o $@
else
- iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
$< -o $@
endif
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
index 6cac66f..15548a4 100755
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -33,8 +33,9 @@
#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
-# GLS
-#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+# GLS
+#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+#
vvp user_uart_tb.vvp | tee test.log
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index d140c85..ae6502e 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -16,7 +16,7 @@
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS
-`define UNIT_DELAY #1
+`define UNIT_DELAY #0.1
`ifdef GL
@@ -24,18 +24,17 @@
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
-
- `include "glbl_cfg.v"
- `include "sdram.v"
- `include "spi_master.v"
- `include "uart.v"
- `include "wb_interconnect.v"
- `include "user_project_wrapper.v"
-
- `include "syntacore.v"
- `include "wb_host.v"
+ `include "glbl_cfg.v"
+ `include "sdram.v"
+ `include "spi_master.v"
+ `include "uart.v"
+ `include "wb_interconnect.v"
+ `include "user_project_wrapper.v"
+ `include "syntacore.v"
+ `include "wb_host.v"
+ `include "clk_skew_adjust.v"
`else
@@ -46,6 +45,8 @@
`include "spi_master/src/spim_top.sv"
+ `include "spi_master/src/spim_if.sv"
+ `include "spi_master/src/spim_fifo.sv"
`include "spi_master/src/spim_regs.sv"
`include "spi_master/src/spim_clkgen.sv"
`include "spi_master/src/spim_ctrl.sv"
@@ -73,7 +74,6 @@
`include "lib/registers.v"
`include "lib/clk_ctl.v"
`include "digital_core/src/glbl_cfg.sv"
- `include "digital_core/src/digital_core.sv"
`include "wb_host/src/wb_host.sv"
`include "lib/async_wb.sv"
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index cfe4819..4852c4b 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -70,12 +70,12 @@
//// ////
//////////////////////////////////////////////////////////////////////
-`default_nettype none
+`default_nettype wire
`timescale 1 ns / 1 ns
+`include "s25fl256s.sv"
`include "uprj_netlists.v"
-`include "spiflash.v"
`include "mt48lc8m8a2.v"
`include "uart_agent.v"
@@ -149,7 +149,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(4, user_uart_tb);
+ $dumpvars(2, user_uart_tb);
end
`endif
@@ -298,10 +298,15 @@
wire flash_clk = io_out[30];
wire flash_csb = io_out[31];
- tri flash_io0 = (io_oeb[32]== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb[33]== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb[34]== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb[35]== 1'b0) ? io_out[35] : 1'bz;
+ // Creating Pad Delay
+ wire #1 io_oeb_32 = io_oeb[32];
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
assign io_in[32] = flash_io0;
assign io_in[33] = flash_io1;
@@ -310,16 +315,20 @@
// Quard flash
- spiflash #(
- .FILENAME("user_uart.hex")
- ) u_user_spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
- );
+ s25fl256s #(.mem_file_name("user_uart.hex"),.otp_file_name("none")) u_spi_flash_256mb
+ (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
//------------------------------------------------
@@ -437,7 +446,33 @@
end
endtask
+`ifdef GL
+wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+
+wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_core.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_core.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_core.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_core.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_core.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_core.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_core.reg_be;
+
+`endif
/**
`ifdef GL
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 2e042cd..4b8a056 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -450,7 +450,7 @@
.wbd_ack_o (wbd_spim_ack_i ),
.wbd_err_o (wbd_spim_err_i ),
- .events_o ( ), // TODO - Need to connect to intr ?
+ .spi_debug (spi_debug ),
// Pad Interface
.io_in (io_in[35:30] ),
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
index df1fbce..dac5928 100644
--- a/verilog/rtl/lib/async_wb.sv
+++ b/verilog/rtl/lib/async_wb.sv
@@ -105,7 +105,7 @@
// -------------------------------------------------
logic PendingRd ; // Pending Read Transaction
logic m_cmd_wr_en ;
-logic [70:0] m_cmd_wr_data ;
+logic [68:0] m_cmd_wr_data ;
logic m_cmd_wr_full ;
logic m_cmd_wr_afull ;
@@ -119,14 +119,14 @@
assign m_cmd_wr_en = (!PendingRd) && wbm_stb_i && !m_cmd_wr_full && !m_cmd_wr_afull;
-assign m_cmd_wr_data = {wbm_cyc_i,wbm_stb_i,wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i};
+assign m_cmd_wr_data = {wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i};
always@(negedge wbm_rst_n or posedge wbm_clk_i)
begin
if(wbm_rst_n == 0) begin
PendingRd <= 1'b0;
end else begin
- if((!PendingRd) && wbm_stb_i && (!wbm_we_i)) begin
+ if((!PendingRd) && wbm_stb_i && (!wbm_we_i) && m_cmd_wr_en) begin
PendingRd <= 1'b1;
end else if(PendingRd && wbm_stb_i && (!wbm_we_i) && wbm_ack_o) begin
PendingRd <= 1'b0;
@@ -158,10 +158,26 @@
logic [32:0] s_resp_wr_data ;
logic s_resp_wr_full ;
logic s_resp_wr_afull ;
+logic wbs_ack_f ;
+
+
+always@(negedge wbs_rst_n or posedge wbs_clk_i)
+begin
+ if(wbs_rst_n == 0) begin
+ wbs_ack_f <= 1'b0;
+ end else begin
+ wbs_ack_f <= wbs_ack_i;
+ end
+end
// Read Interface
-assign {wbs_cyc_o,wbs_stb_o,wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o} = (s_cmd_rd_empty) ? '0: s_cmd_rd_data;
+assign {wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o} = (s_cmd_rd_empty) ? '0: s_cmd_rd_data;
+// All the downstream logic expect Stobe is getting de-asserted
+// atleast for 1 cycle after ack is generated
+assign wbs_stb_o = (wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1;
+assign wbs_cyc_o = (wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1;
+
assign s_cmd_rd_en = wbs_ack_i;
// Write Interface
@@ -169,7 +185,7 @@
assign s_resp_wr_en = wbs_stb_o & (!wbs_we_o) & wbs_ack_i & !s_resp_wr_full;
assign s_resp_wr_data = {wbs_err_i,wbs_dat_i};
-async_fifo #(.W(71), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_cmd_if (
+async_fifo #(.W(69), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_cmd_if (
// Sync w.r.t WR clock
.wr_clk (wbm_clk_i ),
.wr_reset_n (wbm_rst_n ),
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
index b4bee53..9e81d98 100644
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -60,35 +60,54 @@
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
-module spim_ctrl
+module spim_ctrl #(
+ parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
+ )
+
(
input logic clk,
input logic rstn,
- output logic eot,
- input logic [5:0] spi_clk_div,
+ input logic [7:0] spi_clk_div,
output logic [8:0] spi_status,
+ // Master 0 Configuration
+ input logic [3:0] cfg_m0_cs_reg , // Chip select
+ input logic [1:0] cfg_m0_spi_mode , // Final SPI Mode
+ input logic [1:0] cfg_m0_spi_switch, // SPI Mode Switching Place
- input logic spi_req,
- input logic [31:0] spi_addr,
- input logic [5:0] spi_addr_len,
- input logic [7:0] spi_cmd,
- input logic [5:0] spi_cmd_len,
- input logic [7:0] spi_mode_cmd,
- input logic spi_mode_cmd_enb,
- input logic [3:0] spi_csreg,
- input logic [15:0] spi_data_len,
- input logic [15:0] spi_dummy_rd_len,
- input logic [15:0] spi_dummy_wr_len,
- input logic spi_swrst, //FIXME Not used at all
- input logic spi_rd,
- input logic spi_wr,
- input logic spi_qrd,
- input logic spi_qwr,
- input logic [31:0] spi_wdata,
- output logic [31:0] spi_rdata,
- output logic spi_ack,
+ input logic [3:0] cfg_m1_cs_reg , // Chip select
+ input logic [1:0] cfg_m1_spi_mode , // Final SPI Mode
+ input logic [1:0] cfg_m1_spi_switch, // SPI Mode Switching Place
+
+ input logic [1:0] cfg_cs_early , // Amount of cycle early CS asserted
+ input logic [1:0] cfg_cs_late , // Amount of cycle late CS de-asserted
+
+ // Master 0 Command FIFO Interface
+ input logic m0_cmd_fifo_empty,
+ output logic m0_cmd_fifo_rd,
+ input logic [33:0] m0_cmd_fifo_rdata,
+
+ // Master 0 response FIFO Interface
+ output logic m0_res_fifo_flush,
+ input logic m0_res_fifo_empty,
+ input logic m0_res_fifo_full,
+ output logic m0_res_fifo_wr,
+ output logic [31:0] m0_res_fifo_wdata,
+
+ // Master 1 Command FIFO Interface
+ output logic m1_res_fifo_flush,
+ input logic m1_cmd_fifo_empty,
+ output logic m1_cmd_fifo_rd,
+ input logic [33:0] m1_cmd_fifo_rdata,
+
+ // Master 1 response FIFO Interface
+ input logic m1_res_fifo_empty,
+ input logic m1_res_fifo_full,
+ output logic m1_res_fifo_wr,
+ output logic [31:0] m1_res_fifo_wdata,
+
+ output logic [3:0] ctrl_state,
output logic spi_clk,
output logic spi_csn0,
@@ -107,11 +126,73 @@
output logic spi_en_tx // Spi Direction control
);
-
+//--------------------------------------
+// Parameter
+// --------------------------------------
parameter SPI_STD = 2'b00;
parameter SPI_QUAD_TX = 2'b01;
parameter SPI_QUAD_RX = 2'b10;
+/*************************************************************
+* SPI FSM State Control
+*
+* OPERATION COMMAND SEQUENCE
+*
+* ERASE P4E(0x20) -> COMMAND + ADDRESS
+* ERASE P8E(0x40) -> COMMAND + ADDRESS
+* ERASE SE(0xD8) -> COMMAND + ADDRESS
+* ERASE BE(0x60) -> COMMAND + ADDRESS
+* ERASE BE(0xC7) -> COMMAND
+* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
+* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
+* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
+* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
+* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
+* READ RDID (0x9F) -> COMMAND + READ DATA
+* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
+* WRITE WREN(0x6) -> COMMAND
+* WRITE WRDI -> COMMAND
+* STATUS RDSR(0x05) -> COMMAND + READ DATA
+* STATUS RCR(0x35) -> COMMAND + READ DATA
+* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
+* CONFIG CLSR(0x30) -> COMMAND
+* Power Saving DP(0xB9) -> COMMAND
+* Power Saving RES(0xAB) -> COMMAND + READ DATA
+* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
+* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
+* ********************************************************************/
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+
+parameter P_FSM_CDR = 4'b1001; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1010; // COMMAND -> DUMMY -> WRITE
+
+//---------------------
+ parameter P_8BIT = 2'b00;
+ parameter P_16BIT = 2'b01;
+ parameter P_24BIT = 2'b10;
+ parameter P_32BIT = 2'b11;
+
+//---- Phase where to switch the SPI Mode
+//---- This need to decided based on command
+ parameter P_MODE_SWITCH_IDLE = 2'b00;
+ parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+ parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+//----------------------------------------
+// Local Variable
+// ---------------------------------------
logic spi_rise;
logic spi_fall;
@@ -119,6 +200,8 @@
logic spi_en_rx;
+ logic res_fifo_flush;
+
logic [15:0] counter_tx;
logic counter_tx_valid;
logic [15:0] counter_rx;
@@ -127,68 +210,137 @@
logic [31:0] data_to_tx;
logic data_to_tx_valid;
logic data_to_tx_ready;
+ logic tx_data_ready;
- logic en_quad;
- logic en_quad_int;
- logic do_tx; //FIXME NOT USED at all!!
- logic do_rx;
- logic tx_done;
- logic rx_done;
+ logic tx_done;
+ logic rx_done;
logic [1:0] s_spi_mode;
- logic ctrl_data_valid;
+ logic ctrl_data_valid;
- logic spi_cs;
+ logic spi_cs;
- logic tx_clk_en;
- logic rx_clk_en;
- logic en_quad_in;
+ logic tx_clk_en;
+ logic rx_clk_en;
+ logic en_quad_in;
+ logic [1:0] cnt; // counter for cs assertion and de-assertion
+ logic [1:0] nxt_cnt;
+ logic [1:0] gnt;
+
+ logic [7:0] cfg_data_cnt ;
+ logic [1:0] cfg_dummy_cnt ;
+ logic [1:0] cfg_addr_cnt ;
+ logic [3:0] cfg_spi_seq ;
+ logic [7:0] spi_mode_cmd ;
enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
- enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY_RX,DUMMY_TX,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
+ enum logic [4:0] {FSM_IDLE,FSM_CS_ASSERT,FSM_CMD_PHASE,FSM_ADR_PHASE,FSM_DUMMY_PHASE,FSM_MODE_PHASE,FSM_WRITE_CMD,FSM_WRITE_PHASE,
+ FSM_READ_WAIT,FSM_READ_PHASE,FSM_TX_DONE,FSM_CS_DEASEERT} state,next_state;
- assign en_quad = spi_qrd | spi_qwr | en_quad_int;
-
-
+
+ assign ctrl_state = state;
assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;
+ assign spi_mode = s_spi_mode;
+
+ //----------------------------
+ // Configuration
+ //----------------------------
+ logic [3:0] cfg_cs_reg ; // Chip select
+ logic [1:0] cfg_spi_mode ; // Final SPI Mode
+ logic [1:0] cfg_spi_switch; // SPI Mode Switching Place
+
+
+ assign cfg_cs_reg = (gnt == 2'b01) ? cfg_m0_cs_reg : cfg_m1_cs_reg;
+ assign cfg_spi_mode = (gnt == 2'b01) ? cfg_m0_spi_mode : cfg_m1_spi_mode; // Final SPI Mode
+ assign cfg_spi_switch = (gnt == 2'b01) ? cfg_m0_spi_switch: cfg_m1_spi_switch; // SPI Mode Switching Place
+
+ //----------------------------
+ // Command FIFO
+ //----------------------------
+ logic cmd_fifo_empty;
+ logic cmd_fifo_rd;
+ logic [33:0] cmd_fifo_rdata;
+
+ assign cmd_fifo_empty = (gnt == 2'b01) ? m0_cmd_fifo_empty : m1_cmd_fifo_empty;
+ assign cmd_fifo_rdata = (gnt == 2'b01) ? m0_cmd_fifo_rdata : m1_cmd_fifo_rdata;
+
+ assign m0_cmd_fifo_rd = (gnt == 2'b01) ? cmd_fifo_rd : 1'b0;
+ assign m1_cmd_fifo_rd = (gnt == 2'b10) ? cmd_fifo_rd : 1'b0;
+
+ //----------------------------
+ // Response FIFO
+ //----------------------------
+ logic res_fifo_empty;
+ logic res_fifo_full;
+ logic res_fifo_wr;
+ logic [31:0] res_fifo_wdata;
+
+ assign res_fifo_empty = (gnt == 2'b01) ? m0_res_fifo_empty : m1_res_fifo_empty;
+ assign res_fifo_full = (gnt == 2'b01) ? m0_res_fifo_full : m1_res_fifo_full;
+
+ assign m0_res_fifo_wr = (gnt == 2'b01) ? res_fifo_wr : 1'b0;
+ assign m1_res_fifo_wr = (gnt == 2'b10) ? res_fifo_wr : 1'b0;
+
+ assign m0_res_fifo_wdata = (gnt == 2'b01) ? res_fifo_wdata : 1'b0;
+ assign m1_res_fifo_wdata = (gnt == 2'b10) ? res_fifo_wdata : 1'b0;
+
+ //---------------------------------------------------------------------------
+ // To take care of partial/stall data in response fifo
+ // we are flushing the content
+ //
+ // WARNING: This will work well for burst size 4,
+ // If User given 6 Word Burst and Read only one location
+ // Read Path will hang waiting for Response FIFO to empty, User need to take
+ // care of partial reading case.
+ //---------------------------------------------------------------------------
+
+ assign m0_res_fifo_flush = (gnt == 2'b01) ? res_fifo_flush : 1'b0;
+ assign m1_res_fifo_flush = (gnt == 2'b10) ? res_fifo_flush : 1'b0;
+
+ assign spi_clock_en = tx_clk_en | rx_clk_en;
+
+ logic fsm_flush;
+ assign fsm_flush = (state == FSM_IDLE);
+
spim_clkgen u_clkgen
(
- .clk ( clk ),
- .rstn ( rstn ),
- .en ( spi_clock_en ),
- .cfg_sck_period( spi_clk_div ),
- .spi_clk ( spi_clk ),
- .spi_fall ( spi_fall ),
- .spi_rise ( spi_rise )
+ .clk ( clk ),
+ .rstn ( rstn ),
+ .en ( spi_clock_en ),
+ .cfg_sck_period ( spi_clk_div [5:0] ),
+ .spi_clk ( spi_clk ),
+ .spi_fall ( spi_fall ),
+ .spi_rise ( spi_rise )
);
-
spim_tx u_txreg
(
- .clk ( clk ),
- .rstn ( rstn ),
- .en ( spi_en_tx ),
- .tx_edge ( spi_fall ),
- .tx_done ( tx_done ),
- .sdo0 ( spi_sdo0 ),
- .sdo1 ( spi_sdo1 ),
- .sdo2 ( spi_sdo2 ),
- .sdo3 ( spi_sdo3 ),
- .en_quad_in ( en_quad_in ),
- .counter_in ( counter_tx ),
- .txdata ( data_to_tx ),
- .data_valid ( data_to_tx_valid ),
- .data_ready ( ),
- .clk_en_o ( tx_clk_en )
- );
- spim_rx u_rxreg
- (
.clk ( clk ),
.rstn ( rstn ),
+ .flush ( fsm_flush ),
+ .en ( spi_en_tx ),
+ .tx_edge ( spi_fall ),
+ .tx_done ( tx_done ),
+ .sdo0 ( spi_sdo0 ),
+ .sdo1 ( spi_sdo1 ),
+ .sdo2 ( spi_sdo2 ),
+ .sdo3 ( spi_sdo3 ),
+ .en_quad_in ( en_quad_in ),
+ .counter_in ( counter_tx ),
+ .txdata ( data_to_tx ),
+ .data_valid ( data_to_tx_valid ),
+ .data_ready ( tx_data_ready ),
+ .clk_en_o ( tx_clk_en )
+ );
+ spim_rx #(.ENDIEAN(ENDIEAN)) u_rxreg
+ (
+ .clk ( clk ),
+ .rstn ( rstn ),
+ .flush ( fsm_flush ),
.en ( spi_en_rx ),
.rx_edge ( spi_rise ),
.rx_done ( rx_done ),
@@ -199,13 +351,12 @@
.en_quad_in ( en_quad_in ),
.counter_in ( counter_rx ),
.counter_in_upd ( counter_rx_valid ),
- .data ( spi_rdata ),
- .data_valid ( ),
- .data_ready ( 1'b1 ),
+ .data ( res_fifo_wdata ),
+ .data_valid ( res_fifo_wr ),
+ .data_ready ( !res_fifo_full ),
.clk_en_o ( rx_clk_en )
);
-
always_comb
begin
data_to_tx = 'h0;
@@ -226,7 +377,7 @@
DATA_CMD:
begin
- data_to_tx = {spi_cmd,24'h0};
+ data_to_tx = {cmd_fifo_rdata[7:0],24'h0};
data_to_tx_valid = ctrl_data_valid;
end
DATA_MODE:
@@ -237,518 +388,311 @@
DATA_ADDR:
begin
- data_to_tx = spi_addr;
+ data_to_tx = (cfg_addr_cnt == P_8BIT) ? {cmd_fifo_rdata[7:0],24'h0} :
+ (cfg_addr_cnt == P_16BIT) ? {cmd_fifo_rdata[15:0],16'h0} :
+ (cfg_addr_cnt == P_24BIT) ? {cmd_fifo_rdata[23:0],8'h0} : {cmd_fifo_rdata[31:0]};
data_to_tx_valid = ctrl_data_valid;
end
- DATA_FIFO:
- begin
- data_to_tx = spi_wdata;
- data_to_tx_valid = ctrl_data_valid;
+ // RISV is little endian, so data is converted to little endian format
+ DATA_FIFO: begin
+ data_to_tx = (ENDIEAN) ? cmd_fifo_rdata[31:0] :
+ {cmd_fifo_rdata[7:0],cmd_fifo_rdata[15:8],cmd_fifo_rdata[23:16],cmd_fifo_rdata[31:24]};
+ data_to_tx_valid = !cmd_fifo_empty;
end
endcase
end
always_comb
begin
- spi_cs = 1'b1;
- spi_clock_en = 1'b0;
- counter_tx = '0;
- counter_tx_valid = 1'b0;
- counter_rx = '0;
- counter_rx_valid = 1'b0;
- state_next = state;
- ctrl_data_mux = DATA_NULL;
- ctrl_data_valid = 1'b0;
- spi_en_rx = 1'b0;
- spi_en_tx = 1'b0;
- spi_status = '0;
- s_spi_mode = SPI_QUAD_RX;
- eot = 1'b0;
+ counter_tx = '0;
+ counter_tx_valid = 1'b0;
+ counter_rx = '0;
+ counter_rx_valid = 1'b0;
+ next_state = state;
+ ctrl_data_mux = DATA_NULL;
+ ctrl_data_valid = 1'b0;
+ spi_en_rx = 1'b0;
+ spi_en_tx = 1'b0;
+ spi_status = '0;
+ cmd_fifo_rd = 1'b0;
+ res_fifo_flush = 0;
+ nxt_cnt = cnt;
case(state)
- IDLE:
+ FSM_IDLE:
begin
spi_status[0] = 1'b1;
- s_spi_mode = SPI_QUAD_RX;
- if (spi_req && spi_fall)
- begin
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
-
- if (spi_cmd_len != 0)
- begin
-// s_spi_mode = (spi_qrd | spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
- s_spi_mode = SPI_STD; // COMMAND is always Standard Mode ?
- counter_tx = {8'h0,spi_cmd_len};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_CMD;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = CMD;
- end
- else if (spi_addr_len != 0)
- begin
- s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
- counter_tx = {8'h0,spi_addr_len};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_ADDR;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = ADDR;
- end
- else if (spi_mode_cmd_enb != 0)
- begin
- s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
- counter_tx = {8'h0,8'h8};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_MODE;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = MODE;
- end
- else if (spi_data_len != 0)
- begin
- if (spi_rd || spi_qrd)
- begin
- s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;
- if(spi_dummy_rd_len != 0)
- begin
- counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = rx_clk_en;
- state_next = DUMMY_RX;
- end
- else
- begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end
- end
- else
- begin
- s_spi_mode = (spi_qwr) ? SPI_QUAD_TX : SPI_STD;
- if(spi_dummy_wr_len != 0)
- begin
- counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_en_tx = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DUMMY_TX;
- end
- else
- begin
- counter_tx = spi_data_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b0;
- spi_en_tx = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DATA_TX;
- end
- end
- end
- end
- else
- begin
- spi_cs = 1'b1;
- state_next = IDLE;
+ nxt_cnt = 0;
+ if(!m0_cmd_fifo_empty || !m1_cmd_fifo_empty ) begin
+ next_state = FSM_CS_ASSERT;
end
end
- CMD:
- begin
- spi_status[1] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
-// s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- s_spi_mode = SPI_STD; // Command is always Standard Mode ?
- if (tx_done && spi_fall)
- begin
- if (spi_addr_len != 0)
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- counter_tx = {8'h0,spi_addr_len};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_ADDR;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = ADDR;
- end
- else if (spi_mode_cmd_enb != 0)
- begin
- s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
- counter_tx = {8'h0,8'h8};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_MODE;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = MODE;
- end
- else if (spi_data_len != 0)
- begin
- if (do_rx)
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
- if(spi_dummy_rd_len != 0)
- begin
- counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = rx_clk_en;
- state_next = DUMMY_RX;
- end
- else
- begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end
- end
- else
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- if(spi_dummy_wr_len != 0)
- begin
- counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_en_tx = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DUMMY_TX;
- end
- else
- begin
- counter_tx = spi_data_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DATA_TX;
- end
- end
- end
- else
- begin
- spi_en_tx = 1'b1;
- state_next = WAIT_EDGE;
- end
- end
- else
- begin
- spi_en_tx = 1'b1;
- state_next = CMD;
- end
+ // Asserted CS# low
+ FSM_CS_ASSERT: begin
+ if(cfg_cs_early == cnt) begin
+ next_state = FSM_CMD_PHASE;
+ end else begin
+ nxt_cnt = nxt_cnt+1;
+ end
end
- ADDR:
- begin
- spi_en_tx = 1'b1;
- spi_status[2] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
-
- if (tx_done && spi_fall)
- begin
- if (spi_mode_cmd_enb != 0)
- begin
- s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
- counter_tx = {8'h0,8'h8};
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_MODE;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- state_next = MODE;
- end
- else if (spi_data_len != 0)
- begin
- if (do_rx)
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
- if(spi_dummy_rd_len != 0)
- begin
- counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = rx_clk_en;
- state_next = DUMMY_RX;
- end
- else
- begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end
- end
- else
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- spi_en_tx = 1'b1;
-
- if(spi_dummy_wr_len != 0) begin
- counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = tx_clk_en;
- state_next = DUMMY_TX;
- end else begin
- counter_tx = spi_data_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DATA_TX;
- end
- end
- end
- else
- begin
- state_next = WAIT_EDGE;
- end
- end
- end
-
- MODE:
- begin
- spi_en_tx = 1'b1;
- spi_status[3] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- if (tx_done && spi_fall)
- begin
- if (spi_data_len != 0)
- begin
- if (do_rx)
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
- if(spi_dummy_rd_len != 0)
- begin
- counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = rx_clk_en;
- state_next = DUMMY_RX;
- end
- else
- begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end
- end
- else
- begin
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- spi_en_tx = 1'b1;
-
- if(spi_dummy_wr_len != 0) begin
- counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_EMPTY;
- spi_clock_en = tx_clk_en;
- state_next = DUMMY_TX;
- end else begin
- counter_tx = spi_data_len;
- counter_tx_valid = 1'b1;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b1;
- spi_clock_en = tx_clk_en;
- state_next = DATA_TX;
- end
- end
- end
- else
- begin
- state_next = WAIT_EDGE;
- end
- end
- end
-
- DUMMY_TX:
- begin
- spi_en_tx = 1'b1;
- spi_status[4] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
-
- if (tx_done && spi_fall) begin
- if (spi_data_len != 0) begin
- if (do_rx) begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end else begin
- counter_tx = spi_data_len;
+ // WAIT for COMMAND Phase Completed
+ FSM_CMD_PHASE: begin
+ counter_tx = 8'h8;
+ ctrl_data_mux = DATA_CMD;
+ ctrl_data_valid = 1'b1;
+ counter_tx = 'd8;
counter_tx_valid = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
-
- spi_clock_en = tx_clk_en;
spi_en_tx = 1'b1;
- state_next = DATA_TX;
- end
- end
- else
- begin
- eot = 1'b1;
- state_next = WAIT_EDGE;
- end
+ if (tx_data_ready) begin
+ cmd_fifo_rd = 1'b1;
+ case(cfg_spi_seq)
+ P_FSM_C: next_state = FSM_TX_DONE;
+ P_FSM_CW: next_state = FSM_WRITE_CMD;
+ P_FSM_CA: next_state = FSM_ADR_PHASE;
+ P_FSM_CAR: next_state = FSM_ADR_PHASE;
+ P_FSM_CADR: next_state = FSM_ADR_PHASE;
+ P_FSM_CAMR: next_state = FSM_ADR_PHASE;
+ P_FSM_CAMDR: next_state = FSM_ADR_PHASE;
+ P_FSM_CAW: next_state = FSM_ADR_PHASE;
+ P_FSM_CADW: next_state = FSM_ADR_PHASE;
+ P_FSM_CDR: next_state = FSM_DUMMY_PHASE;
+ P_FSM_CDW: next_state = FSM_DUMMY_PHASE;
+ default : next_state = FSM_TX_DONE;
+ endcase
+ end
+ end
+
+ // WAIT for ADDR Command Accepted
+ FSM_ADR_PHASE: begin
+ nxt_cnt = 0;
+ ctrl_data_mux = DATA_ADDR;
+ ctrl_data_valid = 1'b1;
+ counter_tx = (cfg_addr_cnt == P_8BIT) ? 'd8 :
+ (cfg_addr_cnt == P_16BIT) ? 'd16 :
+ (cfg_addr_cnt == P_24BIT) ? 'd24 : 'd20;
+ counter_tx_valid = 1'b1;
+ spi_en_tx = 1'b1;
+ if (tx_data_ready) begin
+ ctrl_data_valid = 1'b0;
+ cmd_fifo_rd = 1'b1;
+ case(cfg_spi_seq)
+ P_FSM_CA: next_state = FSM_TX_DONE;
+ P_FSM_CAR: next_state = FSM_READ_WAIT;
+ P_FSM_CADR: next_state = FSM_DUMMY_PHASE;
+ P_FSM_CAMR: next_state = FSM_MODE_PHASE;
+ P_FSM_CAMDR: next_state = FSM_MODE_PHASE;
+ P_FSM_CAW: next_state = FSM_WRITE_CMD;
+ P_FSM_CADW: next_state = FSM_DUMMY_PHASE;
+ default : next_state = FSM_TX_DONE;
+ endcase
+ end
end
- else
- begin
- ctrl_data_mux = DATA_EMPTY;
- spi_en_tx = 1'b1;
- state_next = DUMMY_TX;
+
+ // WAIT for DUMMY command Accepted
+ FSM_DUMMY_PHASE: begin
+ nxt_cnt = 0;
+ ctrl_data_mux = DATA_EMPTY;
+ ctrl_data_valid = 1'b1;
+ counter_tx_valid = 1'b1;
+ counter_tx = (cfg_dummy_cnt == P_8BIT) ? 'd8 :
+ (cfg_dummy_cnt == P_16BIT) ? 'd16 :
+ (cfg_dummy_cnt == P_24BIT) ? 'd24 : 'd20;
+ spi_en_tx = 1'b1;
+ if (tx_data_ready) begin
+ ctrl_data_valid = 1'b0;
+ case(cfg_spi_seq)
+ P_FSM_CADR: next_state = FSM_READ_WAIT;
+ P_FSM_CAMDR: next_state = FSM_READ_WAIT;
+ P_FSM_CADW: next_state = FSM_WRITE_CMD;
+ P_FSM_CDR: next_state = FSM_READ_WAIT;
+ P_FSM_CDW: next_state = FSM_WRITE_CMD;
+ default : next_state = FSM_CS_DEASEERT;
+ endcase
+ end
end
- end
-
- DUMMY_RX:
- begin
- spi_en_rx = 1'b1;
- spi_status[5] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
-
- if (rx_done && spi_rise) begin
- if (spi_data_len != 0) begin
- if (do_rx) begin
- counter_rx = spi_data_len;
- counter_rx_valid = 1'b1;
- spi_en_rx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DATA_RX;
- end else begin
- counter_tx = spi_data_len;
- counter_tx_valid = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
-
- spi_clock_en = tx_clk_en;
- spi_en_tx = 1'b1;
- state_next = DATA_TX;
- end
- end
- else
- begin
- eot = 1'b1;
- state_next = WAIT_EDGE;
- end
+ // WAIT for MODE command accepted
+ FSM_MODE_PHASE: begin
+ nxt_cnt = 0;
+ ctrl_data_mux = DATA_MODE;
+ ctrl_data_valid = 1'b1;
+ counter_tx_valid = 1'b1;
+ counter_tx = 'd8;
+ spi_en_tx = 1'b1;
+ if (tx_data_ready) begin
+ case(cfg_spi_seq)
+ P_FSM_CAMR: next_state = FSM_READ_WAIT;
+ P_FSM_CAMDR: next_state = FSM_DUMMY_PHASE;
+ default : next_state = FSM_CS_DEASEERT;
+ endcase
+ end
end
- else
- begin
- ctrl_data_mux = DATA_EMPTY;
- spi_en_tx = 1'b1;
- spi_clock_en = rx_clk_en;
- state_next = DUMMY_RX;
+
+ // Wait for WRITE COMMAND ACCEPTED
+ FSM_WRITE_CMD: begin
+ nxt_cnt = 0;
+ ctrl_data_mux = DATA_FIFO;
+ ctrl_data_valid = 1'b1;
+ counter_tx_valid = 1'b1;
+ counter_tx = {5'b0,cfg_data_cnt[7:0],3'b000}; // Convert Byte to Bit Count
+ spi_en_tx = 1'b1;
+ if (tx_data_ready) begin
+ cmd_fifo_rd = 1'b1;
+ next_state = FSM_WRITE_PHASE;
+ end
end
- end
- DATA_TX:
- begin
- spi_status[6] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = tx_clk_en;
- ctrl_data_mux = DATA_FIFO;
- spi_en_tx = 1'b1;
- s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
- if (tx_done && spi_fall) begin
- eot = 1'b1;
- state_next = WAIT_EDGE;
- spi_clock_en = 1'b0;
- end else begin
- state_next = DATA_TX;
+ // Wait for ALL WRITE DATA ACCEPTED
+ FSM_WRITE_PHASE: begin
+ nxt_cnt = 0;
+ ctrl_data_mux = DATA_FIFO;
+ ctrl_data_valid = 1'b1;
+ spi_en_tx = 1'b1;
+ if (tx_done) begin
+ next_state = FSM_CS_DEASEERT;
+ end else if(tx_data_ready && cmd_fifo_empty == 0) begin
+ // Once Current Data is accepted by TX FSM, check FIFO not empty
+ // and read next location
+ cmd_fifo_rd = 1'b1;
+ end
end
+
+ // Wait for Previous TX Completeion
+ FSM_READ_WAIT: begin
+ spi_en_tx = 1'b1;
+ if (tx_done) begin
+ res_fifo_flush = 1; // Flush any stall data in response fifo
+ next_state = FSM_READ_PHASE;
+ end
end
- DATA_RX:
- begin
- spi_status[7] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = rx_clk_en;
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
-
- if (rx_done && spi_rise) begin
- state_next = WAIT_EDGE;
- end else begin
- spi_en_rx = 1'b1;
- state_next = DATA_RX;
+ FSM_READ_PHASE: begin
+ nxt_cnt = 0;
+ counter_rx_valid = 1'b1;
+ counter_rx = {5'b0,cfg_data_cnt[7:0],3'b000}; // Convert Byte to Bit Count
+ spi_en_rx = 1'b1;
+ if(!cmd_fifo_empty) begin
+ // If you see new command request, then abort the current request
+ next_state = FSM_CS_DEASEERT;
+ end else begin
+ if (rx_done && spi_rise) begin
+ next_state = FSM_CS_DEASEERT;
+ end
+ end
end
- end
- WAIT_EDGE:
- begin
- spi_status[8] = 1'b1;
- spi_cs = 1'b0;
- spi_clock_en = 1'b0;
- s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
- eot = 1'b1;
- state_next = IDLE;
- end
- endcase
- end
-assign spi_ack = ((spi_req ==1) && (state == WAIT_EDGE)) ? 1'b1 : 1'b0;
+ // Wait for TX Done
+ FSM_TX_DONE: begin
+ spi_en_tx = 1'b1;
+ if(tx_done) next_state = FSM_CS_DEASEERT;
+ end
+
+ // De-assert CS#
+ FSM_CS_DEASEERT: begin
+ if(cfg_cs_late == cnt) begin
+ next_state = FSM_IDLE;
+ end else begin
+ nxt_cnt = nxt_cnt+1;
+ end
+ end
+ endcase
+end
- always_ff @(posedge clk, negedge rstn)
- begin
- if (rstn == 1'b0)
- begin
- state <= IDLE;
- en_quad_int <= 1'b0;
- do_rx <= 1'b0;
- do_tx <= 1'b0;
- spi_mode <= SPI_QUAD_RX;
- end
- else
- begin
- state <= state_next;
- spi_mode <= s_spi_mode;
- if (spi_qrd || spi_qwr)
- en_quad_int <= 1'b1;
- else if (state_next == IDLE)
- en_quad_int <= 1'b0;
- if (spi_rd || spi_qrd)
- begin
- do_rx <= 1'b1;
- do_tx <= 1'b0;
- end
- else if (spi_wr || spi_qwr)
- begin
- do_rx <= 1'b0;
- do_tx <= 1'b1;
- end
- else if (state_next == IDLE)
- begin
- do_rx <= 1'b0;
- do_tx <= 1'b0;
- end
+
+ always @(posedge clk or negedge rstn) begin
+ if (rstn == 1'b0) begin
+ state <= FSM_IDLE;
+ cnt <= 'h0;
+ end else begin
+ state <= next_state;
+ cnt <= nxt_cnt;
end
end
- assign spi_csn0 = ~spi_csreg[0] | spi_cs;
- assign spi_csn1 = ~spi_csreg[1] | spi_cs;
- assign spi_csn2 = ~spi_csreg[2] | spi_cs;
- assign spi_csn3 = ~spi_csreg[3] | spi_cs;
+ //---------------------------------------------------------------------
+ // Grant Generation Based on FIFO empty, priority given to Master 0
+ // Grant switch happens only at FSM IDLE State
+ // ---------------------------------------------------------------------
+
+ always @(posedge clk or negedge rstn) begin
+ if (rstn == 1'b0) begin
+ gnt <= 0;
+ spi_mode_cmd <= 'h0;
+ cfg_spi_seq <= 'h0;
+ cfg_addr_cnt <= 'h0;
+ cfg_dummy_cnt <= 'h0;
+ cfg_data_cnt <= 'h0;
+ end else begin
+ if(state == FSM_IDLE) begin
+ if(!m0_cmd_fifo_empty) begin
+ cfg_data_cnt <= m0_cmd_fifo_rdata[31:24];
+ cfg_dummy_cnt <= m0_cmd_fifo_rdata[23:22];
+ cfg_addr_cnt <= m0_cmd_fifo_rdata[21:20];
+ cfg_spi_seq <= m0_cmd_fifo_rdata[19:16];
+ spi_mode_cmd <= m0_cmd_fifo_rdata[15:8];
+ gnt <= 2'b01;
+ end
+ else if(!m1_cmd_fifo_empty ) begin
+ cfg_data_cnt <= m1_cmd_fifo_rdata[31:24];
+ cfg_dummy_cnt <= m1_cmd_fifo_rdata[23:22];
+ cfg_addr_cnt <= m1_cmd_fifo_rdata[21:20];
+ cfg_spi_seq <= m1_cmd_fifo_rdata[19:16];
+ spi_mode_cmd <= m1_cmd_fifo_rdata[15:8];
+ gnt <= 2'b10;
+ end
+ end
+ end
+ end
+
+
+ //-----------------------------------------------------------------------
+ // SPI Mode Switch Control Logic
+ // Note: SPI Protocl Start with SPI_STD Mode (Sigle Bit Mode) Base on the
+ // Command, Type it Switch the mode at ADDRESS/DUMMY/DATA Phase
+ // QIOR(0xEB) -> Mode switch at Address Phase
+ // DIOR(0xBB) -> Mode Switch at Address Phase
+ // QOR (0x6B) -> Mode Switch at Data Phase
+ // DOR (0x3B) -> Mode Switch at Data Phase
+ // QPP (0x32) -> Mode Switch at Data Phase
+ // ----------------------------------------------------------------------
+ always @(posedge clk or negedge rstn) begin
+ if (rstn == 1'b0) begin
+ s_spi_mode <= SPI_STD;
+ end else begin
+ if(state == FSM_IDLE) begin // Reset the Mode at IDLE State
+ s_spi_mode <= SPI_STD;
+ end else if(state == FSM_ADR_PHASE && cfg_spi_switch == P_MODE_SWITCH_AT_ADDR) begin
+ s_spi_mode <= cfg_spi_mode;
+ end else if(state == FSM_DUMMY_PHASE && cfg_spi_switch == P_MODE_SWITCH_AT_DATA) begin
+ s_spi_mode <= cfg_spi_mode;
+ end
+ end
+ end
+
+ // SPI Chip Select Logic
+ always @(posedge clk or negedge rstn) begin
+ if (rstn == 1'b0) begin
+ spi_csn0 <= 1'b1;
+ spi_csn1 <= 1'b1;
+ spi_csn2 <= 1'b1;
+ spi_csn3 <= 1'b1;
+ end else begin
+ if(state != FSM_IDLE) begin
+ spi_csn0 <= ~cfg_cs_reg[0];
+ spi_csn1 <= ~cfg_cs_reg[1];
+ spi_csn2 <= ~cfg_cs_reg[2];
+ spi_csn3 <= ~cfg_cs_reg[3];
+ end else begin
+ spi_csn0 <= 1'b1;
+ spi_csn1 <= 1'b1;
+ spi_csn2 <= 1'b1;
+ spi_csn3 <= 1'b1;
+ end
+ end
+ end
endmodule
diff --git a/verilog/rtl/spi_master/src/spim_fifo.sv b/verilog/rtl/spi_master/src/spim_fifo.sv
index bbe3c1a..b16a1b3 100644
--- a/verilog/rtl/spi_master/src/spim_fifo.sv
+++ b/verilog/rtl/spi_master/src/spim_fifo.sv
@@ -15,160 +15,213 @@
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// YiFive cores common library Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// Sync Fifo with full and empty ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : June 7, 2021 ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+
+ SYNC FIFO
+
+ This file is part of the yifive project
+ https://github.com/dineshannayya/yifive_r0.git
+
+ Description: SYNC FIFO
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
-module spim_fifo #(
- parameter DATA_WIDTH = 32, // Data Width
- parameter ADDR_WIDTH = 1, // Address Width
- parameter FIFO_DEPTH = 2 // FIFO DEPTH
-
-)(
- input rstn,
- input srst,
- input clk,
- input wr_en, // Write
- input [DATA_WIDTH-1:0] din,
- output ready_o,
+//-------------------------------------------
+// sync FIFO
+//-----------------------------------------------
+//`timescale 1ns/1ps
- input rd_en, // Read
- output [DATA_WIDTH-1:0] dout,
- output valid_o
-);
+module spim_fifo (clk,
+ reset_n,
+ flush,
+ wr_en,
+ wr_data,
+ full,
+ afull,
+ rd_en,
+ empty,
+ aempty,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input clk, reset_n, wr_en,flush,
+ rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
-reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];
-reg [ADDR_WIDTH-1:0] wptr; // write ptr
-reg [ADDR_WIDTH-1:0] rptr; // write ptr
-reg [ADDR_WIDTH:0] status_cnt; // status counter
-reg empty;
-reg full;
+ // synopsys translate_off
- wire ready_o = ! full;
- wire valid_o = ! empty;
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
- //-----------Code Start---------------------------
- always @ (negedge rstn or posedge clk)
- begin : WRITE_POINTER
- if (rstn==1'b0) begin
- wptr <= 0;
- end else if (srst ) begin
- wptr <= 0;
- end else if (wr_en ) begin
- wptr <= wptr + 1;
+ // synopsys translate_on
+
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] wr_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0] wr_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else begin
+ if(flush) begin
+ wr_ptr <= 0;
+ full_q <= 0;
+ end else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+
+ /************************ read side *****************************/
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if(flush) begin
+ rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end else if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ reg [W-1 : 0] rd_data_q;
+
+ wire [W-1 : 0] rd_data_c = mem[rd_ptr[AW-1:0]];
+ always @(posedge clk) begin
+ rd_data_q <= rd_data_c;
end
- end
+ assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
-always @ (negedge rstn or posedge clk)
-begin : READ_POINTER
- if (rstn==1'b0) begin
- rptr <= 0;
- end else if (srst ) begin
- rptr <= 0;
- end else if (rd_en) begin
- rptr <= rptr + 1;
- end
-end
-always @ (negedge rstn or posedge clk)
-begin : STATUS_COUNTER
- if (rstn==1'b0) begin
- status_cnt <= 0;
- end else if (srst ) begin
- status_cnt <= 0;
- // Read but no write.
- end else if (rd_en && (!wr_en) && (status_cnt != 0)) begin
- status_cnt <= status_cnt - 1;
- // Write but no read.
- end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin
- status_cnt <= status_cnt + 1;
- end
-end
-
-// underflow is not handled
-always @ (negedge rstn or posedge clk)
-begin : EMPTY_FLAG
- if (rstn==1'b0) begin
- empty <= 1;
- end else if (srst ) begin
- empty <= 1;
- // Read but no write.
- end else if (rd_en && (!wr_en) && (status_cnt == 1)) begin
- empty <= 1;
- // Write
- end else if (wr_en) begin
- empty <= 0;
- end else if (status_cnt == 0) begin
- empty <= 1;
- end
-end
-
-// overflow is not handled
-always @ (negedge rstn or posedge clk)
-begin : FULL_FLAG
- if (rstn==1'b0) begin
- full <= 0;
- end else if (srst ) begin
- full <= 0;
- // Write but no read.
- end else if (wr_en && (!rd_en) && (status_cnt == (FIFO_DEPTH-1))) begin
- full <= 1;
- // Read
- end else if (rd_en && (!wr_en) ) begin
- full <= 0;
- end else if (status_cnt == FIFO_DEPTH) begin
- full <= 1;
- end
-end
-assign dout = ram[rptr];
-
-always @ (posedge clk)
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
begin
- if (wr_en) ram[wptr] <= din;
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
end
+always @(posedge clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+// synopsys translate_on
endmodule
diff --git a/verilog/rtl/spi_master/src/spim_if.sv b/verilog/rtl/spi_master/src/spim_if.sv
new file mode 100644
index 0000000..e8c85e0
--- /dev/null
+++ b/verilog/rtl/spi_master/src/spim_if.sv
@@ -0,0 +1,295 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SPI WishBone I/F Module ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// SPI WishBone I/F module ////
+//// This block support following functionality ////
+//// 1. This block Response to Direct Memory Read and ////
+//// Register Write and Read Command ////
+//// 2. In case of Direct Memory Read, It check send the ////
+//// SPI Read command to SPI Ctrl logic and wait for ////
+//// Read data through Response ////
+//// ////
+//// To Do: ////
+//// 1. Add 4 Word Memory Fetch for better Through Put ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - June 30, 2021 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module spim_if #( parameter WB_WIDTH = 32) (
+ input logic mclk,
+ input logic rst_n,
+
+ input logic wbd_stb_i, // strobe/request
+ input logic [WB_WIDTH-1:0] wbd_adr_i, // address
+ input logic wbd_we_i, // write
+ input logic [WB_WIDTH-1:0] wbd_dat_i, // data output
+ input logic [3:0] wbd_sel_i, // byte enable
+ output logic [WB_WIDTH-1:0] wbd_dat_o, // data input
+ output logic wbd_ack_o, // acknowlegement
+ output logic wbd_err_o, // error
+
+
+ // Configuration
+ input logic cfg_fsm_reset,
+ input logic [3:0] cfg_mem_seq, // SPI MEM SEQUENCE
+ input logic [1:0] cfg_addr_cnt, // SPI Addr Count
+ input logic [1:0] cfg_dummy_cnt, // SPI Dummy Count
+ input logic [7:0] cfg_data_cnt, // SPI Read Count
+ input logic [7:0] cfg_cmd_reg, // SPI MEM COMMAND
+ input logic [7:0] cfg_mode_reg, // SPI MODE REG
+ input logic spi_init_done, // SPI internal Init completed
+
+ // Towards Reg I/F
+ output logic spim_reg_req, // Reg Request
+ output logic [3:0] spim_reg_addr, // Reg Address
+ output logic spim_reg_we, // Reg Write/Read Command
+ output logic [3:0] spim_reg_be, // Reg Byte Enable
+ output logic [31:0] spim_reg_wdata, // Reg Write Data
+ input logic spim_reg_ack, // Read Ack
+ input logic [31:0] spim_reg_rdata, // Read Read Data
+
+ // Towards Command FIFO
+ input logic cmd_fifo_empty, // Command FIFO empty
+ output logic cmd_fifo_wr, // Command FIFO Write
+ output logic [33:0] cmd_fifo_wdata, // Command FIFO WData
+
+ // Towards Response FIFO
+ input logic res_fifo_empty, // Response FIFO Empty
+ output logic res_fifo_rd, // Response FIFO Read
+ input logic [31:0] res_fifo_rdata, // Response FIFO Data
+
+ output logic [3:0] state
+ );
+
+//------------------------------------------------
+// Parameter Decleration
+// -----------------------------------------------
+parameter SOC = 1'b1; // START of COMMAND
+parameter EOC = 1'b1; // END of COMMAND
+parameter NOC = 1'b0; // NORMAL COMMAND
+
+// State Machine state
+parameter IDLE = 4'b000;
+parameter ADR_PHASE = 4'b001;
+parameter READ_DATA = 4'b010;
+
+/*************************************************************
+* SPI FSM State Control
+*
+* OPERATION COMMAND SEQUENCE
+*
+* ERASE P4E(0x20) -> COMMAND + ADDRESS
+* ERASE P8E(0x40) -> COMMAND + ADDRESS
+* ERASE SE(0xD8) -> COMMAND + ADDRESS
+* ERASE BE(0x60) -> COMMAND + ADDRESS
+* ERASE BE(0xC7) -> COMMAND
+* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
+* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
+* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
+* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
+* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
+* READ RDID (0x9F) -> COMMAND + READ DATA
+* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
+* WRITE WREN(0x6) -> COMMAND
+* WRITE WRDI -> COMMAND
+* STATUS RDSR(0x05) -> COMMAND + READ DATA
+* STATUS RCR(0x35) -> COMMAND + READ DATA
+* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
+* CONFIG CLSR(0x30) -> COMMAND
+* Power Saving DP(0xB9) -> COMMAND
+* Power Saving RES(0xAB) -> COMMAND + READ DATA
+* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
+* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
+* ********************************************************************/
+
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CA = 4'b0001; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0010; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0011; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0100; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0101; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0110; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b0111; // Command -> Address -> DUMMY + Write Data
+//---------------------------------------------------------
+// Variable declartion
+// -------------------------------------------------------
+logic spim_mem_req ; // Current Request is Direct Memory Read
+
+
+logic spim_wb_req ;
+logic [WB_WIDTH-1:0] spim_wb_wdata ;
+logic [WB_WIDTH-1:0] spim_wb_addr ;
+logic spim_wb_ack ;
+logic spim_wb_we ;
+logic [3:0] spim_wb_be ;
+logic [WB_WIDTH-1:0] spi_mem_rdata ;
+logic [WB_WIDTH-1:0] spim_wb_rdata ;
+
+logic spim_mem_ack ;
+logic [3:0] next_state ;
+
+
+
+ //---------------------------------------------------------------
+ // Address Decoding
+ // 0x0000_0000 - 0x0FFF_FFFF - SPI FLASH MEMORY ACCESS - 256MB
+ // 0x1000_0000 - - SPI Register Access
+ //
+ //
+ // Note: Only Bit[28] is decoding done here, other Bit decoding
+ // will be done inside the wishbone inter-connect
+ // --------------------------------------------------------------
+
+ assign spim_mem_req = ((spim_wb_req) && spim_wb_addr[28] == 1'b0);
+ assign spim_reg_req = ((spim_wb_req) && spim_wb_addr[28] == 1'b1);
+
+ assign spim_reg_addr = spim_wb_addr[5:2];
+ assign spim_reg_wdata = spim_wb_wdata;
+ assign spim_reg_we = spim_wb_we;
+ assign spim_reg_be = spim_wb_be;
+
+ assign wbd_dat_o = spim_wb_rdata;
+ assign wbd_ack_o = spim_wb_ack;
+ assign wbd_err_o = 1'b0;
+
+ // To reduce the load/Timing Wishbone I/F, all the variable are registered
+always_ff @(negedge rst_n or posedge mclk) begin
+ if ( rst_n == 1'b0 ) begin
+ spim_wb_req <= '0;
+ spim_wb_wdata <= '0;
+ spim_wb_rdata <= '0;
+ spim_wb_addr <= '0;
+ spim_wb_be <= '0;
+ spim_wb_we <= '0;
+ spim_wb_ack <= '0;
+ end else begin
+ if(spi_init_done) begin // Wait for internal SPI Init Done
+ spim_wb_req <= wbd_stb_i && ((spim_wb_ack == 0) && (spim_mem_ack ==0) && (spim_reg_ack == 0));
+ spim_wb_wdata <= wbd_dat_i;
+ spim_wb_addr <= wbd_adr_i;
+ spim_wb_be <= wbd_sel_i;
+ spim_wb_we <= wbd_we_i;
+
+
+ if(!spim_wb_we && spim_mem_req && spim_mem_ack)
+ spim_wb_rdata <= spi_mem_rdata;
+ else if (spim_reg_req && spim_reg_ack)
+ spim_wb_rdata <= spim_reg_rdata;
+
+ spim_wb_ack <= (spim_mem_req) ? spim_mem_ack :
+ (spim_reg_req) ? spim_reg_ack : 1'b0;
+ end
+ end
+end
+
+
+always_ff @(negedge rst_n or posedge mclk) begin
+ if ( rst_n == 1'b0 ) begin
+ state <= IDLE;
+ end else begin
+ if(cfg_fsm_reset) state <= IDLE;
+ else state <= next_state;
+ end
+end
+
+/***********************************************************************************
+* This block interface with WishBone Request and Write Command & Read Response FIFO
+* **********************************************************************************/
+
+always_comb
+begin
+ cmd_fifo_wr = '0;
+ cmd_fifo_wdata = '0;
+ res_fifo_rd = 0;
+ spi_mem_rdata = '0;
+
+ spim_mem_ack = 0;
+ next_state = state;
+ case(state)
+ IDLE: begin
+ if(spim_mem_req && cmd_fifo_empty) begin
+ cmd_fifo_wdata = {SOC,NOC,cfg_data_cnt[7:0],cfg_dummy_cnt[1:0],cfg_addr_cnt[1:0],cfg_mem_seq[3:0],cfg_mode_reg[7:0],cfg_cmd_reg[7:0]};
+ cmd_fifo_wr = 1;
+ next_state = ADR_PHASE;
+ end
+ end
+ ADR_PHASE: begin
+ cmd_fifo_wdata = {NOC,EOC,spim_wb_addr[31:0]};
+ cmd_fifo_wr = 1;
+ next_state = READ_DATA;
+ end
+
+
+ READ_DATA: begin
+ if(res_fifo_empty != 1) begin
+ spi_mem_rdata = res_fifo_rdata;
+ res_fifo_rd = 1;
+ spim_mem_ack = 1;
+ next_state = IDLE;
+ end
+ end
+ endcase
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 64cb6f7..f3fa7e1 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -70,349 +70,472 @@
module spim_regs #( parameter WB_WIDTH = 32) (
- input logic mclk,
- input logic rst_n,
+ input logic mclk ,
+ input logic rst_n ,
+ input logic fast_sim_mode , // Set 1 for simulation
- input logic wbd_stb_i, // strobe/request
- input logic [WB_WIDTH-1:0] wbd_adr_i, // address
- input logic wbd_we_i, // write
- input logic [WB_WIDTH-1:0] wbd_dat_i, // data output
- input logic [3:0] wbd_sel_i, // byte enable
- output logic [WB_WIDTH-1:0] wbd_dat_o, // data input
- output logic wbd_ack_o, // acknowlegement
- output logic wbd_err_o, // error
+ output logic [7:0] spi_clk_div ,
+ output logic spi_init_done , // SPI internal Init completed
- output logic [7:0] spi_clk_div,
- input logic [8:0] spi_status,
+ // Status Monitoring
+ input logic [31:0] spi_debug ,
- // Towards SPI TX/RX FSM
+ // Master 0 Configuration
+ output logic cfg_m0_fsm_reset ,
+ output logic [3:0] cfg_m0_cs_reg , // Chip select
+ output logic [1:0] cfg_m0_spi_mode , // Final SPI Mode
+ output logic [1:0] cfg_m0_spi_switch, // SPI Mode Switching Place
+ output logic [3:0] cfg_m0_spi_seq , // SPI SEQUENCE
+ output logic [1:0] cfg_m0_addr_cnt , // SPI Addr Count
+ output logic [1:0] cfg_m0_dummy_cnt , // SPI Dummy Count
+ output logic [7:0] cfg_m0_data_cnt , // SPI Read Count
+ output logic [7:0] cfg_m0_cmd_reg , // SPI MEM COMMAND
+ output logic [7:0] cfg_m0_mode_reg , // SPI MODE REG
+ output logic [3:0] cfg_m1_cs_reg , // Chip select
+ output logic [1:0] cfg_m1_spi_mode , // Final SPI Mode
+ output logic [1:0] cfg_m1_spi_switch, // SPI Mode Switching Place
- output logic spi_req,
- output logic [31:0] spi_addr,
- output logic [5:0] spi_addr_len,
- output logic [7:0] spi_cmd,
- output logic [5:0] spi_cmd_len,
- output logic [7:0] spi_mode_cmd,
- output logic spi_mode_cmd_enb,
- output logic [3:0] spi_csreg,
- output logic [15:0] spi_data_len,
- output logic [15:0] spi_dummy_rd_len,
- output logic [15:0] spi_dummy_wr_len,
- output logic spi_swrst,
- output logic spi_rd,
- output logic spi_wr,
- output logic spi_qrd,
- output logic spi_qwr,
- output logic [31:0] spi_wdata,
- input logic [31:0] spi_rdata,
- input logic spi_ack
+ output logic [1:0] cfg_cs_early , // Amount of cycle early CS asserted
+ output logic [1:0] cfg_cs_late , // Amount of cycle late CS de-asserted
+ // Towards Reg I/F
+ input logic spim_reg_req , // Reg Request
+ input logic [3:0] spim_reg_addr , // Reg Address
+ input logic spim_reg_we , // Reg Write/Read Command
+ input logic [3:0] spim_reg_be , // Reg Byte Enable
+ input logic [31:0] spim_reg_wdata , // Reg Write Data
+ output logic spim_reg_ack , // Read Ack
+ output logic [31:0] spim_reg_rdata , // Read Read Data
+
+ // Towards Command FIFO
+ input logic cmd_fifo_full , // Command FIFO full
+ input logic cmd_fifo_empty , // Command FIFO empty
+ output logic cmd_fifo_wr , // Command FIFO Write
+ output logic [33:0] cmd_fifo_wdata , // Command FIFO WData
+
+ // Towards Response FIFO
+ input logic res_fifo_full , // Response FIFO Empty
+ input logic res_fifo_empty , // Response FIFO Empty
+ output logic res_fifo_rd , // Response FIFO Read
+ input logic [31:0] res_fifo_rdata , // Response FIFO Data
+
+ output logic [3:0] state
);
+//------------------------------------------------
+// Parameter Decleration
+// -----------------------------------------------
+parameter SOC = 1'b1; // START of COMMAND
+parameter EOC = 1'b1; // END of COMMAND
+parameter NOC = 1'b0; // NORMAL COMMAND
+
+parameter BTYPE = 1'b0; // Count is Byte Type
+parameter WTYPE = 1'b1; // Count is Word Type
+
+parameter CNT1 = 2'b00; // BYTE/WORD Count1
+parameter CNT2 = 2'b01; // BYTE/WORD Count2
+parameter CNT3 = 2'b10; // BYTE/WORD Count3
+parameter CNT4 = 2'b11; // BYTE/WORD Count4
+
+
+// Type of command
+parameter NWRITE = 2'b00; // Normal Write
+parameter NREAD = 2'b01; // Normal Read
+parameter DWRITE = 2'b10; // Dummy Write
+parameter DREAD = 2'b11; // Dummy Read
+
+// State Machine state
+parameter FSM_IDLE = 3'b000;
+parameter FSM_ADR_PHASE = 3'b001;
+parameter FSM_WRITE_PHASE = 3'b010;
+parameter FSM_READ_PHASE = 3'b011;
+parameter FSM_READ_BUSY = 3'b100;
+parameter FSM_WRITE_BUSY = 3'b101;
+parameter FSM_ACK_PHASE = 3'b110;
//----------------------------
// Register Decoding
// ---------------------------
-parameter REG_CTRL = 4'b0000;
-parameter REG_CLKDIV = 4'b0001;
-parameter REG_SPICMD = 4'b0010;
-parameter REG_SPIADR = 4'b0011;
-parameter REG_SPILEN = 4'b0100;
-parameter REG_SPIDUM = 4'b0101;
+parameter GLBL_CTRL = 4'b0000;
+parameter MEM_CTRL1 = 4'b0001;
+parameter MEM_CTRL2 = 4'b0010;
+parameter REG_CTRL1 = 4'b0011;
+parameter REG_CTRL2 = 4'b0100;
+parameter REG_SPIADR = 4'b0101;
parameter REG_SPIWDATA = 4'b0110;
parameter REG_SPIRDATA = 4'b0111;
parameter REG_STATUS = 4'b1000;
// Init FSM
-parameter SPI_INIT_IDLE = 3'b000;
-parameter SPI_INIT_CMD_WAIT = 3'b001;
-parameter SPI_INIT_WREN_CMD = 3'b010;
-parameter SPI_INIT_WREN_WAIT = 3'b011;
-parameter SPI_INIT_WRR_CMD = 3'b100;
-parameter SPI_INIT_WRR_WAIT = 3'b101;
+parameter SPI_INIT_PWUP = 3'b000;
+parameter SPI_INIT_IDLE = 3'b001;
+parameter SPI_INIT_CMD_WAIT = 3'b010;
+parameter SPI_INIT_WREN_CMD = 3'b011;
+parameter SPI_INIT_WREN_WAIT = 3'b100;
+parameter SPI_INIT_WRR_CMD = 3'b101;
+parameter SPI_INIT_WRR_WAIT = 3'b110;
+parameter SPI_INIT_WAIT = 3'b111;
+/*************************************************************
+* SPI FSM State Control
+*
+* OPERATION COMMAND SEQUENCE
+*
+* ERASE P4E(0x20) -> COMMAND + ADDRESS
+* ERASE P8E(0x40) -> COMMAND + ADDRESS
+* ERASE SE(0xD8) -> COMMAND + ADDRESS
+* ERASE BE(0x60) -> COMMAND + ADDRESS
+* ERASE BE(0xC7) -> COMMAND
+* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
+* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
+* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
+* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
+* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
+* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
+* READ RDID (0x9F) -> COMMAND + READ DATA
+* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
+* WRITE WREN(0x6) -> COMMAND
+* WRITE WRDI -> COMMAND
+* STATUS RDSR(0x05) -> COMMAND + READ DATA
+* STATUS RCR(0x35) -> COMMAND + READ DATA
+* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
+* CONFIG CLSR(0x30) -> COMMAND
+* Power Saving DP(0xB9) -> COMMAND
+* Power Saving RES(0xAB) -> COMMAND + READ DATA
+* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
+* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
+* ********************************************************************/
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+
+parameter P_FSM_CDR = 4'b1001; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1010; // COMMAND -> DUMMY -> WRITE
+//---------------------------------------------------------
+ parameter P_CS0 = 4'b0001;
+ parameter P_CS1 = 4'b0010;
+ parameter P_CS2 = 4'b0100;
+ parameter P_CS3 = 4'b1000;
+
+ parameter P_SINGLE = 2'b00;
+ parameter P_DOUBLE = 2'b01;
+ parameter P_QUAD = 2'b10;
+
+ parameter P_MODE_SWITCH_IDLE = 2'b00;
+ parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+ parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+
+ parameter P_QOR = 8'h6B;
+ parameter P_QIOR = 8'hEB;
+ parameter P_RES = 8'hAB;
+ parameter P_WEN = 8'h06;
+ parameter P_WRR = 8'h01;
+
+ parameter P_8BIT = 2'b00;
+ parameter P_16BIT = 2'b01;
+ parameter P_24BIT = 2'b10;
+ parameter P_32BIT = 2'b11;
//---------------------------------------------------------
// Variable declartion
// -------------------------------------------------------
-logic spi_init_done ;
-logic [2:0] spi_init_state ;
-logic spim_mem_req ;
-logic spim_reg_req ;
+logic [2:0] spi_init_state ;
+logic spim_reg_req_f ;
+
+logic [1:0] cfg_m1_fsm_reset ;
+logic [3:0] cfg_m1_spi_seq ; // SPI SEQUENCE
+logic [1:0] cfg_m1_addr_cnt ; // SPI Addr Count
+logic [1:0] cfg_m1_dummy_cnt ; // SPI Dummy Count
+logic [7:0] cfg_m1_data_cnt ; // SPI Read Count
+logic [7:0] cfg_m1_cmd_reg ; // SPI MEM COMMAND
+logic [7:0] cfg_m1_mode_reg ; // SPI MODE REG
+logic [31:0] cfg_m1_addr ;
+logic [31:0] cfg_m1_wdata ;
+logic [31:0] cfg_m1_rdata ;
+logic cfg_m1_wrdy ;
+logic cfg_m1_req ;
+
+logic [31:0] reg_rdata ;
-logic spim_wb_req ;
-logic spim_wb_req_l ;
-logic [WB_WIDTH-1:0] spim_wb_wdata ;
-logic [WB_WIDTH-1:0] spim_wb_addr ;
-logic spim_wb_ack ;
-logic spim_wb_we ;
-logic [3:0] spim_wb_be ;
-logic [WB_WIDTH-1:0] spim_reg_rdata ;
-logic [WB_WIDTH-1:0] spim_wb_rdata ;
-logic [WB_WIDTH-1:0] reg_rdata ;
-
-// Control Signal Generated from Reg to SPI Access
-logic reg2spi_req;
-logic [31:0] reg2spi_addr;
-logic [5:0] reg2spi_addr_len;
-logic [31:0] reg2spi_cmd;
-logic [5:0] reg2spi_cmd_len;
-logic [3:0] reg2spi_csreg;
-logic [15:0] reg2spi_data_len;
-logic reg2spi_mode_enb; // mode enable
-logic [7:0] reg2spi_mode; // mode
-logic [15:0] reg2spi_dummy_rd_len;
-logic [15:0] reg2spi_dummy_wr_len;
-logic reg2spi_swrst;
-logic reg2spi_rd;
-logic reg2spi_wr;
-logic reg2spi_qrd;
-logic reg2spi_qwr;
-logic [31:0] reg2spi_wdata;
-//------------------------------------------------------------------
-// Priority given to mem2spi request over Reg2Spi
-
- assign spi_req = (spim_mem_req && !spim_wb_we) ? 1'b1 : reg2spi_req;
- assign spi_addr = (spim_mem_req && !spim_wb_we) ? {spim_wb_addr[23:0],8'h0} : reg2spi_addr;
- assign spi_addr_len = (spim_mem_req && !spim_wb_we) ? 24 : reg2spi_addr_len;
- assign spi_cmd = (spim_mem_req && !spim_wb_we) ? 8'hEB : reg2spi_cmd;
- assign spi_cmd_len = (spim_mem_req && !spim_wb_we) ? 8 : reg2spi_cmd_len;
- assign spi_mode_cmd = (spim_mem_req && !spim_wb_we) ? 8'h00 : reg2spi_mode;
- assign spi_mode_cmd_enb = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_mode_enb;
- assign spi_csreg = (spim_mem_req && !spim_wb_we) ? '1 : reg2spi_csreg;
- assign spi_data_len = (spim_mem_req && !spim_wb_we) ? 'h20 : reg2spi_data_len;
- assign spi_dummy_rd_len = (spim_mem_req && !spim_wb_we) ? 'h20 : reg2spi_dummy_rd_len;
- assign spi_dummy_wr_len = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_dummy_wr_len;
- assign spi_swrst = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_swrst;
- assign spi_rd = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_rd;
- assign spi_wr = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_wr;
- assign spi_qrd = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_qrd;
- assign spi_qwr = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_qwr;
- assign spi_wdata = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_wdata;
+logic [5:0] cur_cnt ;
+logic [5:0] next_cnt ;
+logic [3:0] next_state ;
+logic [31:0] spim_m1_rdata ;
+logic spim_m1_ack ;
+logic spim_m1_rrdy ;
+logic spim_m1_wrdy ;
+logic [9:0] spi_delay_cnt ;
+logic spim_fifo_rdata_req ;
+logic spim_fifo_wdata_req ;
- //---------------------------------------------------------------
- // Address Decoding
- // 0x0000_0000 - 0x0FFF_FFFF - SPI FLASH MEMORY ACCESS - 256MB
- // 0x1000_0000 - - SPI Register Access
- // --------------------------------------------------------------
+//----------------------------------------------
+// Consolidated Register Ack handling
+// 1. Handles Normal Register Read
+// 2. Indirect Memory Write
+// 3. Indirect Memory Read
+//----------------------------------------------
+//
+assign spim_fifo_rdata_req = spim_reg_req && spim_reg_we == 0 && (spim_reg_addr== REG_SPIRDATA);
+assign spim_fifo_wdata_req = spim_reg_req && spim_reg_we == 1 && (spim_reg_addr== REG_SPIWDATA);
- assign spim_mem_req = ((spim_wb_req) && spim_wb_addr[31:28] == 4'b0000);
- assign spim_reg_req = ((spim_wb_req) && spim_wb_addr[31:28] == 4'b0001);
-
-
- assign wbd_dat_o = spim_wb_rdata;
- assign wbd_ack_o = spim_wb_ack;
- assign wbd_err_o = 1'b0;
-
- // To reduce the load/Timing Wishbone I/F, all the variable are registered
always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- spim_wb_req <= '0;
- spim_wb_req_l <= '0;
- spim_wb_wdata <= '0;
- spim_wb_rdata <= '0;
- spim_wb_addr <= '0;
- spim_wb_be <= '0;
- spim_wb_we <= '0;
- spim_wb_ack <= '0;
+ if ( rst_n == 1'b0 ) begin
+ spim_reg_ack <= 1'b0;
+ spim_reg_rdata <= 'h0;
end else begin
- if(spi_init_done) begin // Wait for internal SPI Init Done
- spim_wb_req <= wbd_stb_i && (spi_ack == 0) && (spim_wb_ack==0);
- spim_wb_req_l <= spim_wb_req;
- spim_wb_wdata <= wbd_dat_i;
- spim_wb_addr <= wbd_adr_i;
- spim_wb_be <= wbd_sel_i;
- spim_wb_we <= wbd_we_i;
-
-
- // If there is Reg2Spi read Access, Register the Read Data
- if(reg2spi_req && (reg2spi_rd || reg2spi_qrd ) && spi_ack)
- spim_reg_rdata <= spi_rdata;
-
- if(!spim_wb_we && spim_wb_req && spi_ack)
- spim_wb_rdata <= spi_rdata;
- else if (spim_reg_req)
- spim_wb_rdata <= reg_rdata;
-
- // For safer design, we have generated ack after 2 cycle latter to
- // cross-check current request is towards SPI or not
- spim_wb_ack <= (spi_req && spim_wb_req) ? spi_ack :
- ((spim_wb_ack==0) && spim_wb_req && spim_wb_req_l) ;
- end
+ if(spi_init_done && spim_reg_ack == 0) begin
+ if (spim_fifo_wdata_req && (spim_m1_wrdy == 1)) begin // Indirect Memory Write
+ // If FIFO Write DATA case, Make sure that there no previous pending
+ // need to processed
+ spim_reg_ack <= 1'b1;
+ end else if (spim_reg_req && spim_reg_we && (spim_reg_addr != REG_SPIWDATA)) begin // Indirect memory Write
+ spim_reg_ack <= 1'b1;
+ end else if (spim_fifo_rdata_req && (spim_m1_rrdy == 1)) begin // Indirect mem Read
+ // If FIFO Read DATA case, Make sure that there Data is read from
+ // External SPI Memory
+ spim_reg_ack <= 1'b1;
+ spim_reg_rdata <= reg_rdata;
+ end else if (spim_reg_req && spim_reg_we == 0 && (spim_reg_addr != REG_SPIRDATA)) begin // Normal Read
+ // Read other than FIFO Read Data case
+ spim_reg_ack <= 1'b1;
+ spim_reg_rdata <= reg_rdata;
+ end
+ end else begin
+ spim_reg_ack <= 1'b0;
+ end
end
end
- wire [3:0] reg_addr = spim_wb_addr[5:2];
+ //---------------------------------------------
+ // Manges the initial Config Phase of SPI Memory
+ // 1. Power Up Command - RES(0xAB)
+ // 2. Write Enable Command - WEN (0x06)
+ // 3. WRITE CONFIG Reg - WRR (0x01) - Set Qaud Mode
+ // --------------------------------------------
+
+ logic [9:0] cfg_exit_cnt ;
+ assign cfg_exit_cnt = (fast_sim_mode) ? 100: 1000;
+
integer byte_index;
always_ff @(negedge rst_n or posedge mclk) begin
if ( rst_n == 1'b0 ) begin
- reg2spi_swrst <= 1'b0;
- reg2spi_rd <= 1'b0;
- reg2spi_wr <= 1'b0;
- reg2spi_qrd <= 1'b0;
- reg2spi_qwr <= 1'b0;
- reg2spi_cmd <= 'h0;
- reg2spi_addr <= 'h0;
- reg2spi_cmd_len <= 'h0;
- reg2spi_addr_len <= 'h0;
- reg2spi_data_len <= 'h0;
- reg2spi_wdata <= 'h0;
- reg2spi_mode_enb <= 'h0;
- reg2spi_mode <= 'h0;
- reg2spi_dummy_rd_len <= 'h0;
- reg2spi_dummy_wr_len <= 'h0;
- reg2spi_csreg <= 'h0;
- reg2spi_req <= 'h0;
- spi_clk_div <= 'h2;
+ cfg_m0_fsm_reset <= 'h0;
+ cfg_m0_cs_reg <= P_CS0;
+ cfg_m0_spi_mode <= P_QUAD;
+ cfg_m0_spi_switch <= P_MODE_SWITCH_AT_ADDR;
+ cfg_m0_cmd_reg <= P_QIOR;
+ cfg_m0_mode_reg <= 'h0;
+ cfg_m0_spi_seq[3:0] <= P_FSM_CAMDR;
+ cfg_m0_addr_cnt[1:0] <= P_24BIT;
+ cfg_m0_dummy_cnt[1:0] <= P_16BIT;
+ cfg_m0_data_cnt[7:0] <= 4; // 4 Byte
+
+ cfg_m1_fsm_reset <= 'h0;
+ cfg_m1_cs_reg <= P_CS0;
+ cfg_m1_spi_mode <= P_QUAD;
+ cfg_m1_spi_switch <= P_MODE_SWITCH_AT_DATA;
+ cfg_m1_cmd_reg <= P_QOR;
+ cfg_m1_mode_reg <= 'h0;
+ cfg_m1_spi_seq[3:0] <= P_FSM_CADR;
+ cfg_m1_addr_cnt[1:0] <= P_24BIT;
+ cfg_m1_dummy_cnt[1:0] <= P_8BIT;
+ cfg_m1_data_cnt[7:0] <= 0;
+ cfg_m1_req <= 0;
+ cfg_m1_wrdy <= 1'b0;
+ cfg_m1_wdata <= 'h0; // Not Used
+
+ cfg_cs_early <= 'h1;
+ cfg_cs_late <= 'h1;
+ spi_clk_div <= 'h2;
+
spi_init_done <= 'h0;
- spi_init_state <= SPI_INIT_IDLE;
- end
- else if (spi_init_done == 0) begin
- case(spi_init_state)
- SPI_INIT_IDLE:
- begin
- reg2spi_rd <= 'h0;
- reg2spi_wr <= 'h1; // SPI Write Req
- reg2spi_qrd <= 'h0;
- reg2spi_qwr <= 'h0;
- reg2spi_swrst <= 'h0;
- reg2spi_csreg <= 'h1;
- reg2spi_cmd[7:0] <= 'hAB; // POWER UP command
- reg2spi_mode[7:0] <= 'h0;
- reg2spi_cmd_len <= 'h8;
- reg2spi_addr_len <= 'h0;
- reg2spi_data_len <= 'h0;
- reg2spi_wdata <= 'h0;
- reg2spi_req <= 'h1;
- spi_init_state <= SPI_INIT_CMD_WAIT;
- end
- SPI_INIT_CMD_WAIT:
- begin
- if(spi_ack) begin
- reg2spi_req <= 1'b0;
- spi_init_state <= SPI_INIT_WREN_CMD;
- end
- end
- SPI_INIT_WREN_CMD:
- begin
- reg2spi_rd <= 'h0;
- reg2spi_wr <= 'h1; // SPI Write Req
- reg2spi_qrd <= 'h0;
- reg2spi_qwr <= 'h0;
- reg2spi_swrst <= 'h0;
- reg2spi_csreg <= 'h1;
- reg2spi_cmd[7:0] <= 'h6; // WREN command
- reg2spi_mode[7:0] <= 'h0;
- reg2spi_cmd_len <= 'h8;
- reg2spi_addr_len <= 'h0;
- reg2spi_data_len <= 'h0;
- reg2spi_wdata <= 'h0;
- reg2spi_req <= 'h1;
- spi_init_state <= SPI_INIT_WREN_WAIT;
- end
- SPI_INIT_WREN_WAIT:
- begin
- if(spi_ack) begin
- reg2spi_req <= 1'b0;
- spi_init_state <= SPI_INIT_WRR_CMD;
- end
- end
- SPI_INIT_WRR_CMD:
- begin
- reg2spi_rd <= 'h0;
- reg2spi_wr <= 'h1; // SPI Write Req
- reg2spi_qrd <= 'h0;
- reg2spi_qwr <= 'h0;
- reg2spi_swrst <= 'h0;
- reg2spi_csreg <= 'h1;
- reg2spi_cmd[7:0] <= 'h1; // WRR command
- reg2spi_mode[7:0] <= 'h0;
- reg2spi_cmd_len <= 'h8;
- reg2spi_addr_len <= 'h0;
- reg2spi_data_len <= 'h10;
- reg2spi_wdata <= {8'h0,8'h2,16'h0}; // <sr1[7:0]><<cr1[7:0]><16'h0> cr1[1] = 1 indicate quad mode
- reg2spi_req <= 'h1;
- spi_init_state <= SPI_INIT_WRR_WAIT;
- end
- SPI_INIT_WRR_WAIT:
- begin
- if(spi_ack) begin
- reg2spi_req <= 1'b0;
- spi_init_done <= 'h1;
- end
- end
- endcase
- end else if (spim_reg_req & spim_wb_we )
- begin
- case(reg_addr)
- REG_CTRL:
- begin
- if ( spim_wb_be[0] == 1 )
- begin
- reg2spi_rd <= spim_wb_wdata[0];
- reg2spi_wr <= spim_wb_wdata[1];
- reg2spi_qrd <= spim_wb_wdata[2];
- reg2spi_qwr <= spim_wb_wdata[3];
- reg2spi_swrst <= spim_wb_wdata[4];
- reg2spi_req <= 1'b1;
- end
- if ( spim_wb_be[1] == 1 )
- begin
- reg2spi_csreg <= spim_wb_wdata[11:8];
- end
- end
- REG_CLKDIV:
- if ( spim_wb_be[0] == 1 )
- begin
- spi_clk_div <= spim_wb_wdata[7:0];
- end
- REG_SPICMD: begin
- if ( spim_wb_be[0] == 1 )
- reg2spi_cmd[7:0] <= spim_wb_wdata[7:0];
- if ( spim_wb_be[1] == 1 )
- reg2spi_mode[7:0] <= spim_wb_wdata[15:8];
- end
- REG_SPIADR:
- for (byte_index = 0; byte_index < 4; byte_index = byte_index+1 )
- if ( spim_wb_be[byte_index] == 1 )
- reg2spi_addr[byte_index*8 +: 8] <= spim_wb_wdata[(byte_index*8) +: 8];
- REG_SPILEN:
- begin
- if ( spim_wb_be[0] == 1 ) begin
- reg2spi_mode_enb <= spim_wb_wdata[6];
- reg2spi_cmd_len <= spim_wb_wdata[5:0];
- end
- if ( spim_wb_be[1] == 1 )
- reg2spi_addr_len <= spim_wb_wdata[13:8];
- if ( spim_wb_be[2] == 1 )
- reg2spi_data_len[7:0] <= spim_wb_wdata[23:16];
- if ( spim_wb_be[3] == 1 )
- reg2spi_data_len[15:8] <= spim_wb_wdata[31:24];
- end
- REG_SPIDUM:
- begin
- if ( spim_wb_be[0] == 1 )
- reg2spi_dummy_rd_len[7:0] <= spim_wb_wdata[7:0];
- if ( spim_wb_be[1] == 1 )
- reg2spi_dummy_rd_len[15:8] <= spim_wb_wdata[15:8];
- if ( spim_wb_be[2] == 1 )
- reg2spi_dummy_wr_len[7:0] <= spim_wb_wdata[23:16];
- if ( spim_wb_be[3] == 1 )
- reg2spi_dummy_wr_len[15:8] <= spim_wb_wdata[31:24];
- end
- REG_SPIWDATA: begin
- reg2spi_wdata <= spim_wb_wdata;
- end
- endcase
- end
- else
- begin
- if(spi_ack && spim_reg_req)
- reg2spi_req <= 1'b0;
- end
+ spi_delay_cnt <= 'h0;
+ spim_reg_req_f <= 1'b0;
+ spi_init_state <= SPI_INIT_PWUP;
+ end else begin
+ spim_reg_req_f <= spim_reg_req; // Needed for finding Req Edge
+ if (spi_init_done == 0) begin
+ case(spi_init_state)
+
+ //----------------------------------------------
+ // SPI MEMORY Need minimum 5Us after power up
+ // With 100Mhz, 10ns translated to 500 cycle
+ // We are waiting 1000 cycle
+ // ---------------------------------------------
+ SPI_INIT_PWUP:begin
+ if(spi_delay_cnt == cfg_exit_cnt) begin
+ spi_init_state <= SPI_INIT_IDLE;
+ end else begin
+ spi_delay_cnt <= spi_delay_cnt+1;
+ end
+ end
+
+ SPI_INIT_IDLE:
+ begin
+ cfg_m1_cs_reg <= P_CS0;
+ cfg_m1_spi_mode <= P_SINGLE;
+ cfg_m1_spi_seq[3:0] <= P_FSM_C;
+ cfg_m1_spi_switch <= '0;
+ cfg_m1_cmd_reg <= P_RES;
+ cfg_m1_mode_reg <= 'h0; // Not Used
+ cfg_m1_addr_cnt[1:0] <= 'h0; // Not Used
+ cfg_m1_dummy_cnt[1:0]<= 'h0; // Not Used
+ cfg_m1_data_cnt[7:0] <= 'h0; // Not Used
+ cfg_m1_addr <= 'h0; // Not Used
+ cfg_m1_wdata <= 'h0; // Not Used
+ cfg_m1_req <= 'h1;
+ spi_init_state <= SPI_INIT_CMD_WAIT;
+ end
+ SPI_INIT_CMD_WAIT:
+ begin
+ if(spim_m1_ack) begin
+ cfg_m1_req <= 1'b0;
+ spi_init_state <= SPI_INIT_WREN_CMD;
+ end
+ end
+ SPI_INIT_WREN_CMD:
+ begin
+ cfg_m1_cs_reg <= P_CS0;
+ cfg_m1_spi_mode <= P_SINGLE;
+ cfg_m1_spi_seq[3:0] <= P_FSM_C;
+ cfg_m1_spi_switch <= '0;
+ cfg_m1_cmd_reg <= P_WEN;
+ cfg_m1_mode_reg <= 'h0; // Not Used
+ cfg_m1_addr_cnt[1:0] <= 'h0; // Not Used
+ cfg_m1_dummy_cnt[1:0]<= 'h0; // Not Used
+ cfg_m1_data_cnt[7:0] <= 'h0; // Not Used
+ cfg_m1_addr <= 'h0; // Not Used
+ cfg_m1_wdata <= 'h0; // Not Used
+ cfg_m1_req <= 'h1;
+ spi_init_state <= SPI_INIT_WREN_WAIT;
+ end
+ SPI_INIT_WREN_WAIT:
+ begin
+ if(spim_m1_ack) begin
+ cfg_m1_req <= 1'b0;
+ spi_init_state <= SPI_INIT_WRR_CMD;
+ end
+ end
+ SPI_INIT_WRR_CMD:
+ begin
+ cfg_m1_cs_reg <= P_CS0;
+ cfg_m1_spi_mode <= P_SINGLE;
+ cfg_m1_spi_seq[3:0] <= P_FSM_CW;
+ cfg_m1_spi_switch <= '0;
+ cfg_m1_cmd_reg <= P_WRR;
+ cfg_m1_mode_reg <= 'h0;
+ cfg_m1_addr_cnt[1:0] <= 'h0;
+ cfg_m1_dummy_cnt[1:0]<= 'h0;
+ cfg_m1_data_cnt[7:0] <= 'h2; // 2 Bytes
+ cfg_m1_addr <= 'h0;
+ cfg_m1_wrdy <= 1'b1;
+ cfg_m1_wdata <= {16'h0,8'h2,8'h0}; // <<cr1[7:0]><sr1[7:0]>> cr1[1] = 1 indicate quad mode
+ cfg_m1_req <= 'h1;
+ spi_init_state <= SPI_INIT_WRR_WAIT;
+ end
+ SPI_INIT_WRR_WAIT:
+ begin
+ if(spim_m1_ack) begin
+ spi_delay_cnt <= 'h0;
+ cfg_m1_wrdy <= 1'b0;
+ cfg_m1_req <= 1'b0;
+ spi_init_state <= SPI_INIT_WAIT;
+ end
+ end
+ SPI_INIT_WAIT:
+ begin // SPI MEMORY need 5us after WRR Command
+ if(spi_delay_cnt == cfg_exit_cnt) begin
+ spi_init_done <= 'h1;
+ end else begin
+ spi_delay_cnt <= spi_delay_cnt+1;
+ end
+ end
+ endcase
+ end else if (spim_reg_req && spim_reg_we && spi_init_done )
+ begin
+ case(spim_reg_addr)
+ GLBL_CTRL: begin
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_cs_early <= spim_reg_wdata[1:0];
+ cfg_cs_late <= spim_reg_wdata[3:2];
+ end
+ if ( spim_reg_be[1] == 1 ) begin
+ spi_clk_div <= spim_reg_wdata[15:8];
+ end
+ end
+ MEM_CTRL1: begin // This register control Direct Memory Access Type
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_m0_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
+ cfg_m0_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard
+ cfg_m0_spi_switch<= spim_reg_wdata[7:6]; // Phase where to switch the SPI Mode
+ end
+ if ( spim_reg_be[1] == 1 ) begin
+ cfg_m0_fsm_reset <= spim_reg_wdata[8];
+ end
+ end
+ MEM_CTRL2: begin // This register control Direct Memory Access Type
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_m0_cmd_reg <= spim_reg_wdata[7:0];
+ end
+ if ( spim_reg_be[1] == 1 ) begin
+ cfg_m0_mode_reg <= spim_reg_wdata[15:8];
+ end
+ if ( spim_reg_be[2] == 1 ) begin
+ cfg_m0_spi_seq[3:0] <= spim_reg_wdata[19:16];
+ cfg_m0_addr_cnt[1:0] <= spim_reg_wdata[21:20];
+ cfg_m0_dummy_cnt[1:0]<= spim_reg_wdata[23:22];
+ end
+ if ( spim_reg_be[3] == 1 ) begin
+ cfg_m0_data_cnt[7:0] <= spim_reg_wdata[31:24];
+ end
+ end
+ REG_CTRL1: begin
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_m1_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
+ cfg_m1_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard
+ cfg_m1_spi_switch<= spim_reg_wdata[7:6]; // Phase where to switch the SPI Mode
+ end
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_m1_fsm_reset <= spim_reg_wdata[8];
+ end
+ end
+ REG_CTRL2: begin // This register control Direct Memory Access Type
+ if ( spim_reg_be[0] == 1 ) begin
+ cfg_m1_cmd_reg <= spim_reg_wdata[7:0];
+ end
+ if ( spim_reg_be[1] == 1 ) begin
+ cfg_m1_mode_reg <= spim_reg_wdata[15:8];
+ end
+ if ( spim_reg_be[2] == 1 ) begin
+ cfg_m1_spi_seq[3:0] <= spim_reg_wdata[19:16];
+ cfg_m1_addr_cnt[1:0] <= spim_reg_wdata[21:20];
+ cfg_m1_dummy_cnt[1:0]<= spim_reg_wdata[23:22];
+ end
+ if ( spim_reg_be[3] == 1 ) begin
+ cfg_m1_data_cnt[7:0] <= spim_reg_wdata[31:24];
+ end
+ end
+ REG_SPIADR: begin
+ for (byte_index = 0; byte_index < 4; byte_index = byte_index+1 )
+ if ( spim_reg_be[byte_index] == 1 )
+ cfg_m1_addr[byte_index*8 +: 8] <= spim_reg_wdata[(byte_index*8) +: 8];
+ end
+ endcase
+ end
+ end
end
@@ -422,36 +545,254 @@
begin
reg_rdata = '0;
if(spim_reg_req) begin
- case(reg_addr)
- REG_CTRL:
- reg_rdata[31:0] = { 20'h0,
- reg2spi_csreg,
- 3'b0,
- reg2spi_swrst,
- reg2spi_qwr,
- reg2spi_qrd,
- reg2spi_wr,
- reg2spi_rd};
-
- REG_CLKDIV:
- reg_rdata[31:0] = {24'h0,spi_clk_div};
- REG_SPICMD:
- reg_rdata[31:0] = {16'h0,reg2spi_mode,reg2spi_cmd};
- REG_SPIADR:
- reg_rdata[31:0] = reg2spi_addr;
- REG_SPILEN:
- reg_rdata[31:0] = {reg2spi_data_len,2'b00,reg2spi_addr_len,1'b0,reg2spi_mode_enb,reg2spi_cmd_len};
- REG_SPIDUM:
- reg_rdata[31:0] = {reg2spi_dummy_wr_len,reg2spi_dummy_rd_len};
- REG_SPIWDATA:
- reg_rdata[31:0] = reg2spi_wdata;
- REG_SPIRDATA:
- reg_rdata[31:0] = spim_reg_rdata;
- REG_STATUS:
- reg_rdata[31:0] = {23'h0,spi_status};
+ case(spim_reg_addr)
+ GLBL_CTRL: reg_rdata[31:0] = {16'h0,spi_clk_div,4'h0,cfg_cs_late,cfg_cs_early};
+ MEM_CTRL1: reg_rdata[31:0] = {23'h0,cfg_m0_fsm_reset,cfg_m0_spi_switch,cfg_m0_spi_mode,cfg_m0_cs_reg};
+ MEM_CTRL2: reg_rdata[31:0] = {cfg_m0_data_cnt,cfg_m0_dummy_cnt,cfg_m0_addr_cnt,cfg_m0_spi_seq,cfg_m0_mode_reg,cfg_m0_cmd_reg};
+ REG_CTRL1: reg_rdata[31:0] = {23'h0, cfg_m1_fsm_reset,cfg_m1_spi_switch,cfg_m1_spi_mode,cfg_m1_cs_reg};
+ REG_CTRL2: reg_rdata[31:0] = {cfg_m1_data_cnt,cfg_m1_dummy_cnt,cfg_m1_addr_cnt,cfg_m1_spi_seq,cfg_m1_mode_reg,cfg_m1_cmd_reg};
+ REG_SPIADR: reg_rdata[31:0] = cfg_m1_addr;
+ REG_SPIWDATA: reg_rdata[31:0] = cfg_m1_wdata;
+ REG_SPIRDATA: reg_rdata[31:0] = cfg_m1_rdata;
+ REG_STATUS: reg_rdata[31:0] = spi_debug;
endcase
end
end
+// FSM
+
+always_ff @(negedge rst_n or posedge mclk) begin
+ if ( rst_n == 1'b0 ) begin
+ cur_cnt <= 'h0;
+ state <= FSM_IDLE;
+ end else begin
+ if(cfg_m1_fsm_reset) begin
+ cur_cnt <= 'h0;
+ state <= FSM_IDLE;
+ end else begin
+ cur_cnt <= next_cnt;
+ state <= next_state;
+ end
+ end
+end
+
+/***********************************************************************************
+* This block interface with WishBone Request and Write Command & Read Response FIFO
+* **********************************************************************************/
+
+logic [7:0] cfg_data_cnt;
+logic [31:0] spim_fifo_wdata;
+logic spim_fifo_req;
+assign cfg_data_cnt = cfg_m1_data_cnt-1;
+
+assign spim_fifo_req = cfg_m1_req || spim_fifo_rdata_req || spim_fifo_wdata_req;
+
+assign spim_fifo_wdata = (cfg_m1_req) ? cfg_m1_wdata : spim_reg_wdata;
+
+always_comb
+begin
+ cmd_fifo_wr = '0;
+ cmd_fifo_wdata = '0;
+
+ res_fifo_rd = 0;
+ spim_m1_rdata = '0;
+
+ spim_m1_ack = 0;
+ spim_m1_rrdy = 0;
+ next_cnt = cur_cnt;
+ next_state = state;
+ spim_m1_rrdy = 0;
+ spim_m1_wrdy = 0;
+ cfg_m1_rdata = 0;
+
+ case(state)
+ FSM_IDLE: begin
+ if(spim_fifo_req && cmd_fifo_empty) begin
+ case(cfg_m1_spi_seq)
+ P_FSM_C: begin
+ cmd_fifo_wdata = {SOC,EOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ACK_PHASE;
+ end
+ P_FSM_CW: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_WRITE_PHASE;
+ end
+ P_FSM_CA: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CAR: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CADR: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CAMR: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CAMDR: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CAW: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CADW: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_ADR_PHASE;
+ end
+ P_FSM_CDR: begin
+ cmd_fifo_wdata = {SOC,EOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_READ_PHASE;
+ end
+ P_FSM_CDW: begin
+ cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
+ cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
+ cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
+ next_state = FSM_WRITE_PHASE;
+ end
+
+
+ endcase
+ cmd_fifo_wr = 1;
+ end
+ end
+ // ADDRESS PHASE
+ FSM_ADR_PHASE: begin
+ if(!cmd_fifo_full) begin
+ case(cfg_m1_spi_seq)
+ P_FSM_CA: // COMMAND + ADDRESS PHASE
+ begin
+ cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
+ next_state = FSM_ACK_PHASE;
+ end
+ P_FSM_CAR: // COMMAND + ADDRESS + READ PHASE
+ begin
+ cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_READ_PHASE;
+ end
+ P_FSM_CADR: // COMMAND + ADDRESS + DUMMY + READ PHASE
+ begin
+ cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_READ_PHASE;
+ end
+ P_FSM_CAMR: // COMMAND + ADDRESS + MODE + READ PHASE
+ begin
+ cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_READ_PHASE;
+ end
+ P_FSM_CAMDR: // COMMAND + ADDRESS + MODE + DUMMY + READ PHASE
+ begin
+ cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_READ_PHASE;
+ end
+
+ P_FSM_CAW:begin
+ cmd_fifo_wdata = {NOC,NOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_WRITE_PHASE;
+ end
+ P_FSM_CADW: begin
+ cmd_fifo_wdata = {NOC,NOC,cfg_m1_addr[31:0]};
+ next_cnt = 'h0;
+ next_state = FSM_WRITE_PHASE;
+ end
+ endcase
+ cmd_fifo_wr = 1;
+ end
+ end
+
+ //----------------------------------------------------------
+ // Check Resonse FIFO is not empty then read the data from response fifo
+ // ---------------------------------------------------------
+ FSM_READ_PHASE: begin
+ if(res_fifo_empty != 1 && spim_fifo_rdata_req) begin
+ spim_m1_rrdy = 1;
+ cfg_m1_rdata = res_fifo_rdata;
+ res_fifo_rd = 1;
+ if(cfg_data_cnt[7:2] == cur_cnt) begin
+ next_state = FSM_ACK_PHASE;
+ end else begin
+ next_state = FSM_READ_BUSY;
+ next_cnt = cur_cnt+1;
+ end
+ end
+ end
+ //----------------------------------------------
+ // Wait for Previous Read Data Read
+ // ---------------------------------------------
+ FSM_READ_BUSY: begin
+ spim_m1_rrdy = 0;
+ if(spim_fifo_rdata_req == 0) begin
+ next_state = FSM_READ_PHASE;
+ end
+ end
+
+ //----------------------------------------------------------
+ // Check command FIFO is not full and Write Data is available
+ // ---------------------------------------------------------
+ FSM_WRITE_PHASE: begin
+ if(cmd_fifo_full != 1 && spim_fifo_req) begin
+ // If this a single word config cycle or
+ // in crrent spim_fifo_wr request
+ spim_m1_wrdy = 1;
+ if(cfg_data_cnt[7:2] == cur_cnt) begin
+ cmd_fifo_wdata = {NOC,EOC,spim_fifo_wdata[31:0]};
+ next_state = FSM_ACK_PHASE;
+ end else begin
+ cmd_fifo_wdata = {NOC,NOC,spim_fifo_wdata[31:0]};
+ next_state = FSM_WRITE_BUSY;
+ next_cnt = cur_cnt+1;
+ end
+ cmd_fifo_wr = 1;
+ end
+ end
+ //----------------------------------------------
+ // Wait for NEXT Data Ready
+ // ---------------------------------------------
+ FSM_WRITE_BUSY: begin
+ spim_m1_wrdy = 0;
+ if(spim_fifo_wdata_req == 0) begin
+ next_state = FSM_WRITE_PHASE;
+ end
+ end
+
+ FSM_ACK_PHASE: begin
+ spim_m1_ack = 1;
+ next_state = FSM_IDLE;
+ end
+
+ endcase
+
+
+end
endmodule
diff --git a/verilog/rtl/spi_master/src/spim_rx.sv b/verilog/rtl/spi_master/src/spim_rx.sv
index 7832a8e..6e183de 100644
--- a/verilog/rtl/spi_master/src/spim_rx.sv
+++ b/verilog/rtl/spi_master/src/spim_rx.sv
@@ -69,6 +69,7 @@
(
input logic clk,
input logic rstn,
+ input logic flush,
input logic en,
input logic rx_edge,
output logic rx_done,
@@ -91,20 +92,19 @@
logic [15:0] counter_trgt;
logic [15:0] counter_next;
logic reg_done;
+ logic data_valid_i;
enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
- // RISV is little endian, so data is converted to little endian format
- assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
always_comb
begin
rx_NS = rx_CS;
data_int_next = data_int;
- data_valid = 1'b0;
+ data_valid_i = 1'b0;
counter_next = counter;
case (rx_CS)
@@ -127,14 +127,14 @@
if (rx_done) begin
counter_next = 0;
- data_valid = 1'b1;
+ data_valid_i = 1'b1;
if (data_ready)
rx_NS = IDLE;
else
rx_NS = WAIT_FIFO_DONE;
end else if (reg_done) begin
- data_valid = 1'b1;
+ data_valid_i = 1'b1;
if (~data_ready) begin
// no space in the FIFO, wait for free space
@@ -145,13 +145,13 @@
end
WAIT_FIFO_DONE: begin
- data_valid = 1'b1;
+ data_valid_i = 1'b1;
if (data_ready)
rx_NS = IDLE;
end
WAIT_FIFO: begin
- data_valid = 1'b1;
+ data_valid_i = 1'b1;
if (data_ready)
rx_NS = RECEIVE;
end
@@ -168,20 +168,31 @@
data_int <= '0;
rx_done <= '0;
clk_en_o <= '0;
+ data <= 'b0;
+ data_valid <= 1'b0;
rx_CS <= IDLE;
- end
- else
- begin
- if (rx_edge) begin
- counter <= counter_next;
- data_int <= data_int_next;
- rx_CS <= rx_NS;
- rx_done <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
- clk_en_o <= (rx_NS == RECEIVE);
- end
+ end else if(flush) begin
+ counter <= 0;
+ counter_trgt <= 'h8;
+ data_int <= '0;
+ rx_done <= '0;
+ clk_en_o <= '0;
+ data <= 'b0;
+ data_valid <= 1'b0;
+ rx_CS <= IDLE;
+ end else begin
+ data_valid <= data_valid_i;
+ data <= (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
+ if (rx_edge) begin
+ counter <= counter_next;
+ data_int <= data_int_next;
+ rx_CS <= rx_NS;
+ rx_done <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
+ clk_en_o <= (rx_NS == RECEIVE);
+ end
if (en && counter_in_upd) begin
- counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
- end
+ counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
+ end
end
end
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 98c7a66..fbb25b8 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -25,9 +25,23 @@
//// ////
//// Description ////
//// SPI Master Top module ////
+//// There are two seperate Data path managed here ////
+//// with seperate command and response memory ////
+//// Master-0 : This is targetted for CORE IMEM request ////
+//// and expect only Read access ////
+//// Master-1: This is targetted to CORE DMEM or ////
+//// Indirect Memory access, Both Write and Read ////
+//// accesss are supported. ////
+//// Upto 255 Byte Read/Write Burst supported ////
+//// Limitation: ////
+//// 1. Write/Read FIFO Abort case not managed, expect ////
+//// user to clearly close the busrt request ////
+//// 2. Wishbone Request abort not yet supported. ////
+//// 3. Write access through M0 Port not supported ////
//// ////
//// To Do: ////
-//// nothing ////
+//// 1. Add support for WishBone request timout ////
+//// 2. Add Pre-fetch feature for M0 Port ////
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
@@ -83,54 +97,95 @@
output logic wbd_ack_o, // acknowlegement
output logic wbd_err_o, // error
- output logic [1:0] events_o,
+ output logic [31:0] spi_debug,
// PAD I/f
- input [5:0] io_in ,
- output [5:0] io_out ,
- output [5:0] io_oeb
+ input logic [5:0] io_in ,
+ output logic [5:0] io_out ,
+ output logic [5:0] io_oeb
);
+
+ logic [7:0] spi_clk_div ;
- logic [5:0] spi_clk_div;
- logic spi_req;
- logic spi_ack;
- logic [31:0] spi_addr;
- logic [5:0] spi_addr_len;
- logic [7:0] spi_cmd;
- logic [5:0] spi_cmd_len;
- logic [7:0] spi_mode_cmd;
- logic spi_mode_cmd_enb;
- logic [15:0] spi_data_len;
- logic [15:0] spi_dummy_rd_len;
- logic [15:0] spi_dummy_wr_len;
- logic spi_swrst;
- logic spi_rd;
- logic spi_wr;
- logic spi_qrd;
- logic spi_qwr;
- logic [31:0] spi_wdata;
- logic [31:0] spi_rdata;
- logic [3:0] spi_csreg;
- logic [31:0] spi_data_tx;
- logic spi_data_tx_valid;
- logic spi_data_tx_ready;
- logic [31:0] spi_data_rx;
- logic spi_data_rx_valid;
- logic spi_data_rx_ready;
- logic [8:0] spi_ctrl_status;
- logic [31:0] spi_ctrl_data_tx;
- logic spi_ctrl_data_tx_valid;
- logic spi_ctrl_data_tx_ready;
- logic [31:0] spi_ctrl_data_rx;
- logic spi_ctrl_data_rx_valid;
- logic spi_ctrl_data_rx_ready;
- logic [31:0] reg2spi_wdata;
+ // Master 0 Configuration
+ logic cfg_m0_fsm_reset ;
+ logic [3:0] cfg_m0_cs_reg ; // Chip select
+ logic [1:0] cfg_m0_spi_mode ; // Final SPI Mode
+ logic [1:0] cfg_m0_spi_switch; // SPI Mode Switching Place
+ logic [3:0] cfg_m0_spi_seq ; // SPI SEQUENCE
+ logic [1:0] cfg_m0_addr_cnt ; // SPI Addr Count
+ logic [1:0] cfg_m0_dummy_cnt ; // SPI Dummy Count
+ logic [7:0] cfg_m0_data_cnt ; // SPI Read Count
+ logic [7:0] cfg_m0_cmd_reg ; // SPI MEM COMMAND
+ logic [7:0] cfg_m0_mode_reg ; // SPI MODE REG
- logic s_eot;
+ logic [3:0] cfg_m1_cs_reg ; // Chip select
+ logic [1:0] cfg_m1_spi_mode ; // Final SPI Mode
+ logic [1:0] cfg_m1_spi_switch; // SPI Mode Switching Place
+ logic [1:0] cfg_cs_early ; // Amount of cycle early CS asserted
+ logic [1:0] cfg_cs_late ; // Amount of cycle late CS de-asserted
+
+ // Towards Reg I/F
+ logic spim_reg_req ; // Reg Request
+ logic [3:0] spim_reg_addr ; // Reg Address
+ logic spim_reg_we ; // Reg Write/Read Command
+ logic [3:0] spim_reg_be ; // Reg Byte Enable
+ logic [31:0] spim_reg_wdata ; // Reg Write Data
+ logic spim_reg_ack ; // Read Ack
+ logic [31:0] spim_reg_rdata ; // Read Read Data
+
+ // Towards m0 Command FIFO
+ logic m0_cmd_fifo_full ; // Command FIFO full
+ logic m0_cmd_fifo_empty ; // Command FIFO empty
+ logic m0_cmd_fifo_wr ; // Command FIFO Write
+ logic m0_cmd_fifo_rd ; // Command FIFO read
+ logic [33:0] m0_cmd_fifo_wdata ; // Command FIFO WData
+ logic [33:0] m0_cmd_fifo_rdata ; // Command FIFO RData
+
+ // Towards m0 Response FIFO
+ logic m0_res_fifo_full ; // Response FIFO Empty
+ logic m0_res_fifo_empty ; // Response FIFO Empty
+ logic m0_res_fifo_wr ; // Response FIFO Write
+ logic m0_res_fifo_rd ; // Response FIFO Read
+ logic [31:0] m0_res_fifo_wdata ; // Response FIFO WData
+ logic [31:0] m0_res_fifo_rdata ; // Response FIFO RData
+
+ // Towards m1 Command FIFO
+ logic m1_cmd_fifo_full ; // Command FIFO full
+ logic m1_cmd_fifo_empty ; // Command FIFO empty
+ logic m1_cmd_fifo_wr ; // Command FIFO Write
+ logic m1_cmd_fifo_rd ; // Command FIFO Write
+ logic [33:0] m1_cmd_fifo_wdata ; // Command FIFO WData
+ logic [33:0] m1_cmd_fifo_rdata ; // Command FIFO RData
+
+ // Towards m0 Response FIFO
+ logic m1_res_fifo_full ; // Response FIFO Empty
+ logic m1_res_fifo_empty ; // Response FIFO Empty
+ logic m1_res_fifo_wr ; // Response FIFO Read
+ logic m1_res_fifo_rd ; // Response FIFO Read
+ logic [31:0] m1_res_fifo_wdata ; // Response FIFO WData
+ logic [31:0] m1_res_fifo_rdata ; // Response FIFO RData
+
+ logic m0_res_fifo_flush ; // m0 response fifo flush
+ logic m1_res_fifo_flush ; // m0 response fifo flush
+
+//-----------------------------------------------------
+// SPI Debug monitoring
+// ----------------------------------------------------
+ logic [8:0] spi_ctrl_status ;
+ logic [3:0] m0_state ;
+ logic [3:0] m1_state ;
+ logic [3:0] ctrl_state ;
+
+
+ assign spi_debug = {3'h0,
+ m0_cmd_fifo_full,m0_cmd_fifo_empty,m0_res_fifo_full,m0_res_fifo_empty,
+ m1_cmd_fifo_full,m1_cmd_fifo_empty,m1_res_fifo_full,m1_res_fifo_empty,
+ ctrl_state[3:0], m0_state[3:0],m1_state[3:0],spi_ctrl_status};
//-------------------------------------------------------
// SPI Interface moved inside to support carvel IO pad
@@ -151,6 +206,7 @@
logic spi_sdi2;
logic spi_sdi3;
logic spi_en_tx;
+logic spi_init_done;
assign spi_sdi0 = io_in[2];
@@ -169,17 +225,10 @@
assign io_oeb[1] = 1'b0; // spi_csn
assign io_oeb[2] = !spi_en_tx; // spi_dio0
assign io_oeb[3] = !spi_en_tx; // spi_dio1
-assign io_oeb[4] = !spi_en_tx; // spi_dio2
-assign io_oeb[5] = !spi_en_tx; // spi_dio3
+assign io_oeb[4] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // spi_dio2
+assign io_oeb[5] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // spi_dio3
-
-
- spim_regs
- #(
- .WB_WIDTH(WB_WIDTH)
- )
- u_spim_regs
- (
+spim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if(
.mclk (mclk ),
.rst_n (rst_n ),
@@ -192,59 +241,199 @@
.wbd_ack_o (wbd_ack_o ), // acknowlegement
.wbd_err_o (wbd_err_o ), // error
- .spi_clk_div (spi_clk_div ),
- .spi_status (spi_ctrl_status ),
+ // Configuration
+ .cfg_fsm_reset (cfg_m0_fsm_reset ),
+ .cfg_mem_seq (cfg_m0_spi_seq ), // SPI MEM SEQUENCE
+ .cfg_addr_cnt (cfg_m0_addr_cnt ), // SPI Addr Count
+ .cfg_dummy_cnt (cfg_m0_dummy_cnt ), // SPI Dummy Count
+ .cfg_data_cnt (cfg_m0_data_cnt ), // SPI Read Count
+ .cfg_cmd_reg (cfg_m0_cmd_reg ), // SPI MEM COMMAND
+ .cfg_mode_reg (cfg_m0_mode_reg ), // SPI MODE REG
+ .spi_init_done (spi_init_done ), // SPI internal Init completed
- .spi_req (spi_req ),
- .spi_addr (spi_addr ),
- .spi_addr_len (spi_addr_len ),
- .spi_cmd (spi_cmd ),
- .spi_cmd_len (spi_cmd_len ),
- .spi_mode_cmd (spi_mode_cmd ),
- .spi_mode_cmd_enb (spi_mode_cmd_enb ),
- .spi_csreg (spi_csreg ),
- .spi_data_len (spi_data_len ),
- .spi_dummy_rd_len (spi_dummy_rd_len ),
- .spi_dummy_wr_len (spi_dummy_wr_len ),
- .spi_swrst (spi_swrst ),
- .spi_rd (spi_rd ),
- .spi_wr (spi_wr ),
- .spi_qrd (spi_qrd ),
- .spi_qwr (spi_qwr ),
- .spi_wdata (spi_wdata ),
- .spi_rdata (spi_rdata ),
- .spi_ack (spi_ack )
+ // Towards Reg I/F
+ .spim_reg_req (spim_reg_req ), // Reg Request
+ .spim_reg_addr (spim_reg_addr ), // Reg Address
+ .spim_reg_we (spim_reg_we ), // Reg Write/Read Command
+ .spim_reg_be (spim_reg_be ), // Reg Byte Enable
+ .spim_reg_wdata (spim_reg_wdata ), // Reg Write Data
+ .spim_reg_ack (spim_reg_ack ), // Read Ack
+ .spim_reg_rdata (spim_reg_rdata ), // Read Read Data
+
+ // Towards Command FIFO
+ .cmd_fifo_empty (m0_cmd_fifo_empty ), // Command FIFO empty
+ .cmd_fifo_wr (m0_cmd_fifo_wr ), // Command FIFO Write
+ .cmd_fifo_wdata (m0_cmd_fifo_wdata ), // Command FIFO WData
+
+ // Towards Response FIFO
+ .res_fifo_empty (m0_res_fifo_empty ), // Response FIFO Empty
+ .res_fifo_rd (m0_res_fifo_rd ), // Response FIFO Read
+ .res_fifo_rdata (m0_res_fifo_rdata ), // Response FIFO Data
+
+ .state (m0_state )
+
);
+
+ spim_regs
+ #(
+ .WB_WIDTH(WB_WIDTH)
+ )
+ u_spim_regs
+ (
+ .mclk (mclk ),
+ .rst_n (rst_n ),
+ .fast_sim_mode (1'b0 ),
+
+ .spi_clk_div (spi_clk_div ),
+ .spi_init_done (spi_init_done ),
+
+ .spi_debug (spi_debug ),
+
+ .cfg_m0_fsm_reset (cfg_m0_fsm_reset ),
+ .cfg_m0_cs_reg (cfg_m0_cs_reg ), // Chip select
+ .cfg_m0_spi_mode (cfg_m0_spi_mode ), // Final SPI Mode
+ .cfg_m0_spi_switch (cfg_m0_spi_switch ), // SPI Mode Switching Place
+ .cfg_m0_spi_seq (cfg_m0_spi_seq ), // SPI SEQUENCE
+ .cfg_m0_addr_cnt (cfg_m0_addr_cnt ), // SPI Addr Count
+ .cfg_m0_dummy_cnt (cfg_m0_dummy_cnt ), // SPI Dummy Count
+ .cfg_m0_data_cnt (cfg_m0_data_cnt ), // SPI Read Count
+ .cfg_m0_cmd_reg (cfg_m0_cmd_reg ), // SPI MEM COMMAND
+ .cfg_m0_mode_reg (cfg_m0_mode_reg ), // SPI MODE REG
+
+ .cfg_m1_cs_reg (cfg_m1_cs_reg ), // Chip select
+ .cfg_m1_spi_mode (cfg_m1_spi_mode ), // Final SPI Mode
+ .cfg_m1_spi_switch (cfg_m1_spi_switch ), // SPI Mode Switching Place
+
+ .cfg_cs_early (cfg_cs_early ),
+ .cfg_cs_late (cfg_cs_late ),
+
+ // Towards Reg I/F
+ .spim_reg_req (spim_reg_req ), // Reg Request
+ .spim_reg_addr (spim_reg_addr ), // Reg Address
+ .spim_reg_we (spim_reg_we ), // Reg Write/Read Command
+ .spim_reg_be (spim_reg_be ), // Reg Byte Enable
+ .spim_reg_wdata (spim_reg_wdata ), // Reg Write Data
+ .spim_reg_ack (spim_reg_ack ), // Read Ack
+ .spim_reg_rdata (spim_reg_rdata ), // Read Read Data
+
+ // Towards Command FIFO
+ .cmd_fifo_full (m1_cmd_fifo_full ), // Command FIFO empty
+ .cmd_fifo_empty (m1_cmd_fifo_empty ), // Command FIFO empty
+ .cmd_fifo_wr (m1_cmd_fifo_wr ), // Command FIFO Write
+ .cmd_fifo_wdata (m1_cmd_fifo_wdata ), // Command FIFO WData
+
+ // Towards Response FIFO
+ .res_fifo_full (m1_res_fifo_full ), // Response FIFO Empty
+ .res_fifo_empty (m1_res_fifo_empty ), // Response FIFO Empty
+ .res_fifo_rd (m1_res_fifo_rd ), // Response FIFO Read
+ .res_fifo_rdata (m1_res_fifo_rdata ), // Response FIFO Data
+
+ .state (m1_state )
+
+ );
+
+ // Master 0 Command FIFO
+ spim_fifo #(.W(34), .DP(2)) u_m0_cmd_fifo (
+ .clk (mclk ),
+ .reset_n (rst_n ),
+ .flush (1'b0 ),
+ .wr_en (m0_cmd_fifo_wr ),
+ .wr_data (m0_cmd_fifo_wdata ),
+ .full (m0_cmd_fifo_full ),
+ .afull ( ),
+ .rd_en (m0_cmd_fifo_rd ),
+ .empty (m0_cmd_fifo_empty ),
+ .aempty ( ),
+ .rd_data (m0_cmd_fifo_rdata )
+ );
+
+ // Master 0 Response FIFO
+ spim_fifo #(.W(32), .DP(4)) u_m0_res_fifo (
+ .clk (mclk ),
+ .reset_n (rst_n ),
+ .flush (m0_res_fifo_flush ),
+ .wr_en (m0_res_fifo_wr ),
+ .wr_data (m0_res_fifo_wdata ),
+ .full (m0_res_fifo_full ),
+ .afull ( ),
+ .rd_en (m0_res_fifo_rd ),
+ .empty (m0_res_fifo_empty ),
+ .aempty ( ),
+ .rd_data (m0_res_fifo_rdata )
+ );
+
+ // Master 1 Command FIFO
+ spim_fifo #(.W(34), .DP(4)) u_m1_cmd_fifo (
+ .clk (mclk ),
+ .reset_n (rst_n ),
+ .flush (1'b0 ),
+ .wr_en (m1_cmd_fifo_wr ),
+ .wr_data (m1_cmd_fifo_wdata ),
+ .full (m1_cmd_fifo_full ),
+ .afull ( ),
+ .rd_en (m1_cmd_fifo_rd ),
+ .empty (m1_cmd_fifo_empty ),
+ .aempty ( ),
+ .rd_data (m1_cmd_fifo_rdata )
+ );
+ // Master 1 Response FIFO
+ spim_fifo #(.W(32), .DP(2)) u_m1_res_fifo (
+ .clk (mclk ),
+ .reset_n (rst_n ),
+ .flush (m1_res_fifo_flush ),
+ .wr_en (m1_res_fifo_wr ),
+ .wr_data (m1_res_fifo_wdata ),
+ .full (m1_res_fifo_full ),
+ .afull ( ),
+ .rd_en (m1_res_fifo_rd ),
+ .empty (m1_res_fifo_empty ),
+ .aempty ( ),
+ .rd_data (m1_res_fifo_rdata )
+ );
+
+
spim_ctrl u_spictrl
(
.clk (mclk ),
.rstn (rst_n ),
- .eot ( ),
.spi_clk_div (spi_clk_div ),
.spi_status (spi_ctrl_status ),
- .spi_req (spi_req ),
- .spi_addr (spi_addr ),
- .spi_addr_len (spi_addr_len ),
- .spi_cmd (spi_cmd ),
- .spi_cmd_len (spi_cmd_len ),
- .spi_mode_cmd (spi_mode_cmd ),
- .spi_mode_cmd_enb (spi_mode_cmd_enb ),
- .spi_csreg (spi_csreg ),
- .spi_data_len (spi_data_len ),
- .spi_dummy_rd_len (spi_dummy_rd_len ),
- .spi_dummy_wr_len (spi_dummy_wr_len ),
- .spi_swrst (spi_swrst ),
- .spi_rd (spi_rd ),
- .spi_wr (spi_wr ),
- .spi_qrd (spi_qrd ),
- .spi_qwr (spi_qwr ),
- .spi_wdata (spi_wdata ),
- .spi_rdata (spi_rdata ),
- .spi_ack (spi_ack ),
+ .cfg_m0_cs_reg (cfg_m0_cs_reg ), // Chip select
+ .cfg_m0_spi_mode (cfg_m0_spi_mode ), // Final SPI Mode
+ .cfg_m0_spi_switch (cfg_m0_spi_switch ), // SPI Mode Switching Place
+
+ .cfg_m1_cs_reg (cfg_m1_cs_reg ), // Chip select
+ .cfg_m1_spi_mode (cfg_m1_spi_mode ), // Final SPI Mode
+ .cfg_m1_spi_switch (cfg_m1_spi_switch ), // SPI Mode Switching Place
+
+ .cfg_cs_early (cfg_cs_early ),
+ .cfg_cs_late (cfg_cs_late ),
+
+ .m0_cmd_fifo_empty (m0_cmd_fifo_empty ),
+ .m0_cmd_fifo_rd (m0_cmd_fifo_rd ),
+ .m0_cmd_fifo_rdata (m0_cmd_fifo_rdata ),
+
+ .m0_res_fifo_flush (m0_res_fifo_flush ),
+ .m0_res_fifo_empty (m0_res_fifo_empty ),
+ .m0_res_fifo_full (m0_res_fifo_full ),
+ .m0_res_fifo_wr (m0_res_fifo_wr ),
+ .m0_res_fifo_wdata (m0_res_fifo_wdata ),
+
+ .m1_cmd_fifo_empty (m1_cmd_fifo_empty ),
+ .m1_cmd_fifo_rd (m1_cmd_fifo_rd ),
+ .m1_cmd_fifo_rdata (m1_cmd_fifo_rdata ),
+
+ .m1_res_fifo_flush (m1_res_fifo_flush ),
+ .m1_res_fifo_empty (m1_res_fifo_empty ),
+ .m1_res_fifo_full (m1_res_fifo_full ),
+ .m1_res_fifo_wr (m1_res_fifo_wr ),
+ .m1_res_fifo_wdata (m1_res_fifo_wdata ),
+
+ .ctrl_state (ctrl_state ),
.spi_clk (spi_clk ),
.spi_csn0 (spi_csn0 ),
diff --git a/verilog/rtl/spi_master/src/spim_tx.sv b/verilog/rtl/spi_master/src/spim_tx.sv
index 7a9284c..b904d33 100644
--- a/verilog/rtl/spi_master/src/spim_tx.sv
+++ b/verilog/rtl/spi_master/src/spim_tx.sv
@@ -73,6 +73,7 @@
// General Input
input logic clk, // SPI clock
input logic rstn, // Active low Reset
+ input logic flush, // init the state
input logic en, // Transmit Enable
input logic tx_edge, // Transmiting Edge
output logic tx_done, // Transmission completion
@@ -95,21 +96,26 @@
logic [15:0] counter_trgt ; // counter exit counter
logic tx32b_done ; // 32 bit Transmit done
logic en_quad;
+ logic en_quad_next;
+ logic data_ready_i; // Data in acepted, this for txfifo
enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;
// Indicate 32 bit data done, usefull for readining next 32b from txfifo
- assign tx32b_done = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111)) && tx_edge;
+ assign tx32b_done = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111));
+ assign tx_done = (counter == (counter_trgt-1)) && (tx_CS == TRANSMIT);
+ assign clk_en_o = (tx_NS == TRANSMIT);
always_comb
begin
tx_NS = tx_CS;
data_int_next = data_int;
- data_ready = 1'b0;
+ data_ready_i = 1'b0;
counter_next = counter;
+ en_quad_next = en_quad;
case (tx_CS)
IDLE: begin
@@ -117,37 +123,43 @@
counter_next = '0;
if (en && data_valid) begin
- data_ready = 1'b1;
+ en_quad_next = en_quad_in;
+ data_ready_i = 1'b1;
tx_NS = TRANSMIT;
end
end
TRANSMIT: begin
- counter_next = counter + 1;
- data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
-
- if (tx_done) begin
- counter_next = 0;
- // Check if there is next data
- if (en && data_valid) begin
- data_int_next = txdata;
- data_ready = 1'b1;
- tx_NS = TRANSMIT;
- end else begin
- tx_NS = IDLE;
- end
- end else if (tx32b_done) begin
- if (data_valid) begin
- data_int_next = txdata;
- data_ready = 1'b1;
- end else begin
- tx_NS = IDLE;
- end
- end
+ if ((counter + 1) ==counter_trgt) begin
+ counter_next = 0;
+ // Check if there is next data
+ if (en && data_valid) begin
+ en_quad_next = en_quad_in;
+ data_int_next = txdata;
+ data_ready_i = 1'b1;
+ tx_NS = TRANSMIT;
+ end else begin
+ tx_NS = IDLE;
+ end
+ end else if (tx32b_done) begin
+ if (en && data_valid) begin
+ en_quad_next = en_quad_in;
+ data_int_next = txdata;
+ data_ready_i = 1'b1;
+ tx_NS = TRANSMIT;
+ end else begin
+ tx_NS = IDLE;
+ end
+ end else begin
+ counter_next = counter + 1;
+ data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
+ end
end
endcase
end
+ logic data_ready_f;
+
always_ff @(posedge clk, negedge rstn)
begin
if (~rstn)
@@ -156,32 +168,45 @@
data_int <= 'h0;
tx_CS <= IDLE;
en_quad <= 0;
- tx_done <= '0;
- clk_en_o <= '0;
sdo0 <= '0;
sdo1 <= '0;
- sdo2 <= '0;
- sdo3 <= '0;
+ sdo2 <= '1;
+ sdo3 <= '1;
counter_trgt <= '0;
+ data_ready <= '0;
+ data_ready_f <= 0;
end
- else
- begin
+ else if(flush) begin
+ counter <= 0;
+ data_int <= 'h0;
+ tx_CS <= IDLE;
+ en_quad <= 0;
+ sdo0 <= '0;
+ sdo1 <= '0;
+ sdo2 <= '1;
+ sdo3 <= '1;
+ counter_trgt <= '0;
+ data_ready <= '0;
+ data_ready_f <= 0;
+ end else begin
+ data_ready_f <= data_ready_i;
+ data_ready <= data_ready_f && !data_ready_i; // Generate Pulse at falling edge
if(tx_edge) begin
+ tx_CS <= tx_NS;
counter <= counter_next;
data_int <= data_int_next;
- sdo0 <= (en_quad_in) ? data_int_next[28] : data_int_next[31];
- sdo1 <= (en_quad_in) ? data_int_next[29] : 1'b0;
- sdo2 <= (en_quad_in) ? data_int_next[30] : 1'b0;
- sdo3 <= (en_quad_in) ? data_int_next[31] : 1'b0;
- tx_CS <= tx_NS;
- en_quad <= en_quad_in;
- tx_done <= (counter_next == (counter_trgt -1)) && (tx_NS == TRANSMIT);
- clk_en_o <= (tx_NS == TRANSMIT);
end
// Counter Exit condition, quad mode div-4 , else actual counter
- if (en && data_valid) begin
+ if (en && data_ready_i && tx_edge) begin
+ en_quad <= en_quad_in;
counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
end
+ if(tx_edge && tx_NS == TRANSMIT) begin
+ sdo0 <= (en_quad_next) ? data_int_next[28] : data_int_next[31];
+ sdo1 <= (en_quad_next) ? data_int_next[29] : 1'b0;
+ sdo2 <= (en_quad_next) ? data_int_next[30] : 1'b1; // Protect
+ sdo3 <= (en_quad_next) ? data_int_next[31] : 1'b1; // Hold need to '1'
+ end
end
end
endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 8445819..ae6502e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -16,28 +16,50 @@
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS
-`define UNIT_DELAY #1
+`define UNIT_DELAY #0.1
`ifdef GL
- // Assume default net type to be wire because GL netlists don't have the wire definitions
- `include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
-`else
- `include "user_project_wrapper.v"
- `include "spi_master/src/spim_top.sv"
- `include "spi_master/src/spim_regs.sv"
- `include "spi_master/src/spim_clkgen.sv"
- `include "spi_master/src/spim_ctrl.sv"
- `include "spi_master/src/spim_rx.sv"
- `include "spi_master/src/spim_tx.sv"
- `include "uart/src/uart_core.sv"
- `include "uart/src/uart_cfg.sv"
- `include "uart/src/uart_rxfsm.sv"
- `include "uart/src/uart_txfsm.sv"
- `include "lib/async_fifo_th.sv"
- `include "lib/reset_sync.sv"
- `include "lib/double_sync_low.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
+
+ `include "glbl_cfg.v"
+ `include "sdram.v"
+ `include "spi_master.v"
+ `include "uart.v"
+ `include "wb_interconnect.v"
+ `include "user_project_wrapper.v"
+ `include "syntacore.v"
+ `include "wb_host.v"
+ `include "clk_skew_adjust.v"
+
+`else
+
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
+ `include "spi_master/src/spim_top.sv"
+ `include "spi_master/src/spim_if.sv"
+ `include "spi_master/src/spim_fifo.sv"
+ `include "spi_master/src/spim_regs.sv"
+ `include "spi_master/src/spim_clkgen.sv"
+ `include "spi_master/src/spim_ctrl.sv"
+ `include "spi_master/src/spim_rx.sv"
+ `include "spi_master/src/spim_tx.sv"
+
+ `include "uart/src/uart_core.sv"
+ `include "uart/src/uart_cfg.sv"
+ `include "uart/src/uart_rxfsm.sv"
+ `include "uart/src/uart_txfsm.sv"
+ `include "lib/async_fifo_th.sv"
+ `include "lib/reset_sync.sv"
+ `include "lib/double_sync_low.v"
`include "sdram_ctrl/src/top/sdrc_top.v"
`include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
@@ -52,7 +74,6 @@
`include "lib/registers.v"
`include "lib/clk_ctl.v"
`include "digital_core/src/glbl_cfg.sv"
- `include "digital_core/src/digital_core.sv"
`include "wb_host/src/wb_host.sv"
`include "lib/async_wb.sv"
@@ -61,6 +82,7 @@
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
+
`include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
`include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
`include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
@@ -91,8 +113,9 @@
`include "syntacore/scr1/src/top/scr1_imem_wb.sv"
`include "syntacore/scr1/src/top/scr1_top_wb.sv"
`include "lib/sync_fifo.sv"
+
+ `include "user_project_wrapper.v"
// we are using netlist file for clk_skew_adjust as it has
// standard cell + power pin
`include "gl/clk_skew_adjust.v"
`endif
-
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 404711c..1b2d6b2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,5 +1,6 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
@@ -12,26 +13,106 @@
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Digital core ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is digital core and integrate all the main block ////
+//// here. Following block are integrated here ////
+//// 1. Risc V Core ////
+//// 2. SPI Master ////
+//// 3. Wishbone Cross Bar ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// Initial integration with Risc-V core + ////
+//// Wishbone Cross Bar + SPI Master ////
+//// 0.2 - 17th June 2021, Dinesh A ////
+//// 1. In risc core, wishbone and core domain is ////
+//// created ////
+//// 2. cpu and rtc clock are generated in glbl reg block ////
+//// 3. in wishbone interconnect:- Stagging flop are added ////
+//// at interface to break wishbone timing path ////
+//// 4. buswidth warning are fixed inside spi_master ////
+//// modified rtl files are ////
+//// verilog/rtl/digital_core/src/digital_core.sv ////
+//// verilog/rtl/digital_core/src/glbl_cfg.sv ////
+//// verilog/rtl/lib/wb_stagging.sv ////
+//// verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv ////
+//// verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv ////
+//// verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv ////
+//// verilog/rtl/user_project_wrapper.v ////
+//// verilog/rtl/wb_interconnect/src/wb_interconnect.sv ////
+//// verilog/rtl/spi_master/src/spim_clkgen.sv ////
+//// verilog/rtl/spi_master/src/spim_ctrl.sv ////
+//// 0.3 - 20th June 2021, Dinesh A ////
+//// 1. uart core is integrated ////
+//// 2. 3rd Slave ported added to wishbone interconnect ////
+//// 0.4 - 25th June 2021, Dinesh A ////
+//// Moved the pad logic inside sdram,spi,uart block to ////
+//// avoid logic at digital core level ////
+//// 0.5 - 25th June 2021, Dinesh A ////
+//// Since carvel gives only 16MB address space for user ////
+//// space, we have implemented indirect address select ////
+//// with 8 bit bank select given inside wb_host ////
+//// core Address = {Bank_Sel[7:0], Wb_Address[23:0] ////
+//// caravel user address space is ////
+//// 0x3000_0000 to 0x30FF_FFFF ////
+//// 0.6 - 27th June 2021, Dinesh A ////
+//// Digital core level tie are moved inside IP to avoid ////
+//// power hook up at core level ////
+//// u_risc_top - test_mode & test_rst_n ////
+//// u_intercon - s*_wbd_err_i ////
+//// unused wb_cti_i is removed from u_sdram_ctrl ////
+//// 0.7 - 28th June 2021, Dinesh A ////
+//// wb_interconnect master port are interchanged for ////
+//// better physical placement. ////
+//// m0 - External HOST ////
+//// m1 - RISC IMEM ////
+//// m2 - RISC DMEM ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-`default_nettype wire
-module user_project_wrapper #(
- parameter BITS = 32
-) (
+
+module user_project_wrapper (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
@@ -42,90 +123,678 @@
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
+ input wire wb_clk_i , // System clock
+ input wire user_clock2 , // user Clock
+ input wire wb_rst_i , // Regular Reset signal
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
+ input wire wbs_cyc_i , // strobe/request
+ input wire wbs_stb_i , // strobe/request
+ input wire [WB_WIDTH-1:0] wbs_adr_i , // address
+ input wire wbs_we_i , // write
+ input wire [WB_WIDTH-1:0] wbs_dat_i , // data output
+ input wire [3:0] wbs_sel_i , // byte enable
+ output wire [WB_WIDTH-1:0] wbs_dat_o , // data input
+ output wire wbs_ack_o , // acknowlegement
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Logic Analyzer Signals
+ input wire [127:0] la_data_in ,
+ output wire [127:0] la_data_out ,
+ input wire [127:0] la_oenb ,
+
- // Independent clock (on independent integer divider)
- input user_clock2,
+ // IOs
+ input wire [37:0] io_in ,
+ output wire [37:0] io_out ,
+ output wire [37:0] io_oeb ,
- // User maskable interrupt signals
- output [2:0] user_irq
+ output wire [2:0] user_irq
+
);
+//---------------------------------------------------
+// Local Parameter Declaration
+// --------------------------------------------------
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
+parameter SDR_DW = 8; // SDR Data Width
+parameter SDR_BW = 1; // SDR Byte Width
+parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH
-digital_core u_core (
- `ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V supply
- .vdda2(vdda2), // User area 2 3.3V supply
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
- .vccd1(vccd1), // User area 1 1.8V supply
- .vccd2(vccd2), // User area 2 1.8v supply
- .vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
- `endif
+//---------------------------------------------------------------------
+// Wishbone Risc V Instruction Memory Interface
+//---------------------------------------------------------------------
+wire wbd_riscv_imem_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_imem_adr_i; // address
+wire wbd_riscv_imem_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_i; // data output
+wire [3:0] wbd_riscv_imem_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_o; // data input
+wire wbd_riscv_imem_ack_o; // acknowlegement
+wire wbd_riscv_imem_err_o; // error
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .user_clock2(user_clock2),
+//---------------------------------------------------------------------
+// RISC V Wishbone Data Memory Interface
+//---------------------------------------------------------------------
+wire wbd_riscv_dmem_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i; // address
+wire wbd_riscv_dmem_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i; // data output
+wire [3:0] wbd_riscv_dmem_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o; // data input
+wire wbd_riscv_dmem_ack_o; // acknowlegement
+wire wbd_riscv_dmem_err_o; // error
- // MGMT SoC Wishbone Slave
+//---------------------------------------------------------------------
+// WB HOST Interface
+//---------------------------------------------------------------------
+wire wbd_int_cyc_i; // strobe/request
+wire wbd_int_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_int_adr_i; // address
+wire wbd_int_we_i; // write
+wire [WB_WIDTH-1:0] wbd_int_dat_i; // data output
+wire [3:0] wbd_int_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_int_dat_o; // data input
+wire wbd_int_ack_o; // acknowlegement
+wire wbd_int_err_o; // error
+//---------------------------------------------------------------------
+// SPI Master Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_spim_stb_o; // strobe/request
+wire [WB_WIDTH-1:0] wbd_spim_adr_o; // address
+wire wbd_spim_we_o; // write
+wire [WB_WIDTH-1:0] wbd_spim_dat_o; // data output
+wire [3:0] wbd_spim_sel_o; // byte enable
+wire wbd_spim_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_spim_dat_i; // data input
+wire wbd_spim_ack_i; // acknowlegement
+wire wbd_spim_err_i; // error
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+//---------------------------------------------------------------------
+// SPI Master Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_sdram_stb_o ;
+wire [WB_WIDTH-1:0] wbd_sdram_adr_o ;
+wire wbd_sdram_we_o ; // 1 - Write, 0 - Read
+wire [WB_WIDTH-1:0] wbd_sdram_dat_o ;
+wire [WB_WIDTH/8-1:0] wbd_sdram_sel_o ; // Byte enable
+wire wbd_sdram_cyc_o ;
+wire [2:0] wbd_sdram_cti_o ;
+wire [WB_WIDTH-1:0] wbd_sdram_dat_i ;
+wire wbd_sdram_ack_i ;
- // Logic Analyzer
+//---------------------------------------------------------------------
+// Global Register Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_glbl_stb_o; // strobe/request
+wire [7:0] wbd_glbl_adr_o; // address
+wire wbd_glbl_we_o; // write
+wire [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
+wire [3:0] wbd_glbl_sel_o; // byte enable
+wire wbd_glbl_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input
+wire wbd_glbl_ack_i; // acknowlegement
+wire wbd_glbl_err_i; // error
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
+//---------------------------------------------------------------------
+// Global Register Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_uart_stb_o; // strobe/request
+wire [7:0] wbd_uart_adr_o; // address
+wire wbd_uart_we_o; // write
+wire [7:0] wbd_uart_dat_o; // data output
+wire wbd_uart_sel_o; // byte enable
+wire wbd_uart_cyc_o ;
+wire [7:0] wbd_uart_dat_i; // data input
+wire wbd_uart_ack_i; // acknowlegement
+wire wbd_uart_err_i; // error
- // IO Pads
+//----------------------------------------------------
+// CPU Configuration
+//----------------------------------------------------
+wire cpu_rst_n ;
+wire spi_rst_n ;
+wire sdram_rst_n ;
+wire sdram_clk ;
+wire cpu_clk ;
+wire rtc_clk ;
+wire wbd_clk_int ;
+wire wbd_int_rst_n ;
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
+wire [31:0] fuse_mhartid ;
+wire [15:0] irq_lines ;
+wire soft_irq ;
+
+wire [7:0] cfg_glb_ctrl ;
+wire [31:0] cfg_clk_ctrl1 ;
+wire [31:0] cfg_clk_ctrl2 ;
+wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect
+wire [3:0] cfg_cska_riscv; // clock skew adjust for riscv
+wire [3:0] cfg_cska_uart ; // clock skew adjust for uart
+wire [3:0] cfg_cska_spi ; // clock skew adjust for spi
+wire [3:0] cfg_cska_sdram; // clock skew adjust for sdram
+wire [3:0] cfg_cska_glbl ; // clock skew adjust for global reg
+wire [3:0] cfg_cska_wh ; // clock skew adjust for web host
+
+
+wire wbd_clk_wi ; // clock for wishbone interconnect
+wire wbd_clk_riscv ; // clock for riscv
+wire wbd_clk_uart ; // clock for uart
+wire wbd_clk_spi ; // clock for spi
+wire wbd_clk_sdram ; // clock for sdram
+wire wbd_clk_glbl ; // clock for global reg
+wire wbd_clk_wh ; // clock for global reg
+
+wire [3:0] cfg_cska_sd_co; // clock skew adjust for sdram clock out
+wire [3:0] cfg_cska_sd_ci; // clock skew adjust for sdram clock input
+wire [3:0] cfg_cska_sp_co; // clock skew adjust for SPI clock out
+
+wire io_out_29_ ; // Internally tapped SDRAM clock
+wire io_in_29_ ; // Clock Skewed Pad SDRAM clock
+wire io_in_30_ ; // SPI clock out
+
+//------------------------------------------------
+// Configuration Parameter
+//------------------------------------------------
+wire [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
+wire [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
+wire sdr_init_done ; // Indicate SDRAM Initialisation Done
+wire [3:0] cfg_sdr_tras_d ; // Active to precharge delay
+wire [3:0] cfg_sdr_trp_d ; // Precharge to active delay
+wire [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
+wire cfg_sdr_en ; // Enable SDRAM controller
+wire [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
+wire [12:0] cfg_sdr_mode_reg ;
+wire [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
+wire [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
+wire [3:0] cfg_sdr_twr_d ; // Write recovery delay
+wire [11: 0] cfg_sdr_rfsh ;
+wire [2 : 0] cfg_sdr_rfmax ;
+
+
+
+
+
+/////////////////////////////////////////////////////////
+// Generating acive low wishbone reset
+// //////////////////////////////////////////////////////
+assign wbd_int_rst_n = cfg_glb_ctrl[0];
+assign cpu_rst_n = cfg_glb_ctrl[1];
+assign spi_rst_n = cfg_glb_ctrl[2];
+assign sdram_rst_n = cfg_glb_ctrl[3];
+
+assign cfg_cska_wi = cfg_clk_ctrl1[3:0];
+assign cfg_cska_riscv = cfg_clk_ctrl1[7:4];
+assign cfg_cska_uart = cfg_clk_ctrl1[11:8];
+assign cfg_cska_spi = cfg_clk_ctrl1[15:12];
+assign cfg_cska_sdram = cfg_clk_ctrl1[19:16];
+assign cfg_cska_glbl = cfg_clk_ctrl1[23:20];
+assign cfg_cska_wh = cfg_clk_ctrl1[27:24];
+
+assign cfg_cska_sd_co = cfg_clk_ctrl2[3:0]; // SDRAM clock out control
+assign cfg_cska_sd_ci = cfg_clk_ctrl2[7:4]; // SDRAM clock in control
+assign cfg_cska_sp_co = cfg_clk_ctrl2[11:8];// SPI clock out control
+
+
+wb_host u_wb_host(
+
+ // Master Port
+ .wbm_rst_i (wb_rst_i ),
+ .wbm_clk_i (wb_clk_i ),
+ .wbm_cyc_i (wbs_cyc_i ),
+ .wbm_stb_i (wbs_stb_i ),
+ .wbm_adr_i (wbs_adr_i ),
+ .wbm_we_i (wbs_we_i ),
+ .wbm_dat_i (wbs_dat_i ),
+ .wbm_sel_i (wbs_sel_i ),
+ .wbm_dat_o (wbs_dat_o ),
+ .wbm_ack_o (wbs_ack_o ),
+ .wbm_err_o ( ),
+
+ // Slave Port
+ .wbs_clk_out (wbd_clk_int ),
+ .wbs_clk_i (wbd_clk_wh ),
+ .wbs_cyc_o (wbd_int_cyc_i ),
+ .wbs_stb_o (wbd_int_stb_i ),
+ .wbs_adr_o (wbd_int_adr_i ),
+ .wbs_we_o (wbd_int_we_i ),
+ .wbs_dat_o (wbd_int_dat_i ),
+ .wbs_sel_o (wbd_int_sel_i ),
+ .wbs_dat_i (wbd_int_dat_o ),
+ .wbs_ack_i (wbd_int_ack_o ),
+ .wbs_err_i (wbd_int_err_o ),
+
+ .cfg_glb_ctrl (cfg_glb_ctrl ),
+ .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
+ .cfg_clk_ctrl2 (cfg_clk_ctrl2 ),
+
+ // Logic Analyzer Signals
+ .la_data_in (la_data_in ),
+ .la_data_out (la_data_out ),
+ .la_oenb (la_oenb )
+ );
+
+
+
+
+//------------------------------------------------------------------------------
+// RISC V Core instance
+//------------------------------------------------------------------------------
+scr1_top_wb u_riscv_top (
+ // Reset
+ .pwrup_rst_n (wbd_int_rst_n ),
+ .rst_n (wbd_int_rst_n ),
+ .cpu_rst_n (cpu_rst_n ),
+
+ // Clock
+ .core_clk (cpu_clk ),
+ .rtc_clk (rtc_clk ),
+
+ // Fuses
+ .fuse_mhartid (fuse_mhartid ),
// IRQ
- .user_irq(user_irq)
+ .irq_lines (irq_lines ),
+ .soft_irq (soft_irq ), // TODO - Interrupts
+
+ // DFT
+ // .test_mode (1'b0 ), // Moved inside IP
+ // .test_rst_n (1'b1 ), // Moved inside IP
+
+
+ .wb_rst_n (wbd_int_rst_n ),
+ .wb_clk (wbd_clk_riscv ),
+ // Instruction memory interface
+ .wbd_imem_stb_o (wbd_riscv_imem_stb_i ),
+ .wbd_imem_adr_o (wbd_riscv_imem_adr_i ),
+ .wbd_imem_we_o (wbd_riscv_imem_we_i ),
+ .wbd_imem_dat_o (wbd_riscv_imem_dat_i ),
+ .wbd_imem_sel_o (wbd_riscv_imem_sel_i ),
+ .wbd_imem_dat_i (wbd_riscv_imem_dat_o ),
+ .wbd_imem_ack_i (wbd_riscv_imem_ack_o ),
+ .wbd_imem_err_i (wbd_riscv_imem_err_o ),
+
+ // Data memory interface
+ .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ),
+ .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ),
+ .wbd_dmem_we_o (wbd_riscv_dmem_we_i ),
+ .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ),
+ .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ),
+ .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ),
+ .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ),
+ .wbd_dmem_err_i (wbd_riscv_dmem_err_o )
);
-endmodule // user_project_wrapper
+/*********************************************************
+* SPI Master
+* This is an implementation of an SPI master that is controlled via an AXI bus.
+* It has FIFOs for transmitting and receiving data.
+* It supports both the normal SPI mode and QPI mode with 4 data lines.
+* *******************************************************/
-`default_nettype wire
+spim_top
+#(
+`ifndef SYNTHESIS
+ .WB_WIDTH (WB_WIDTH)
+`endif
+) u_spi_master
+(
+ .mclk (wbd_clk_spi ),
+ .rst_n (spi_rst_n ),
+
+ .wbd_stb_i (wbd_spim_stb_o ),
+ .wbd_adr_i (wbd_spim_adr_o ),
+ .wbd_we_i (wbd_spim_we_o ),
+ .wbd_dat_i (wbd_spim_dat_o ),
+ .wbd_sel_i (wbd_spim_sel_o ),
+ .wbd_dat_o (wbd_spim_dat_i ),
+ .wbd_ack_o (wbd_spim_ack_i ),
+ .wbd_err_o (wbd_spim_err_i ),
+
+ .spi_debug (spi_debug ),
+
+ // Pad Interface
+ .io_in (io_in[35:30] ),
+ .io_out ({io_out[35:31],io_in_30_} ),
+ .io_oeb (io_oeb[35:30] )
+
+);
+
+
+sdrc_top
+ `ifndef SYNTHESIS
+ #(.APP_AW(WB_WIDTH),
+ .APP_DW(WB_WIDTH),
+ .APP_BW(4),
+ .SDR_DW(8),
+ .SDR_BW(1))
+ `endif
+ u_sdram_ctrl (
+ .cfg_sdr_width (cfg_sdr_width ),
+ .cfg_colbits (cfg_colbits ),
+
+ // WB bus
+ .wb_rst_n (wbd_int_rst_n ),
+ .wb_clk_i (wbd_clk_sdram ),
+
+ .wb_stb_i (wbd_sdram_stb_o ),
+ .wb_addr_i (wbd_sdram_adr_o ),
+ .wb_we_i (wbd_sdram_we_o ),
+ .wb_dat_i (wbd_sdram_dat_o ),
+ .wb_sel_i (wbd_sdram_sel_o ),
+ .wb_cyc_i (wbd_sdram_cyc_o ),
+ .wb_ack_o (wbd_sdram_ack_i ),
+ .wb_dat_o (wbd_sdram_dat_i ),
+
+
+ /* Interface to SDRAMs */
+ .sdram_clk (sdram_clk ),
+ .sdram_resetn (sdram_rst_n ),
+
+ /** Pad Interface **/
+ .io_in ({io_in_29_,io_in[28:0]} ),
+ .io_oeb (io_oeb[29:0] ),
+ .io_out ({io_out_29_,io_out[28:0]} ),
+
+ /* Parameters */
+ .sdr_init_done (sdr_init_done ),
+ .cfg_req_depth (cfg_req_depth ), //how many req. buffer should hold
+ .cfg_sdr_en (cfg_sdr_en ),
+ .cfg_sdr_mode_reg (cfg_sdr_mode_reg ),
+ .cfg_sdr_tras_d (cfg_sdr_tras_d ),
+ .cfg_sdr_trp_d (cfg_sdr_trp_d ),
+ .cfg_sdr_trcd_d (cfg_sdr_trcd_d ),
+ .cfg_sdr_cas (cfg_sdr_cas ),
+ .cfg_sdr_trcar_d (cfg_sdr_trcar_d ),
+ .cfg_sdr_twr_d (cfg_sdr_twr_d ),
+ .cfg_sdr_rfsh (cfg_sdr_rfsh ),
+ .cfg_sdr_rfmax (cfg_sdr_rfmax )
+ );
+
+
+wb_interconnect u_intercon (
+ .clk_i (wbd_clk_wi ),
+ .rst_n (wbd_int_rst_n ),
+
+ // Master 0 Interface
+ .m0_wbd_dat_i (wbd_int_dat_i ),
+ .m0_wbd_adr_i (wbd_int_adr_i ),
+ .m0_wbd_sel_i (wbd_int_sel_i ),
+ .m0_wbd_we_i (wbd_int_we_i ),
+ .m0_wbd_cyc_i (wbd_int_cyc_i ),
+ .m0_wbd_stb_i (wbd_int_stb_i ),
+ .m0_wbd_dat_o (wbd_int_dat_o ),
+ .m0_wbd_ack_o (wbd_int_ack_o ),
+ .m0_wbd_err_o (wbd_int_err_o ),
+
+ // Master 0 Interface
+ .m1_wbd_dat_i (wbd_riscv_imem_dat_i ),
+ .m1_wbd_adr_i (wbd_riscv_imem_adr_i ),
+ .m1_wbd_sel_i (wbd_riscv_imem_sel_i ),
+ .m1_wbd_we_i (wbd_riscv_imem_we_i ),
+ .m1_wbd_cyc_i (wbd_riscv_imem_stb_i ),
+ .m1_wbd_stb_i (wbd_riscv_imem_stb_i ),
+ .m1_wbd_dat_o (wbd_riscv_imem_dat_o ),
+ .m1_wbd_ack_o (wbd_riscv_imem_ack_o ),
+ .m1_wbd_err_o (wbd_riscv_imem_err_o ),
+
+ // Master 1 Interface
+ .m2_wbd_dat_i (wbd_riscv_dmem_dat_i ),
+ .m2_wbd_adr_i (wbd_riscv_dmem_adr_i ),
+ .m2_wbd_sel_i (wbd_riscv_dmem_sel_i ),
+ .m2_wbd_we_i (wbd_riscv_dmem_we_i ),
+ .m2_wbd_cyc_i (wbd_riscv_dmem_stb_i ),
+ .m2_wbd_stb_i (wbd_riscv_dmem_stb_i ),
+ .m2_wbd_dat_o (wbd_riscv_dmem_dat_o ),
+ .m2_wbd_ack_o (wbd_riscv_dmem_ack_o ),
+ .m2_wbd_err_o (wbd_riscv_dmem_err_o ),
+
+
+ // Slave 0 Interface
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
+ .s0_wbd_dat_i (wbd_spim_dat_i ),
+ .s0_wbd_ack_i (wbd_spim_ack_i ),
+ .s0_wbd_dat_o (wbd_spim_dat_o ),
+ .s0_wbd_adr_o (wbd_spim_adr_o ),
+ .s0_wbd_sel_o (wbd_spim_sel_o ),
+ .s0_wbd_we_o (wbd_spim_we_o ),
+ .s0_wbd_cyc_o (wbd_spim_cyc_o ),
+ .s0_wbd_stb_o (wbd_spim_stb_o ),
+
+ // Slave 1 Interface
+ // .s1_wbd_err_i (1'b0 ), - Moved inside IP
+ .s1_wbd_dat_i (wbd_sdram_dat_i ),
+ .s1_wbd_ack_i (wbd_sdram_ack_i ),
+ .s1_wbd_dat_o (wbd_sdram_dat_o ),
+ .s1_wbd_adr_o (wbd_sdram_adr_o ),
+ .s1_wbd_sel_o (wbd_sdram_sel_o ),
+ .s1_wbd_we_o (wbd_sdram_we_o ),
+ .s1_wbd_cyc_o (wbd_sdram_cyc_o ),
+ .s1_wbd_stb_o (wbd_sdram_stb_o ),
+
+ // Slave 2 Interface
+ // .s2_wbd_err_i (1'b0 ), - Moved inside IP
+ .s2_wbd_dat_i (wbd_glbl_dat_i ),
+ .s2_wbd_ack_i (wbd_glbl_ack_i ),
+ .s2_wbd_dat_o (wbd_glbl_dat_o ),
+ .s2_wbd_adr_o (wbd_glbl_adr_o ),
+ .s2_wbd_sel_o (wbd_glbl_sel_o ),
+ .s2_wbd_we_o (wbd_glbl_we_o ),
+ .s2_wbd_cyc_o (wbd_glbl_cyc_o ),
+ .s2_wbd_stb_o (wbd_glbl_stb_o ),
+
+ // Slave 3 Interface
+ // .s3_wbd_err_i (1'b0 ), - Moved inside IP
+ .s3_wbd_dat_i (wbd_uart_dat_i ),
+ .s3_wbd_ack_i (wbd_uart_ack_i ),
+ .s3_wbd_dat_o (wbd_uart_dat_o ),
+ .s3_wbd_adr_o (wbd_uart_adr_o ),
+ .s3_wbd_sel_o (wbd_uart_sel_o ),
+ .s3_wbd_we_o (wbd_uart_we_o ),
+ .s3_wbd_cyc_o (wbd_uart_cyc_o ),
+ .s3_wbd_stb_o (wbd_uart_stb_o )
+ );
+
+glbl_cfg u_glbl_cfg (
+
+ .mclk (wbd_clk_glbl ),
+ .reset_n (wbd_int_rst_n ),
+ .user_clock1 (wb_clk_i ),
+ .user_clock2 (user_clock2 ),
+ .device_idcode ( ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (wbd_glbl_stb_o ),
+ .reg_wr (wbd_glbl_we_o ),
+ .reg_addr (wbd_glbl_adr_o ),
+ .reg_wdata (wbd_glbl_dat_o ),
+ .reg_be (wbd_glbl_sel_o ),
+
+ // Outputs
+ .reg_rdata (wbd_glbl_dat_i ),
+ .reg_ack (wbd_glbl_ack_i ),
+
+ // SDRAM Clock
+
+ .sdram_clk (sdram_clk ),
+ .cpu_clk (cpu_clk ),
+ .rtc_clk (rtc_clk ),
+
+ // Risc configuration
+ .fuse_mhartid (fuse_mhartid ),
+ .irq_lines (irq_lines ),
+ .soft_irq (soft_irq ),
+ .user_irq (user_irq ),
+
+ // SDRAM Config
+ .cfg_sdr_width (cfg_sdr_width ),
+ .cfg_colbits (cfg_colbits ),
+
+ /* Parameters */
+ .sdr_init_done (sdr_init_done ),
+ .cfg_req_depth (cfg_req_depth ), //how many req. buffer should hold
+ .cfg_sdr_en (cfg_sdr_en ),
+ .cfg_sdr_mode_reg (cfg_sdr_mode_reg ),
+ .cfg_sdr_tras_d (cfg_sdr_tras_d ),
+ .cfg_sdr_trp_d (cfg_sdr_trp_d ),
+ .cfg_sdr_trcd_d (cfg_sdr_trcd_d ),
+ .cfg_sdr_cas (cfg_sdr_cas ),
+ .cfg_sdr_trcar_d (cfg_sdr_trcar_d ),
+ .cfg_sdr_twr_d (cfg_sdr_twr_d ),
+ .cfg_sdr_rfsh (cfg_sdr_rfsh ),
+ .cfg_sdr_rfmax (cfg_sdr_rfmax )
+
+
+ );
+
+uart_core u_uart_core (
+ .arst_n (wbd_int_rst_n ), // async reset
+ .app_clk (wbd_clk_uart ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (wbd_uart_stb_o ),
+ .reg_wr (wbd_uart_we_o ),
+ .reg_addr (wbd_uart_adr_o[5:2] ),
+ .reg_wdata (wbd_uart_dat_o[7:0] ),
+ .reg_be (wbd_uart_sel_o ),
+
+ // Outputs
+ .reg_rdata (wbd_uart_dat_i[7:0] ),
+ .reg_ack (wbd_uart_ack_i ),
+
+ // Pad interface
+ .io_in (io_in [37:36] ),
+ .io_oeb (io_oeb[37:36] ),
+ .io_out (io_out[37:36] )
+
+ );
+
+////////////////////////////////////////////////////////////////
+// Clock Skew adjust module
+// ///////////////////////////////////////////////////////////
+
+// Wishbone interconnect clock skew control
+clk_skew_adjust u_skew_wi
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_wi ),
+ .clk_out (wbd_clk_wi )
+ );
+
+// riscv clock skew control
+clk_skew_adjust u_skew_riscv
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_riscv ),
+ .clk_out (wbd_clk_riscv )
+ );
+
+// uart clock skew control
+clk_skew_adjust u_skew_uart
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_uart ),
+ .clk_out (wbd_clk_uart )
+ );
+
+// spi clock skew control
+clk_skew_adjust u_skew_spi
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_spi ),
+ .clk_out (wbd_clk_spi )
+ );
+
+// sdram clock skew control
+clk_skew_adjust u_skew_sdram
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_sdram ),
+ .clk_out (wbd_clk_sdram )
+ );
+
+// global clock skew control
+clk_skew_adjust u_skew_glbl
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_glbl ),
+ .clk_out (wbd_clk_glbl )
+ );
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_wh
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_wh ),
+ .clk_out (wbd_clk_wh )
+ );
+
+// SDRAM clock out clock skew control
+clk_skew_adjust u_skew_sd_co
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (io_out_29_ ),
+ .sel (cfg_cska_sd_co ),
+ .clk_out (io_out[29] )
+ );
+
+// Clock Skey for PAD SDRAM clock
+clk_skew_adjust u_skew_sd_ci
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (io_in[29] ),
+ .sel (cfg_cska_sd_ci ),
+ .clk_out (io_in_29_ )
+ );
+
+// Clock Skey for SPI clock out
+clk_skew_adjust u_skew_sp_co
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (io_in_30_ ),
+ .sel (cfg_cska_sp_co ),
+ .clk_out (io_out[30] )
+ );
+
+endmodule : user_project_wrapper
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index e710cfb..def88d3 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -308,7 +308,7 @@
assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
- assign s1_wbd_adr_o = s1_wb_wr.wbd_adr ;
+ assign s1_wbd_adr_o = {4'b0,s1_wb_wr.wbd_adr[27:0]} ;
assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;