full chip sta folder created

commit: 8cc93f72440faf59114a451b619f1769846227d5 [log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com> Tue Nov 23 21:22:32 2021 +0530
committer: dineshannayya <dinesh.annayya@gmail.com> Tue Nov 23 21:22:32 2021 +0530
tree: d682b0d5fb2b8bd1620f7b5b4c548df276476d74
parent: a47e71e64bb104fbc8610304b5be7746e98a95cd [diff]
diff --git a/sta/Makefile b/sta/Makefile
new file mode 100644
index 0000000..535228e
--- /dev/null
+++ b/sta/Makefile

@@ -0,0 +1,51 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = sar_adc wb_interconnect syntacore qspim uart_i2cm_usb_spi pinmux wb_host
+DEF = $(foreach block,$(BLOCKS), ../def/$(block).def)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG = mpw3
+OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_NETLIST_COMMAND = "cd /project/sta && openroad -exit scripts/or_write_verilog.tcl | tee logs/$@.log"
+OPENLANE_STA_COMMAND = "cd /project/sta && sta scripts/sta.tcl | tee logs/sta.log"
+
+all: $(BLOCKS) run_sta
+
+$(DEF) :
+	@echo "Missing $@. Please create a def for that design"
+	@exit 1
+
+$(BLOCKS) : % : ../def/%.def  create 
+	docker run -it  -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_NETLIST_COMMAND)
+
+run_sta: $(BLOCKS)
+	#sta inside the docker is crashing with segmentation fault, so are running sta outside the docker
+	#docker run -it  -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_STA_COMMAND)
+	sta scripts/sta.tcl | tee logs/sta.log
+
+create: clean
+	@echo "create temp directory :)"
+	mkdir -p netlist
+	mkdir -p logs
+	mkdir -p reports
+
+clean:
+	@echo "clean everything :)"
+	rm -rf netlist
+	rm -rf logs
+	rm -rf reports
+

diff --git a/sta/base.sdc b/sta/base.sdc
new file mode 100644
index 0000000..725da1b
--- /dev/null
+++ b/sta/base.sdc

@@ -0,0 +1,1022 @@
+###############################################################################
+# Created by write_sdc
+# Thu Nov 11 07:50:51 2021
+###############################################################################
+current_design user_project_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000  [get_pins {u_wb_host/wbs_clk_out}]
+create_clock -name cpu_clk -period 20.0000    [get_pins {u_wb_host/cpu_clk}]
+create_clock -name rtc_clk -period 50.0000    [get_pins {u_wb_host/rtc_clk}]
+create_clock -name usb_clk -period 20.0000    [get_pins {u_wb_host/usb_clk}]
+create_clock -name line_clk -period 100.0000  [get_pins {u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf/X}]
+
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {line_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
+
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
+
+
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[0]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 1 [get_pins {u_riscv_top/cfg_cska_riscv[0]}]
+set_case_analysis 1 [get_pins {u_riscv_top/cfg_cska_riscv[1]}]
+set_case_analysis 1 [get_pins {u_riscv_top/cfg_cska_riscv[2]}]
+set_case_analysis 0 [get_pins {u_riscv_top/cfg_cska_riscv[3]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+
+set_case_analysis 1 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_wb_host/u_cpu_ref_sel.u_mux/S]
+set_false_path -through [get_pins u_wb_host/u_cpu_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_wb_host/u_wbs_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_wb_host/u_usb_clk_sel.u_mux/S]
+
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i  wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+
+set_multicycle_path -setup -from [get_ports {wbs_adr_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_cyc_i}]  2
+set_multicycle_path -setup -from [get_ports {wbs_dat_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_sel_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_we_i}] 2
+
+set_multicycle_path -hold -from [get_ports {wbs_adr_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_cyc_i}]  2
+set_multicycle_path -hold -from [get_ports {wbs_dat_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_sel_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_we_i}] 2

diff --git a/sta/run_sta b/sta/run_sta
new file mode 100755
index 0000000..744d864
--- /dev/null
+++ b/sta/run_sta

@@ -0,0 +1,35 @@
+
+\rm -rf netlist
+\rm -rf logs
+\rm -rf reports
+mkdir  netlist
+mkdir  logs
+mkdir  reports
+
+echo "#################################################"
+echo "Genenerating Netlist winout power ports"
+echo "#################################################"
+export MERGED_LEF_UNPADDED=../lef/merged_unpadded.lef
+
+export DESIGN_NAME=sar_adc
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=wb_interconnect
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=syntacore
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=qspim
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=uart_i2cm_usb_spi
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=pinmux
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=wb_host
+openroad -exit scripts/or_write_verilog.tcl 
+
+sta scripts/sta.tcl | tee logs/sta.log

diff --git a/sta/scripts/or_write_verilog.tcl b/sta/scripts/or_write_verilog.tcl
new file mode 100644
index 0000000..e24c97e
--- /dev/null
+++ b/sta/scripts/or_write_verilog.tcl

@@ -0,0 +1,30 @@
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set ::env(MERGED_LEF_UNPADDED) "../lef/merged_unpadded.lef"
+set ::env(INPUT_DEF) "../def/$::env(DESIGN_NAME).def"
+set ::env(SAVE_NETLIST) "netlist/$::env(DESIGN_NAME).v"
+
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+    puts stderr $errmsg
+    exit 1
+}
+
+if {[catch {read_def $::env(INPUT_DEF)} errmsg]} {
+    puts stderr $errmsg
+    exit 1
+}
+
+#write_verilog -include_pwr_gnd $::env(SAVE_POWER_NETLIST)
+write_verilog $::env(SAVE_NETLIST)
+

diff --git a/sta/scripts/sta.tcl b/sta/scripts/sta.tcl
new file mode 100644
index 0000000..acfab88
--- /dev/null
+++ b/sta/scripts/sta.tcl

@@ -0,0 +1,131 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "user_project_wrapper"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+read_lib  -corner tt   ../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+
+read_verilog netlist/qspim.v
+read_verilog netlist/syntacore.v  
+read_verilog netlist/uart_i2cm_usb_spi.v
+read_verilog netlist/wb_host.v  
+read_verilog netlist/wb_interconnect.v
+read_verilog netlist/pinmux.v
+read_verilog netlist/sar_adc.v
+read_verilog ../verilog/gl/user_project_wrapper.v  
+
+link_design  $::env(DESIGN_NAME)
+
+
+read_spef -path u_riscv_top         ../spef/scr1_top_wb.spef
+read_spef -path u_pinmux            ../spef/pinmux.spef
+read_spef -path u_qspi_master       ../spef/qspim_top.spef
+read_spef -path u_uart_i2c_usb_spi  ../spef/uart_i2c_usb_spi_top.spef
+read_spef -path u_wb_host           ../spef/wb_host.spef
+read_spef -path u_intercon          ../spef/wb_interconnect.spef
+read_spef                           ../spef/user_project_wrapper.spef  
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > reports/unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power 
+#
+echo "################ CORNER : WC (MAX) TIMING Report ###################"                                              > reports/timing_ss_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks                         -path_delay max                           -corner wc                              >> reports/timing_ss_max.rpt
+
+echo "################ CORNER : WC (MIN) TIMING Report ###################"                                              > reports/timing_ss_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks                         -path_delay min                           -corner wc                              >> reports/timing_ss_min.rpt
+
+echo "################ CORNER : BC (MAX) TIMING Report ###################"                                              > reports/timing_ff_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks                         -path_delay max                           -corner bc                              >> reports/timing_ff_max.rpt
+
+echo "################ CORNER : BC (MIN) TIMING Report ###################"                                              > reports/timing_ff_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks                         -path_delay min                           -corner bc                              >> reports/timing_ff_min.rpt
+
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################"                                              > reports/timing_tt_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks                         -path_delay max                           -corner tt                              >> reports/timing_tt_max.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################"                                              > reports/timing_tt_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks                         -path_delay min                           -corner tt                              >> reports/timing_tt_min.rpt
+
+
+report_checks -path_delay min_max 
+
+#exit
commit	8cc93f72440faf59114a451b619f1769846227d5	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Tue Nov 23 21:22:32 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Tue Nov 23 21:22:32 2021 +0530
tree	d682b0d5fb2b8bd1620f7b5b4c548df276476d74
parent	a47e71e64bb104fbc8610304b5be7746e98a95cd [diff]