def,gds,lef addition
diff --git a/checks/.full_log.log.swp b/checks/.full_log.log.swp
deleted file mode 100644
index 7b64fd1..0000000
--- a/checks/.full_log.log.swp
+++ /dev/null
Binary files differ
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index f0aea1f..95cbf88 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -23,6 +23,9 @@
$script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
$script_dir/../../verilog/rtl/lib/async_fifo_th.sv \
$script_dir/../../verilog/rtl/lib/reset_sync.sv \
+ $script_dir/../../verilog/rtl/lib/double_sync_low.v \
+ $script_dir/../../verilog/rtl/lib/clk_ctl.v \
+ $script_dir/../../verilog/rtl/lib/registers.v \
"
#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
@@ -36,7 +39,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 100.0 100.0]
+set ::env(DIE_AREA) [list 0.0 0.0 400.0 300.0]
diff --git a/openlane/uart/pin_order.cfg b/openlane/uart/pin_order.cfg
index f7b568d..3e6d27a 100644
--- a/openlane/uart/pin_order.cfg
+++ b/openlane/uart/pin_order.cfg
@@ -1,12 +1,12 @@
#BUS_SORT
-#N
+#S
app_clk
arst_n
si
so
-#S
+#N
reg_cs
reg_wr
reg_addr.*
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index ffc604a..f12b8f4 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -36,6 +36,17 @@
m2_wbd_err_o
m2_wbd_cyc_i
+
+s3_wbd_stb_o
+s3_wbd_we_o
+s3_wbd_adr_o.*
+s3_wbd_sel_o.*
+s3_wbd_dat_o.*
+s3_wbd_dat_i.*
+s3_wbd_ack_i
+s3_wbd_err_i
+s3_wbd_cyc_o
+
#N
s0_wbd_stb_o
s0_wbd_we_o
diff --git a/signoff/uart/OPENLANE_VERSION b/signoff/uart/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/uart/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/uart/PDK_SOURCES b/signoff/uart/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/uart/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
new file mode 100644
index 0000000..a2d961d
--- /dev/null
+++ b/signoff/uart/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m24s,0h2m44s,43383.333333333336,0.12,21691.666666666668,36,525.79,2603,0,0,0,0,0,0,0,0,0,0,0,95400,20593,-0.54,-0.54,-0.48,-0.48,-0.69,-37.39,-37.39,-47.96,-47.96,-69.63,70164415,0.0,32.5,20.23,2.87,0.02,-1,2604,2621,453,470,0,0,0,2603,56,0,29,41,183,125,26,685,435,396,18,204,1404,0,1608,93.54536950420955,10.69,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index c03cd8f..b224235 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m26s,0h2m49s,6888.8888888888905,0.36,3444.4444444444453,6,511.24,1240,0,0,0,0,0,0,0,22,0,0,0,496524,14916,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,454520392,0.0,52.93,9.22,42.06,0.0,-1,1005,1557,201,753,0,0,0,1240,247,0,75,5,69,0,0,181,426,402,10,94,4159,0,4253,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m3s,0h2m32s,7222.222222222222,0.36,3611.111111111111,7,521.84,1300,0,0,0,0,0,0,0,24,0,0,0,531752,16160,0.0,0.0,0.0,0.0,-0.08,0.0,0.0,0.0,0.0,-0.09,488578365,0.0,57.91,9.85,43.47,0.0,-1,1054,1627,210,783,0,0,0,1300,247,0,75,14,115,0,0,181,436,422,10,94,4159,0,4253,99.2063492063492,10.08,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 5028dd6..7923d4a 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart
all: ${PATTERNS}
for i in ${PATTERNS}; do \
